Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.72	99.36	99.04	100.00		100.00	100.00	99.89

Total test records in report: 581

T502	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.2455464545	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	41881460 ps
T503	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3740494032	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	28959842 ps
T504	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2359509634	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	186756803 ps
T505	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1092916402	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	71205345 ps
T506	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1754420452	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	150870816 ps
T507	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3227788822	Sep 09 03:53:46 AM UTC 24	Sep 09 03:53:47 AM UTC 24	46388077 ps
T508	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3029130179	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	62822200 ps
T509	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2991337923	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	34823164 ps
T510	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3311277222	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	40520692 ps
T511	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.959867459	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	14156738 ps
T512	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1149687112	Sep 09 03:53:44 AM UTC 24	Sep 09 03:53:47 AM UTC 24	533849808 ps
T513	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3875854672	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	23868259 ps
T514	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1151668856	Sep 09 03:53:46 AM UTC 24	Sep 09 03:53:47 AM UTC 24	32662738 ps
T515	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2981201199	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	108091252 ps
T94	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3401461391	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:47 AM UTC 24	287986727 ps
T516	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3905596125	Sep 09 03:53:46 AM UTC 24	Sep 09 03:53:47 AM UTC 24	27036689 ps
T517	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3056770736	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:48 AM UTC 24	45865629 ps
T518	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.135362062	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:48 AM UTC 24	124834997 ps
T519	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2409556472	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:48 AM UTC 24	143665528 ps
T520	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3493135755	Sep 09 03:53:46 AM UTC 24	Sep 09 03:53:48 AM UTC 24	970077237 ps
T521	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.401689842	Sep 09 03:53:45 AM UTC 24	Sep 09 03:53:48 AM UTC 24	91760284 ps
T522	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.845887004	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:48 AM UTC 24	15649246 ps
T523	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.869149973	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:48 AM UTC 24	25038991 ps
T524	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1142056896	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:48 AM UTC 24	25574686 ps
T525	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1903005230	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	247159699 ps
T526	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1448924996	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	18446946 ps
T527	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.608906431	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	41276080 ps
T528	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.730580196	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	12059200 ps
T529	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3342381617	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	226089873 ps
T530	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2870751679	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	26709293 ps
T531	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2933102809	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	32188034 ps
T532	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1078685687	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:49 AM UTC 24	390132620 ps
T533	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.3388639905	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	25409034 ps
T534	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1861701714	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:50 AM UTC 24	87231618 ps
T535	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1622014340	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	14687235 ps
T536	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.2481390312	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	51388528 ps
T537	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2482464385	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	51747143 ps
T538	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3336517117	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	37503344 ps
T539	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2239717219	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	136265830 ps
T540	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.1708833139	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	22841115 ps
T541	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3308673388	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	42810844 ps
T542	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.544209123	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	25462485 ps
T543	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2365518101	Sep 09 03:53:47 AM UTC 24	Sep 09 03:53:50 AM UTC 24	145045496 ps
T544	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.683782781	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	36048811 ps
T545	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3022201834	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:50 AM UTC 24	14630286 ps
T546	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.33390787	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	14290761 ps
T547	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1818637243	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	10792199 ps
T548	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2899552329	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	19172005 ps
T549	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2145730820	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	46705358 ps
T550	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4095289304	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	16230877 ps
T551	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1027324590	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	58519556 ps
T552	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.88066476	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	15815979 ps
T553	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3772414487	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	22459598 ps
T554	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2396103887	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:50 AM UTC 24	41839569 ps
T555	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3360859655	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:51 AM UTC 24	103404326 ps
T556	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1090578934	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:51 AM UTC 24	16095067 ps
T557	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1950767391	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:51 AM UTC 24	100015044 ps
T558	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3637360191	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:51 AM UTC 24	190100658 ps
T559	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.309310742	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:51 AM UTC 24	353544850 ps
T560	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1788625830	Sep 09 03:53:49 AM UTC 24	Sep 09 03:53:52 AM UTC 24	987809005 ps
T561	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.405863794	Sep 09 03:53:48 AM UTC 24	Sep 09 03:53:52 AM UTC 24	147974699 ps
T562	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2612226118	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	13074341 ps
T563	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.754418704	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	15671270 ps
T564	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1271127485	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	12929467 ps
T565	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1336877685	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	22184537 ps
T566	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2180877492	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	51451233 ps
T567	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1817566392	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	23844395 ps
T568	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3885980575	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	13012805 ps
T569	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.799659814	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	38681831 ps
T570	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2028451000	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	59473491 ps
T571	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.2485442149	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	11763066 ps
T572	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.671645053	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	48735162 ps
T573	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.336705708	Sep 09 03:53:51 AM UTC 24	Sep 09 03:54:00 AM UTC 24	17369113 ps
T574	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3389038402	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	11384203 ps
T575	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3187741426	Sep 09 03:53:50 AM UTC 24	Sep 09 03:53:59 AM UTC 24	40841432 ps
T576	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3843841007	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	11490761 ps
T577	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3470653329	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	11025196 ps
T578	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1615450366	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	41355189 ps
T579	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3263573909	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	16878955 ps
T580	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1945618442	Sep 09 03:53:52 AM UTC 24	Sep 09 03:54:00 AM UTC 24	13527491 ps
T581	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.4012177173	Sep 09 03:53:49 AM UTC 24	Sep 09 03:54:04 AM UTC 24	63620700 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.3591861892
Short name	T8
Test name
Test status
Simulation time	9134615613 ps
CPU time	18.94 seconds
Started	Sep 09 04:25:32 AM UTC 24
Finished	Sep 09 04:25:52 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591861892 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3591861892
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all_with_rand_reset.3949191353
Short name	T11
Test name
Test status
Simulation time	20886707104 ps
CPU time	58.92 seconds
Started	Sep 09 04:25:25 AM UTC 24
Finished	Sep 09 04:26:26 AM UTC 24
Peak memory	205988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3949191353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.rv_timer_stress_all_with_rand_reset.3949191353
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.3295578614
Short name	T1
Test name
Test status
Simulation time	37585463 ps
CPU time	1.12 seconds
Started	Sep 09 04:25:08 AM UTC 24
Finished	Sep 09 04:25:10 AM UTC 24
Peak memory	229300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295578614 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3295578614
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3616515973
Short name	T56
Test name
Test status
Simulation time	4215865056306 ps
CPU time	1233.62 seconds
Started	Sep 09 04:25:45 AM UTC 24
Finished	Sep 09 04:46:34 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616515973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3616515973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.196311649
Short name	T34
Test name
Test status
Simulation time	101232220404 ps
CPU time	78.66 seconds
Started	Sep 09 04:25:53 AM UTC 24
Finished	Sep 09 04:27:14 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196311649 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.196311649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.2843023573
Short name	T171
Test name
Test status
Simulation time	721562978347 ps
CPU time	1672.08 seconds
Started	Sep 09 04:32:35 AM UTC 24
Finished	Sep 09 05:00:44 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843023573 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.2843023573
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.2610727893
Short name	T159
Test name
Test status
Simulation time	1899850665020 ps
CPU time	2455.5 seconds
Started	Sep 09 04:40:55 AM UTC 24
Finished	Sep 09 05:22:16 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610727893 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.2610727893
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.89324535
Short name	T19
Test name
Test status
Simulation time	237276858 ps
CPU time	1.24 seconds
Started	Sep 09 03:53:34 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89324535 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.89324535
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.3925160281
Short name	T216
Test name
Test status
Simulation time	1589744799880 ps
CPU time	4051.43 seconds
Started	Sep 09 04:28:19 AM UTC 24
Finished	Sep 09 05:36:34 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925160281 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.3925160281
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.1870608490
Short name	T235
Test name
Test status
Simulation time	1637850807535 ps
CPU time	1245.57 seconds
Started	Sep 09 04:31:16 AM UTC 24
Finished	Sep 09 04:52:15 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870608490 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.1870608490
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.4024270379
Short name	T106
Test name
Test status
Simulation time	385464645885 ps
CPU time	1105.35 seconds
Started	Sep 09 04:25:56 AM UTC 24
Finished	Sep 09 04:44:35 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024270379 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.4024270379
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1500438429
Short name	T193
Test name
Test status
Simulation time	738392442179 ps
CPU time	6003.35 seconds
Started	Sep 09 04:46:50 AM UTC 24
Finished	Sep 09 06:27:54 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500438429 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1500438429
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1037796399
Short name	T323
Test name
Test status
Simulation time	2270638827860 ps
CPU time	4233.69 seconds
Started	Sep 09 04:45:57 AM UTC 24
Finished	Sep 09 05:57:16 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037796399 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1037796399
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.647140852
Short name	T69
Test name
Test status
Simulation time	37756636 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:33 AM UTC 24
Finished	Sep 09 03:53:35 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647140852 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.647140852
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.1032379389
Short name	T57
Test name
Test status
Simulation time	794047532868 ps
CPU time	889.46 seconds
Started	Sep 09 04:35:52 AM UTC 24
Finished	Sep 09 04:50:50 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032379389 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.1032379389
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.446480109
Short name	T55
Test name
Test status
Simulation time	747598951229 ps
CPU time	670.61 seconds
Started	Sep 09 04:30:34 AM UTC 24
Finished	Sep 09 04:41:52 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446480109 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.446480109
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.3267970052
Short name	T172
Test name
Test status
Simulation time	3604463706378 ps
CPU time	1712.1 seconds
Started	Sep 09 04:32:13 AM UTC 24
Finished	Sep 09 05:01:02 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267970052 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.3267970052
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2632079020
Short name	T187
Test name
Test status
Simulation time	458312581338 ps
CPU time	765.25 seconds
Started	Sep 09 04:41:39 AM UTC 24
Finished	Sep 09 04:54:33 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632079020 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2632079020
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.3122568730
Short name	T127
Test name
Test status
Simulation time	99630460682 ps
CPU time	300.8 seconds
Started	Sep 09 04:25:50 AM UTC 24
Finished	Sep 09 04:30:55 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122568730 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3122568730
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.2057375990
Short name	T198
Test name
Test status
Simulation time	583137039817 ps
CPU time	1318.93 seconds
Started	Sep 09 04:27:28 AM UTC 24
Finished	Sep 09 04:49:39 AM UTC 24
Peak memory	202552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057375990 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.2057375990
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.666920591
Short name	T287
Test name
Test status
Simulation time	405551471700 ps
CPU time	1769.51 seconds
Started	Sep 09 04:38:22 AM UTC 24
Finished	Sep 09 05:08:10 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666920591 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.666920591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.66503761
Short name	T213
Test name
Test status
Simulation time	694519015181 ps
CPU time	610.84 seconds
Started	Sep 09 04:39:19 AM UTC 24
Finished	Sep 09 04:49:36 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66503761 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.66503761
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2930395006
Short name	T356
Test name
Test status
Simulation time	7256875698118 ps
CPU time	2581.04 seconds
Started	Sep 09 04:33:03 AM UTC 24
Finished	Sep 09 05:16:31 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930395006 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2930395006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.1907797630
Short name	T58
Test name
Test status
Simulation time	606632536472 ps
CPU time	1315.83 seconds
Started	Sep 09 04:29:57 AM UTC 24
Finished	Sep 09 04:52:06 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907797630 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.1907797630
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.3841846806
Short name	T124
Test name
Test status
Simulation time	1444956837716 ps
CPU time	1142.59 seconds
Started	Sep 09 04:25:06 AM UTC 24
Finished	Sep 09 04:44:21 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841846806 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.3841846806
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.2428110261
Short name	T260
Test name
Test status
Simulation time	2764190572524 ps
CPU time	2662.77 seconds
Started	Sep 09 04:42:24 AM UTC 24
Finished	Sep 09 05:27:16 AM UTC 24
Peak memory	202520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428110261 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.2428110261
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3160165986
Short name	T52
Test name
Test status
Simulation time	969477694080 ps
CPU time	325.46 seconds
Started	Sep 09 04:30:59 AM UTC 24
Finished	Sep 09 04:36:29 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160165986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3160165986
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.1581642176
Short name	T321
Test name
Test status
Simulation time	1045392138187 ps
CPU time	379.02 seconds
Started	Sep 09 04:56:30 AM UTC 24
Finished	Sep 09 05:02:54 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581642176 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1581642176
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/121.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.2599760042
Short name	T227
Test name
Test status
Simulation time	347500840404 ps
CPU time	498.32 seconds
Started	Sep 09 05:05:11 AM UTC 24
Finished	Sep 09 05:13:35 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599760042 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2599760042
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/186.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2782562537
Short name	T238
Test name
Test status
Simulation time	1278023314406 ps
CPU time	1618.56 seconds
Started	Sep 09 04:31:51 AM UTC 24
Finished	Sep 09 04:59:06 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782562537 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2782562537
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.1786211888
Short name	T279
Test name
Test status
Simulation time	604736151117 ps
CPU time	1523.57 seconds
Started	Sep 09 04:39:44 AM UTC 24
Finished	Sep 09 05:05:25 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786211888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.1786211888
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1084954367
Short name	T246
Test name
Test status
Simulation time	3194674779139 ps
CPU time	3102.76 seconds
Started	Sep 09 04:30:56 AM UTC 24
Finished	Sep 09 05:23:11 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084954367 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1084954367
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.1261879671
Short name	T268
Test name
Test status
Simulation time	592359050233 ps
CPU time	2963.46 seconds
Started	Sep 09 04:36:51 AM UTC 24
Finished	Sep 09 05:26:45 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261879671 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.1261879671
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.3355384778
Short name	T167
Test name
Test status
Simulation time	28946254503 ps
CPU time	101.34 seconds
Started	Sep 09 04:48:31 AM UTC 24
Finished	Sep 09 04:50:15 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355384778 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3355384778
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/59.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.1665903369
Short name	T308
Test name
Test status
Simulation time	579560791636 ps
CPU time	796.49 seconds
Started	Sep 09 04:58:14 AM UTC 24
Finished	Sep 09 05:11:40 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665903369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1665903369
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/132.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.735025483
Short name	T363
Test name
Test status
Simulation time	555367326915 ps
CPU time	810.92 seconds
Started	Sep 09 05:03:59 AM UTC 24
Finished	Sep 09 05:17:39 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735025483 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.735025483
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/176.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.1841242268
Short name	T240
Test name
Test status
Simulation time	243042498881 ps
CPU time	869.42 seconds
Started	Sep 09 04:49:07 AM UTC 24
Finished	Sep 09 05:03:46 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841242268 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1841242268
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/65.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.1524772683
Short name	T204
Test name
Test status
Simulation time	172514491979 ps
CPU time	829.03 seconds
Started	Sep 09 04:55:08 AM UTC 24
Finished	Sep 09 05:09:06 AM UTC 24
Peak memory	202480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524772683 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1524772683
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/113.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.2038066856
Short name	T291
Test name
Test status
Simulation time	642627184338 ps
CPU time	1290.4 seconds
Started	Sep 09 04:59:12 AM UTC 24
Finished	Sep 09 05:20:57 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038066856 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2038066856
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/144.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1188363270
Short name	T296
Test name
Test status
Simulation time	344180343405 ps
CPU time	426.85 seconds
Started	Sep 09 04:59:37 AM UTC 24
Finished	Sep 09 05:06:49 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188363270 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1188363270
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/147.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.2714633805
Short name	T230
Test name
Test status
Simulation time	485410095083 ps
CPU time	1072.29 seconds
Started	Sep 09 04:35:12 AM UTC 24
Finished	Sep 09 04:53:15 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714633805 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2714633805
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.2174061460
Short name	T158
Test name
Test status
Simulation time	253375767512 ps
CPU time	2090.25 seconds
Started	Sep 09 04:36:28 AM UTC 24
Finished	Sep 09 05:11:40 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174061460 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.2174061460
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1976090495
Short name	T234
Test name
Test status
Simulation time	120303320855 ps
CPU time	208.41 seconds
Started	Sep 09 04:48:51 AM UTC 24
Finished	Sep 09 04:52:22 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976090495 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1976090495
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/63.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.2230574229
Short name	T241
Test name
Test status
Simulation time	150333151368 ps
CPU time	754.37 seconds
Started	Sep 09 04:50:49 AM UTC 24
Finished	Sep 09 05:03:32 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230574229 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2230574229
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/79.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.4273311625
Short name	T155
Test name
Test status
Simulation time	180173214200 ps
CPU time	291.67 seconds
Started	Sep 09 04:53:17 AM UTC 24
Finished	Sep 09 04:58:12 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273311625 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4273311625
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/100.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.3372321750
Short name	T372
Test name
Test status
Simulation time	655763115194 ps
CPU time	1132.88 seconds
Started	Sep 09 04:58:02 AM UTC 24
Finished	Sep 09 05:17:07 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372321750 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3372321750
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/128.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.327364193
Short name	T115
Test name
Test status
Simulation time	289062306126 ps
CPU time	316.01 seconds
Started	Sep 09 04:27:42 AM UTC 24
Finished	Sep 09 04:33:02 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327364193 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.327364193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1494217481
Short name	T359
Test name
Test status
Simulation time	375392158740 ps
CPU time	553.86 seconds
Started	Sep 09 04:58:20 AM UTC 24
Finished	Sep 09 05:07:41 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494217481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1494217481
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/133.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.3607459509
Short name	T165
Test name
Test status
Simulation time	164810123207 ps
CPU time	292.53 seconds
Started	Sep 09 04:59:02 AM UTC 24
Finished	Sep 09 05:03:58 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607459509 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3607459509
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/139.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2503470129
Short name	T303
Test name
Test status
Simulation time	382922673846 ps
CPU time	1122.1 seconds
Started	Sep 09 04:59:45 AM UTC 24
Finished	Sep 09 05:18:40 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503470129 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2503470129
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/148.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2186652289
Short name	T280
Test name
Test status
Simulation time	316064438189 ps
CPU time	881.7 seconds
Started	Sep 09 05:02:44 AM UTC 24
Finished	Sep 09 05:17:35 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186652289 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2186652289
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/167.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.3831153063
Short name	T365
Test name
Test status
Simulation time	1325910617485 ps
CPU time	602.43 seconds
Started	Sep 09 05:02:51 AM UTC 24
Finished	Sep 09 05:13:01 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831153063 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3831153063
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/169.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.784800285
Short name	T161
Test name
Test status
Simulation time	187323654402 ps
CPU time	273.76 seconds
Started	Sep 09 05:03:07 AM UTC 24
Finished	Sep 09 05:07:45 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784800285 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.784800285
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/171.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.740797101
Short name	T39
Test name
Test status
Simulation time	44591677 ps
CPU time	0.85 seconds
Started	Sep 09 03:53:33 AM UTC 24
Finished	Sep 09 03:53:35 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740797101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.740797101
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.472390237
Short name	T215
Test name
Test status
Simulation time	394715513836 ps
CPU time	842.47 seconds
Started	Sep 09 04:53:34 AM UTC 24
Finished	Sep 09 05:07:46 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472390237 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.472390237
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/104.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.1159327873
Short name	T176
Test name
Test status
Simulation time	97134187944 ps
CPU time	331.22 seconds
Started	Sep 09 04:53:55 AM UTC 24
Finished	Sep 09 04:59:31 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159327873 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1159327873
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/108.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1286066524
Short name	T243
Test name
Test status
Simulation time	122047943634 ps
CPU time	334.18 seconds
Started	Sep 09 04:56:19 AM UTC 24
Finished	Sep 09 05:01:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286066524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1286066524
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/118.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.1820127342
Short name	T320
Test name
Test status
Simulation time	67574142727 ps
CPU time	367.4 seconds
Started	Sep 09 04:56:24 AM UTC 24
Finished	Sep 09 05:02:36 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820127342 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1820127342
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/120.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.2789886288
Short name	T358
Test name
Test status
Simulation time	218186113333 ps
CPU time	495.2 seconds
Started	Sep 09 04:57:25 AM UTC 24
Finished	Sep 09 05:05:47 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789886288 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2789886288
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/124.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.2478611235
Short name	T277
Test name
Test status
Simulation time	242275604289 ps
CPU time	346.16 seconds
Started	Sep 09 04:59:07 AM UTC 24
Finished	Sep 09 05:04:58 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478611235 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2478611235
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/141.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.3319407795
Short name	T275
Test name
Test status
Simulation time	550642721177 ps
CPU time	234.63 seconds
Started	Sep 09 04:59:08 AM UTC 24
Finished	Sep 09 05:03:06 AM UTC 24
Peak memory	199604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319407795 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3319407795
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/142.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.388322861
Short name	T119
Test name
Test status
Simulation time	209854156253 ps
CPU time	232.96 seconds
Started	Sep 09 04:28:20 AM UTC 24
Finished	Sep 09 04:32:16 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388322861 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.388322861
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2499720159
Short name	T109
Test name
Test status
Simulation time	210900921545 ps
CPU time	226.19 seconds
Started	Sep 09 04:28:26 AM UTC 24
Finished	Sep 09 04:32:16 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499720159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2499720159
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.16830824
Short name	T249
Test name
Test status
Simulation time	903929020521 ps
CPU time	1336.2 seconds
Started	Sep 09 05:01:03 AM UTC 24
Finished	Sep 09 05:23:34 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16830824 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.16830824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/160.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.896017923
Short name	T334
Test name
Test status
Simulation time	588450263086 ps
CPU time	519.01 seconds
Started	Sep 09 04:35:20 AM UTC 24
Finished	Sep 09 04:44:05 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896017923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.896017923
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.2649250913
Short name	T178
Test name
Test status
Simulation time	190229552207 ps
CPU time	101.87 seconds
Started	Sep 09 04:37:41 AM UTC 24
Finished	Sep 09 04:39:25 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649250913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2649250913
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.408875375
Short name	T113
Test name
Test status
Simulation time	148003805387 ps
CPU time	229.47 seconds
Started	Sep 09 04:38:57 AM UTC 24
Finished	Sep 09 04:42:50 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408875375 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.408875375
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3721684802
Short name	T203
Test name
Test status
Simulation time	561759140338 ps
CPU time	1132.72 seconds
Started	Sep 09 04:46:35 AM UTC 24
Finished	Sep 09 05:05:39 AM UTC 24
Peak memory	202532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721684802 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3721684802
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.1950294385
Short name	T139
Test name
Test status
Simulation time	107876291092 ps
CPU time	142.67 seconds
Started	Sep 09 04:25:53 AM UTC 24
Finished	Sep 09 04:28:19 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950294385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1950294385
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.3440634011
Short name	T214
Test name
Test status
Simulation time	97967824680 ps
CPU time	279.66 seconds
Started	Sep 09 04:48:45 AM UTC 24
Finished	Sep 09 04:53:28 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440634011 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3440634011
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/61.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.1355338156
Short name	T138
Test name
Test status
Simulation time	330587786222 ps
CPU time	375.2 seconds
Started	Sep 09 04:26:16 AM UTC 24
Finished	Sep 09 04:32:36 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355338156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1355338156
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3401461391
Short name	T94
Test name
Test status
Simulation time	287986727 ps
CPU time	1.07 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401461391 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.3401461391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.557511470
Short name	T114
Test name
Test status
Simulation time	283410910525 ps
CPU time	437.78 seconds
Started	Sep 09 04:25:08 AM UTC 24
Finished	Sep 09 04:32:31 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557511470 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.557511470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3744908653
Short name	T264
Test name
Test status
Simulation time	241281750157 ps
CPU time	439.15 seconds
Started	Sep 09 04:25:13 AM UTC 24
Finished	Sep 09 04:32:37 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744908653 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3744908653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.2832874959
Short name	T194
Test name
Test status
Simulation time	266138686060 ps
CPU time	224.96 seconds
Started	Sep 09 04:55:23 AM UTC 24
Finished	Sep 09 04:59:11 AM UTC 24
Peak memory	199604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832874959 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2832874959
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/115.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.3019177024
Short name	T218
Test name
Test status
Simulation time	204909956301 ps
CPU time	324.56 seconds
Started	Sep 09 04:55:24 AM UTC 24
Finished	Sep 09 05:00:53 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019177024 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3019177024
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/117.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1622155815
Short name	T355
Test name
Test status
Simulation time	429423922484 ps
CPU time	395.7 seconds
Started	Sep 09 04:57:17 AM UTC 24
Finished	Sep 09 05:03:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622155815 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1622155815
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/123.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.482415536
Short name	T133
Test name
Test status
Simulation time	88207443180 ps
CPU time	543.91 seconds
Started	Sep 09 04:27:46 AM UTC 24
Finished	Sep 09 04:36:57 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482415536 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.482415536
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.63804022
Short name	T322
Test name
Test status
Simulation time	601300940175 ps
CPU time	1964.26 seconds
Started	Sep 09 04:59:07 AM UTC 24
Finished	Sep 09 05:32:12 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63804022 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.63804022
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/140.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.1489408566
Short name	T374
Test name
Test status
Simulation time	37058663886 ps
CPU time	98.25 seconds
Started	Sep 09 05:00:32 AM UTC 24
Finished	Sep 09 05:02:13 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489408566 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1489408566
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/153.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.4186680920
Short name	T366
Test name
Test status
Simulation time	6263668306 ps
CPU time	6.11 seconds
Started	Sep 09 05:03:33 AM UTC 24
Finished	Sep 09 05:03:41 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186680920 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4186680920
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/172.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3852412704
Short name	T263
Test name
Test status
Simulation time	76072475682 ps
CPU time	160.1 seconds
Started	Sep 09 05:04:42 AM UTC 24
Finished	Sep 09 05:07:25 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852412704 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3852412704
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/180.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2860771887
Short name	T242
Test name
Test status
Simulation time	240454158740 ps
CPU time	526.56 seconds
Started	Sep 09 05:04:43 AM UTC 24
Finished	Sep 09 05:13:36 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860771887 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2860771887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/181.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.3600725184
Short name	T271
Test name
Test status
Simulation time	210574618853 ps
CPU time	864.97 seconds
Started	Sep 09 05:04:58 AM UTC 24
Finished	Sep 09 05:19:35 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600725184 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3600725184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/183.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.3860384377
Short name	T207
Test name
Test status
Simulation time	391787133834 ps
CPU time	297.58 seconds
Started	Sep 09 05:06:33 AM UTC 24
Finished	Sep 09 05:11:35 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860384377 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3860384377
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/197.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.2576561798
Short name	T97
Test name
Test status
Simulation time	149091565205 ps
CPU time	428.05 seconds
Started	Sep 09 04:30:20 AM UTC 24
Finished	Sep 09 04:37:33 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576561798 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2576561798
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1511855763
Short name	T206
Test name
Test status
Simulation time	447560404225 ps
CPU time	680.5 seconds
Started	Sep 09 04:33:42 AM UTC 24
Finished	Sep 09 04:45:11 AM UTC 24
Peak memory	199756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511855763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1511855763
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.232454508
Short name	T304
Test name
Test status
Simulation time	200418342518 ps
CPU time	98.75 seconds
Started	Sep 09 04:36:48 AM UTC 24
Finished	Sep 09 04:38:29 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232454508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.232454508
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3962967098
Short name	T223
Test name
Test status
Simulation time	192302266139 ps
CPU time	335.93 seconds
Started	Sep 09 04:37:39 AM UTC 24
Finished	Sep 09 04:43:20 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962967098 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3962967098
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.1148249472
Short name	T239
Test name
Test status
Simulation time	446554025872 ps
CPU time	470.43 seconds
Started	Sep 09 04:44:06 AM UTC 24
Finished	Sep 09 04:52:02 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148249472 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1148249472
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.3385023739
Short name	T341
Test name
Test status
Simulation time	170276113943 ps
CPU time	71.89 seconds
Started	Sep 09 04:47:04 AM UTC 24
Finished	Sep 09 04:48:17 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385023739 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3385023739
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/52.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2104339039
Short name	T196
Test name
Test status
Simulation time	98400821590 ps
CPU time	1104.55 seconds
Started	Sep 09 04:26:08 AM UTC 24
Finished	Sep 09 04:44:44 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104339039 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2104339039
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1039136380
Short name	T456
Test name
Test status
Simulation time	104845663 ps
CPU time	1.48 seconds
Started	Sep 09 03:53:33 AM UTC 24
Finished	Sep 09 03:53:36 AM UTC 24
Peak memory	199036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039136380 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.1039136380
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4036332216
Short name	T21
Test name
Test status
Simulation time	20154602 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:32 AM UTC 24
Finished	Sep 09 03:53:34 AM UTC 24
Peak memory	199036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036332216 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.4036332216
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2593968401
Short name	T40
Test name
Test status
Simulation time	16098342 ps
CPU time	0.59 seconds
Started	Sep 09 03:53:34 AM UTC 24
Finished	Sep 09 03:53:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2593968401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.2593968401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.1844444427
Short name	T22
Test name
Test status
Simulation time	28195821 ps
CPU time	0.59 seconds
Started	Sep 09 03:53:33 AM UTC 24
Finished	Sep 09 03:53:35 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844444427 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1844444427
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.2915914496
Short name	T454
Test name
Test status
Simulation time	15699841 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:32 AM UTC 24
Finished	Sep 09 03:53:34 AM UTC 24
Peak memory	199824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915914496 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2915914496
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.2041509190
Short name	T455
Test name
Test status
Simulation time	160274504 ps
CPU time	2.06 seconds
Started	Sep 09 03:53:32 AM UTC 24
Finished	Sep 09 03:53:35 AM UTC 24
Peak memory	200564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041509190 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2041509190
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1298197906
Short name	T18
Test name
Test status
Simulation time	415758832 ps
CPU time	1.25 seconds
Started	Sep 09 03:53:32 AM UTC 24
Finished	Sep 09 03:53:34 AM UTC 24
Peak memory	198888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298197906 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1298197906
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3023442828
Short name	T71
Test name
Test status
Simulation time	18731316 ps
CPU time	0.64 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023442828 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.3023442828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2718056485
Short name	T78
Test name
Test status
Simulation time	426932404 ps
CPU time	3.51 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	200684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718056485 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.2718056485
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.604839981
Short name	T41
Test name
Test status
Simulation time	47194372 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	198752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604839981 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.604839981
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3335406302
Short name	T42
Test name
Test status
Simulation time	108095419 ps
CPU time	0.67 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:38 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3335406302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.3335406302
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.2027829335
Short name	T70
Test name
Test status
Simulation time	18462285 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027829335 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2027829335
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.752633084
Short name	T458
Test name
Test status
Simulation time	59593049 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:35 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752633084 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.752633084
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3789547951
Short name	T43
Test name
Test status
Simulation time	167258612 ps
CPU time	0.78 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:38 AM UTC 24
Peak memory	198852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789547951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.3789547951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.3426062521
Short name	T457
Test name
Test status
Simulation time	46283767 ps
CPU time	0.99 seconds
Started	Sep 09 03:53:34 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426062521 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3426062521
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2923241110
Short name	T498
Test name
Test status
Simulation time	26511439 ps
CPU time	0.61 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:46 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2923241110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.2923241110
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.3727955327
Short name	T83
Test name
Test status
Simulation time	18111573 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727955327 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3727955327
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.781782534
Short name	T495
Test name
Test status
Simulation time	20402053 ps
CPU time	0.59 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781782534 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.781782534
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.393387180
Short name	T494
Test name
Test status
Simulation time	14875799 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393387180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.393387180
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1149687112
Short name	T512
Test name
Test status
Simulation time	533849808 ps
CPU time	2.4 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	200744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149687112 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1149687112
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1269384839
Short name	T20
Test name
Test status
Simulation time	244746906 ps
CPU time	0.91 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:46 AM UTC 24
Peak memory	198776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269384839 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.1269384839
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1754420452
Short name	T506
Test name
Test status
Simulation time	150870816 ps
CPU time	0.78 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1754420452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.1754420452
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.1122279629
Short name	T501
Test name
Test status
Simulation time	64794112 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122279629 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1122279629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.1701123185
Short name	T500
Test name
Test status
Simulation time	15636874 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701123185 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1701123185
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3740494032
Short name	T503
Test name
Test status
Simulation time	28959842 ps
CPU time	0.65 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	199096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740494032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.3740494032
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1838355433
Short name	T497
Test name
Test status
Simulation time	83214452 ps
CPU time	1.7 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838355433 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1838355433
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3503263994
Short name	T479
Test name
Test status
Simulation time	323934504 ps
CPU time	1.23 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:46 AM UTC 24
Peak memory	199072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503263994 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.3503263994
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3311277222
Short name	T510
Test name
Test status
Simulation time	40520692 ps
CPU time	0.65 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3311277222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.3311277222
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.2455464545
Short name	T502
Test name
Test status
Simulation time	41881460 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455464545 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2455464545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1092916402
Short name	T505
Test name
Test status
Simulation time	71205345 ps
CPU time	0.55 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092916402 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1092916402
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2359509634
Short name	T504
Test name
Test status
Simulation time	186756803 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359509634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.2359509634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.401689842
Short name	T521
Test name
Test status
Simulation time	91760284 ps
CPU time	1.67 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401689842 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.401689842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2981201199
Short name	T515
Test name
Test status
Simulation time	108091252 ps
CPU time	0.75 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2981201199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2981201199
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.959867459
Short name	T511
Test name
Test status
Simulation time	14156738 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959867459 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.959867459
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2991337923
Short name	T509
Test name
Test status
Simulation time	34823164 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991337923 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2991337923
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3875854672
Short name	T513
Test name
Test status
Simulation time	23868259 ps
CPU time	0.66 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875854672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.3875854672
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2409556472
Short name	T519
Test name
Test status
Simulation time	143665528 ps
CPU time	1.45 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	199096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409556472 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2409556472
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.135362062
Short name	T518
Test name
Test status
Simulation time	124834997 ps
CPU time	1.29 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135362062 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.135362062
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2870751679
Short name	T530
Test name
Test status
Simulation time	26709293 ps
CPU time	1.04 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	201020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2870751679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.2870751679
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1151668856
Short name	T514
Test name
Test status
Simulation time	32662738 ps
CPU time	0.55 seconds
Started	Sep 09 03:53:46 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	199048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151668856 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1151668856
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3227788822
Short name	T507
Test name
Test status
Simulation time	46388077 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:46 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	198640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227788822 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3227788822
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3905596125
Short name	T516
Test name
Test status
Simulation time	27036689 ps
CPU time	0.64 seconds
Started	Sep 09 03:53:46 AM UTC 24
Finished	Sep 09 03:53:47 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905596125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3905596125
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3056770736
Short name	T517
Test name
Test status
Simulation time	45865629 ps
CPU time	1.04 seconds
Started	Sep 09 03:53:45 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	199096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056770736 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3056770736
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3493135755
Short name	T520
Test name
Test status
Simulation time	970077237 ps
CPU time	1.25 seconds
Started	Sep 09 03:53:46 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493135755 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.3493135755
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2933102809
Short name	T531
Test name
Test status
Simulation time	32188034 ps
CPU time	1.24 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2933102809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.2933102809
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.869149973
Short name	T523
Test name
Test status
Simulation time	25038991 ps
CPU time	0.48 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869149973 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.869149973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.845887004
Short name	T522
Test name
Test status
Simulation time	15649246 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	198700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845887004 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.845887004
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1448924996
Short name	T526
Test name
Test status
Simulation time	18446946 ps
CPU time	0.64 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448924996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.1448924996
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2365518101
Short name	T543
Test name
Test status
Simulation time	145045496 ps
CPU time	2.28 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	200744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365518101 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2365518101
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1078685687
Short name	T532
Test name
Test status
Simulation time	390132620 ps
CPU time	1.29 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	198828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078685687 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.1078685687
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.730580196
Short name	T528
Test name
Test status
Simulation time	12059200 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=730580196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.730580196
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1142056896
Short name	T524
Test name
Test status
Simulation time	25574686 ps
CPU time	0.48 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:48 AM UTC 24
Peak memory	199048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142056896 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1142056896
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1903005230
Short name	T525
Test name
Test status
Simulation time	247159699 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903005230 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1903005230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.608906431
Short name	T527
Test name
Test status
Simulation time	41276080 ps
CPU time	0.61 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608906431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.608906431
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1861701714
Short name	T534
Test name
Test status
Simulation time	87231618 ps
CPU time	1.7 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861701714 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1861701714
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3342381617
Short name	T529
Test name
Test status
Simulation time	226089873 ps
CPU time	0.77 seconds
Started	Sep 09 03:53:47 AM UTC 24
Finished	Sep 09 03:53:49 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342381617 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.3342381617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2482464385
Short name	T537
Test name
Test status
Simulation time	51747143 ps
CPU time	0.61 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2482464385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.2482464385
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1622014340
Short name	T535
Test name
Test status
Simulation time	14687235 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622014340 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1622014340
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.2481390312
Short name	T536
Test name
Test status
Simulation time	51388528 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481390312 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2481390312
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2239717219
Short name	T539
Test name
Test status
Simulation time	136265830 ps
CPU time	0.66 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239717219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2239717219
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.683782781
Short name	T544
Test name
Test status
Simulation time	36048811 ps
CPU time	0.93 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683782781 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.683782781
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3308673388
Short name	T541
Test name
Test status
Simulation time	42810844 ps
CPU time	0.78 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308673388 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.3308673388
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3637360191
Short name	T558
Test name
Test status
Simulation time	190100658 ps
CPU time	1.32 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:51 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3637360191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.3637360191
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3022201834
Short name	T545
Test name
Test status
Simulation time	14630286 ps
CPU time	0.62 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022201834 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3022201834
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3336517117
Short name	T538
Test name
Test status
Simulation time	37503344 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336517117 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3336517117
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.544209123
Short name	T542
Test name
Test status
Simulation time	25462485 ps
CPU time	0.6 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544209123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.544209123
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.405863794
Short name	T561
Test name
Test status
Simulation time	147974699 ps
CPU time	2.53 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:52 AM UTC 24
Peak memory	200672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405863794 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.405863794
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1950767391
Short name	T557
Test name
Test status
Simulation time	100015044 ps
CPU time	1.29 seconds
Started	Sep 09 03:53:48 AM UTC 24
Finished	Sep 09 03:53:51 AM UTC 24
Peak memory	198656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950767391 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.1950767391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1090578934
Short name	T556
Test name
Test status
Simulation time	16095067 ps
CPU time	0.69 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:51 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1090578934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.1090578934
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2899552329
Short name	T548
Test name
Test status
Simulation time	19172005 ps
CPU time	0.57 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	199048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899552329 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2899552329
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.33390787
Short name	T546
Test name
Test status
Simulation time	14290761 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33390787 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.33390787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3360859655
Short name	T555
Test name
Test status
Simulation time	103404326 ps
CPU time	0.76 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:51 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360859655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.3360859655
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1788625830
Short name	T560
Test name
Test status
Simulation time	987809005 ps
CPU time	2.06 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:52 AM UTC 24
Peak memory	200684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788625830 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1788625830
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.309310742
Short name	T559
Test name
Test status
Simulation time	353544850 ps
CPU time	1.23 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:51 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309310742 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.309310742
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3014412
Short name	T74
Test name
Test status
Simulation time	187991129 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:37 AM UTC 24
Finished	Sep 09 03:53:39 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014412 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.3014412
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2548731175
Short name	T77
Test name
Test status
Simulation time	65696143 ps
CPU time	2.09 seconds
Started	Sep 09 03:53:37 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	200940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548731175 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2548731175
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.582002802
Short name	T72
Test name
Test status
Simulation time	52013783 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	198772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582002802 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.582002802
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2180877467
Short name	T460
Test name
Test status
Simulation time	76441033 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:37 AM UTC 24
Finished	Sep 09 03:53:39 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2180877467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2180877467
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.10178356
Short name	T73
Test name
Test status
Simulation time	161290319 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:37 AM UTC 24
Finished	Sep 09 03:53:39 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10178356 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.10178356
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.3537866067
Short name	T459
Test name
Test status
Simulation time	21216498 ps
CPU time	0.45 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:37 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537866067 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3537866067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.618570553
Short name	T53
Test name
Test status
Simulation time	19436285 ps
CPU time	0.57 seconds
Started	Sep 09 03:53:37 AM UTC 24
Finished	Sep 09 03:53:39 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618570553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.618570553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.1695947670
Short name	T461
Test name
Test status
Simulation time	39781053 ps
CPU time	1.94 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:39 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695947670 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1695947670
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.879246020
Short name	T90
Test name
Test status
Simulation time	174985154 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:36 AM UTC 24
Finished	Sep 09 03:53:38 AM UTC 24
Peak memory	198860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879246020 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.879246020
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4095289304
Short name	T550
Test name
Test status
Simulation time	16230877 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095289304 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4095289304
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3772414487
Short name	T553
Test name
Test status
Simulation time	22459598 ps
CPU time	0.48 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772414487 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3772414487
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.88066476
Short name	T552
Test name
Test status
Simulation time	15815979 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88066476 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.88066476
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2396103887
Short name	T554
Test name
Test status
Simulation time	41839569 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396103887 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2396103887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.4012177173
Short name	T581
Test name
Test status
Simulation time	63620700 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:54:04 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012177173 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4012177173
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1027324590
Short name	T551
Test name
Test status
Simulation time	58519556 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:49 AM UTC 24
Finished	Sep 09 03:53:50 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027324590 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1027324590
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2612226118
Short name	T562
Test name
Test status
Simulation time	13074341 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612226118 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2612226118
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1271127485
Short name	T564
Test name
Test status
Simulation time	12929467 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271127485 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1271127485
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.754418704
Short name	T563
Test name
Test status
Simulation time	15671270 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754418704 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.754418704
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.799659814
Short name	T569
Test name
Test status
Simulation time	38681831 ps
CPU time	0.6 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799659814 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.799659814
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2119075941
Short name	T76
Test name
Test status
Simulation time	115830630 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119075941 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.2119075941
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2270734798
Short name	T81
Test name
Test status
Simulation time	90452351 ps
CPU time	2.95 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:43 AM UTC 24
Peak memory	200744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270734798 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.2270734798
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2930417618
Short name	T75
Test name
Test status
Simulation time	29651516 ps
CPU time	0.59 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930417618 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2930417618
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2968381757
Short name	T465
Test name
Test status
Simulation time	31078765 ps
CPU time	1.25 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	201024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2968381757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2968381757
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.2600040841
Short name	T84
Test name
Test status
Simulation time	21642513 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600040841 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2600040841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.2239109456
Short name	T462
Test name
Test status
Simulation time	14324976 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239109456 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2239109456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.798418939
Short name	T85
Test name
Test status
Simulation time	32207602 ps
CPU time	0.69 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798418939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.798418939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.708578855
Short name	T466
Test name
Test status
Simulation time	128072153 ps
CPU time	1.66 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708578855 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.708578855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.6612306
Short name	T92
Test name
Test status
Simulation time	130929507 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6612306 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.6612306
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1817566392
Short name	T567
Test name
Test status
Simulation time	23844395 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817566392 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1817566392
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2180877492
Short name	T566
Test name
Test status
Simulation time	51451233 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180877492 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2180877492
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1336877685
Short name	T565
Test name
Test status
Simulation time	22184537 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336877685 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1336877685
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3885980575
Short name	T568
Test name
Test status
Simulation time	13012805 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885980575 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3885980575
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.2485442149
Short name	T571
Test name
Test status
Simulation time	11763066 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485442149 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2485442149
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2028451000
Short name	T570
Test name
Test status
Simulation time	59473491 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028451000 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2028451000
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.671645053
Short name	T572
Test name
Test status
Simulation time	48735162 ps
CPU time	0.55 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671645053 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.671645053
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3389038402
Short name	T574
Test name
Test status
Simulation time	11384203 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389038402 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3389038402
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.3388639905
Short name	T533
Test name
Test status
Simulation time	25409034 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388639905 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3388639905
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3187741426
Short name	T575
Test name
Test status
Simulation time	40841432 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187741426 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3187741426
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3642322737
Short name	T79
Test name
Test status
Simulation time	33452896 ps
CPU time	0.77 seconds
Started	Sep 09 03:53:39 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642322737 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.3642322737
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3595511545
Short name	T475
Test name
Test status
Simulation time	65467226 ps
CPU time	2 seconds
Started	Sep 09 03:53:39 AM UTC 24
Finished	Sep 09 03:53:43 AM UTC 24
Peak memory	199036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595511545 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.3595511545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2874460720
Short name	T463
Test name
Test status
Simulation time	23094020 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874460720 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.2874460720
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.905672015
Short name	T470
Test name
Test status
Simulation time	88934557 ps
CPU time	0.62 seconds
Started	Sep 09 03:53:40 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=905672015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr _mem_rw_with_rand_reset.905672015
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3553416855
Short name	T468
Test name
Test status
Simulation time	43825178 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:39 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553416855 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3553416855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.1559951052
Short name	T464
Test name
Test status
Simulation time	65710482 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:40 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559951052 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1559951052
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1088930085
Short name	T86
Test name
Test status
Simulation time	32976721 ps
CPU time	0.75 seconds
Started	Sep 09 03:53:39 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088930085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.1088930085
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.2685071513
Short name	T469
Test name
Test status
Simulation time	64854450 ps
CPU time	1.34 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685071513 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2685071513
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.654946494
Short name	T91
Test name
Test status
Simulation time	172545365 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:38 AM UTC 24
Finished	Sep 09 03:53:41 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654946494 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.654946494
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3029130179
Short name	T508
Test name
Test status
Simulation time	62822200 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:50 AM UTC 24
Finished	Sep 09 03:53:59 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029130179 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3029130179
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.336705708
Short name	T573
Test name
Test status
Simulation time	17369113 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:51 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336705708 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.336705708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.1708833139
Short name	T540
Test name
Test status
Simulation time	22841115 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708833139 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1708833139
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2145730820
Short name	T549
Test name
Test status
Simulation time	46705358 ps
CPU time	0.53 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145730820 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2145730820
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1818637243
Short name	T547
Test name
Test status
Simulation time	10792199 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818637243 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1818637243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1615450366
Short name	T578
Test name
Test status
Simulation time	41355189 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	197916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615450366 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1615450366
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3470653329
Short name	T577
Test name
Test status
Simulation time	11025196 ps
CPU time	0.48 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470653329 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3470653329
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3263573909
Short name	T579
Test name
Test status
Simulation time	16878955 ps
CPU time	0.55 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263573909 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3263573909
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1945618442
Short name	T580
Test name
Test status
Simulation time	13527491 ps
CPU time	0.52 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945618442 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1945618442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3843841007
Short name	T576
Test name
Test status
Simulation time	11490761 ps
CPU time	0.49 seconds
Started	Sep 09 03:53:52 AM UTC 24
Finished	Sep 09 03:54:00 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843841007 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3843841007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2427046697
Short name	T477
Test name
Test status
Simulation time	595520235 ps
CPU time	1.48 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:43 AM UTC 24
Peak memory	200956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2427046697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2427046697
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3933620842
Short name	T80
Test name
Test status
Simulation time	32912955 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933620842 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3933620842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.1866111137
Short name	T473
Test name
Test status
Simulation time	61858056 ps
CPU time	0.47 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866111137 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1866111137
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.959956276
Short name	T88
Test name
Test status
Simulation time	171734391 ps
CPU time	0.8 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:43 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959956276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.959956276
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.274731761
Short name	T471
Test name
Test status
Simulation time	140777981 ps
CPU time	0.92 seconds
Started	Sep 09 03:53:40 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274731761 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.274731761
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1779782578
Short name	T472
Test name
Test status
Simulation time	1383986655 ps
CPU time	1.26 seconds
Started	Sep 09 03:53:40 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779782578 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1779782578
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3681592771
Short name	T485
Test name
Test status
Simulation time	162469426 ps
CPU time	1.01 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3681592771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.3681592771
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.4036918417
Short name	T87
Test name
Test status
Simulation time	39050791 ps
CPU time	0.48 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036918417 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4036918417
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.3937933973
Short name	T474
Test name
Test status
Simulation time	29850978 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:42 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937933973 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3937933973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3775980417
Short name	T89
Test name
Test status
Simulation time	55294640 ps
CPU time	0.74 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775980417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.3775980417
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.4165374469
Short name	T478
Test name
Test status
Simulation time	373155235 ps
CPU time	1.85 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165374469 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4165374469
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3959456696
Short name	T476
Test name
Test status
Simulation time	843181275 ps
CPU time	1.15 seconds
Started	Sep 09 03:53:41 AM UTC 24
Finished	Sep 09 03:53:43 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959456696 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.3959456696
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2514817214
Short name	T487
Test name
Test status
Simulation time	29207073 ps
CPU time	0.73 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2514817214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.2514817214
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.3092370789
Short name	T82
Test name
Test status
Simulation time	84845393 ps
CPU time	0.51 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092370789 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3092370789
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.113087647
Short name	T480
Test name
Test status
Simulation time	18887597 ps
CPU time	0.56 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113087647 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.113087647
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2198820503
Short name	T481
Test name
Test status
Simulation time	31953969 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198820503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.2198820503
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3171078940
Short name	T490
Test name
Test status
Simulation time	272724502 ps
CPU time	1.5 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171078940 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3171078940
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1938804111
Short name	T484
Test name
Test status
Simulation time	92533946 ps
CPU time	0.79 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938804111 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.1938804111
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2578787870
Short name	T486
Test name
Test status
Simulation time	56785051 ps
CPU time	0.58 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2578787870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.2578787870
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.208557397
Short name	T482
Test name
Test status
Simulation time	12364328 ps
CPU time	0.5 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208557397 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.208557397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2173161449
Short name	T483
Test name
Test status
Simulation time	27508338 ps
CPU time	0.55 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173161449 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2173161449
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2039468186
Short name	T488
Test name
Test status
Simulation time	17254610 ps
CPU time	0.72 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039468186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.2039468186
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2256578350
Short name	T491
Test name
Test status
Simulation time	31567999 ps
CPU time	1.31 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	198896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256578350 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2256578350
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3975780816
Short name	T489
Test name
Test status
Simulation time	65382494 ps
CPU time	0.99 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975780816 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.3975780816
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1169562271
Short name	T499
Test name
Test status
Simulation time	54739130 ps
CPU time	1.28 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:46 AM UTC 24
Peak memory	200660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1169562271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.1169562271
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.506681794
Short name	T493
Test name
Test status
Simulation time	22749282 ps
CPU time	0.57 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506681794 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.506681794
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1061883213
Short name	T467
Test name
Test status
Simulation time	25321082 ps
CPU time	0.54 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061883213 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1061883213
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2328098610
Short name	T496
Test name
Test status
Simulation time	40611659 ps
CPU time	0.82 seconds
Started	Sep 09 03:53:44 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	198792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328098610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.2328098610
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.417565138
Short name	T492
Test name
Test status
Simulation time	108250146 ps
CPU time	1.22 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:45 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417565138 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.417565138
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.668738261
Short name	T93
Test name
Test status
Simulation time	691811839 ps
CPU time	1.03 seconds
Started	Sep 09 03:53:42 AM UTC 24
Finished	Sep 09 03:53:44 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668738261 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.668738261
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.4038373703
Short name	T306
Test name
Test status
Simulation time	492479720182 ps
CPU time	853.98 seconds
Started	Sep 09 04:25:04 AM UTC 24
Finished	Sep 09 04:39:27 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038373703 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.4038373703
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2132107393
Short name	T387
Test name
Test status
Simulation time	327944405099 ps
CPU time	352.39 seconds
Started	Sep 09 04:25:04 AM UTC 24
Finished	Sep 09 04:31:00 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132107393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2132107393
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2214285922
Short name	T10
Test name
Test status
Simulation time	34767093000 ps
CPU time	62.8 seconds
Started	Sep 09 04:25:04 AM UTC 24
Finished	Sep 09 04:26:08 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214285922 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2214285922
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.3826954548
Short name	T15
Test name
Test status
Simulation time	261921108497 ps
CPU time	74.92 seconds
Started	Sep 09 04:25:06 AM UTC 24
Finished	Sep 09 04:26:23 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826954548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3826954548
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2567895581
Short name	T125
Test name
Test status
Simulation time	114688192503 ps
CPU time	149.97 seconds
Started	Sep 09 04:25:10 AM UTC 24
Finished	Sep 09 04:27:43 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567895581 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2567895581
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4191451703
Short name	T384
Test name
Test status
Simulation time	147487697599 ps
CPU time	235.21 seconds
Started	Sep 09 04:25:10 AM UTC 24
Finished	Sep 09 04:29:09 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191451703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4191451703
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.374072451
Short name	T2
Test name
Test status
Simulation time	591827271 ps
CPU time	1.36 seconds
Started	Sep 09 04:25:10 AM UTC 24
Finished	Sep 09 04:25:13 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374072451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.374072451
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.1960970567
Short name	T3
Test name
Test status
Simulation time	60381772 ps
CPU time	1.3 seconds
Started	Sep 09 04:25:14 AM UTC 24
Finished	Sep 09 04:25:17 AM UTC 24
Peak memory	228704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960970567 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1960970567
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.3382923128
Short name	T140
Test name
Test status
Simulation time	376266201874 ps
CPU time	236.27 seconds
Started	Sep 09 04:26:48 AM UTC 24
Finished	Sep 09 04:30:48 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382923128 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3382923128
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.625731936
Short name	T385
Test name
Test status
Simulation time	197557140104 ps
CPU time	160.79 seconds
Started	Sep 09 04:26:47 AM UTC 24
Finished	Sep 09 04:29:30 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625731936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.625731936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.2319336840
Short name	T141
Test name
Test status
Simulation time	65096963961 ps
CPU time	86.37 seconds
Started	Sep 09 04:26:41 AM UTC 24
Finished	Sep 09 04:28:09 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319336840 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2319336840
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.87205764
Short name	T146
Test name
Test status
Simulation time	60381217958 ps
CPU time	479.15 seconds
Started	Sep 09 04:26:50 AM UTC 24
Finished	Sep 09 04:34:55 AM UTC 24
Peak memory	199912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87205764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.87205764
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.3212974333
Short name	T202
Test name
Test status
Simulation time	1357251856546 ps
CPU time	1826.56 seconds
Started	Sep 09 04:27:01 AM UTC 24
Finished	Sep 09 04:57:47 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212974333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3212974333
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/10.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.2633936489
Short name	T229
Test name
Test status
Simulation time	268653914729 ps
CPU time	317.41 seconds
Started	Sep 09 04:53:22 AM UTC 24
Finished	Sep 09 04:58:43 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633936489 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2633936489
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/101.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3133022033
Short name	T285
Test name
Test status
Simulation time	224436457234 ps
CPU time	171.62 seconds
Started	Sep 09 04:53:29 AM UTC 24
Finished	Sep 09 04:56:23 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133022033 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3133022033
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/102.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.3301637888
Short name	T219
Test name
Test status
Simulation time	190261017323 ps
CPU time	443.78 seconds
Started	Sep 09 04:53:29 AM UTC 24
Finished	Sep 09 05:00:58 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301637888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3301637888
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/103.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.193335226
Short name	T312
Test name
Test status
Simulation time	203142515550 ps
CPU time	298.06 seconds
Started	Sep 09 04:53:36 AM UTC 24
Finished	Sep 09 04:58:38 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193335226 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.193335226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/105.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.1244247824
Short name	T315
Test name
Test status
Simulation time	49634244583 ps
CPU time	292.45 seconds
Started	Sep 09 04:53:42 AM UTC 24
Finished	Sep 09 04:58:38 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244247824 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1244247824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/106.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.388474550
Short name	T293
Test name
Test status
Simulation time	71956153399 ps
CPU time	255.71 seconds
Started	Sep 09 04:53:54 AM UTC 24
Finished	Sep 09 04:58:13 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388474550 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.388474550
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/107.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.1519667181
Short name	T257
Test name
Test status
Simulation time	172811052215 ps
CPU time	317.91 seconds
Started	Sep 09 04:54:08 AM UTC 24
Finished	Sep 09 04:59:31 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519667181 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1519667181
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/109.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.4159187054
Short name	T329
Test name
Test status
Simulation time	428338934720 ps
CPU time	810.88 seconds
Started	Sep 09 04:27:04 AM UTC 24
Finished	Sep 09 04:40:44 AM UTC 24
Peak memory	202468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159187054 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.4159187054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.3987033653
Short name	T394
Test name
Test status
Simulation time	278169964630 ps
CPU time	307.49 seconds
Started	Sep 09 04:27:04 AM UTC 24
Finished	Sep 09 04:32:16 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987033653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3987033653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.1472117943
Short name	T126
Test name
Test status
Simulation time	61151962997 ps
CPU time	141.37 seconds
Started	Sep 09 04:27:02 AM UTC 24
Finished	Sep 09 04:29:25 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472117943 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1472117943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1289766105
Short name	T163
Test name
Test status
Simulation time	45005316426 ps
CPU time	817.34 seconds
Started	Sep 09 04:27:06 AM UTC 24
Finished	Sep 09 04:40:54 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289766105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1289766105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.2606216161
Short name	T54
Test name
Test status
Simulation time	908757977760 ps
CPU time	179.46 seconds
Started	Sep 09 04:27:11 AM UTC 24
Finished	Sep 09 04:30:14 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606216161 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.2606216161
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/11.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.1249219205
Short name	T350
Test name
Test status
Simulation time	116510873471 ps
CPU time	691.13 seconds
Started	Sep 09 04:54:35 AM UTC 24
Finished	Sep 09 05:06:14 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249219205 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1249219205
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/110.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.4096788749
Short name	T281
Test name
Test status
Simulation time	412415432951 ps
CPU time	229.52 seconds
Started	Sep 09 04:54:47 AM UTC 24
Finished	Sep 09 04:58:39 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096788749 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4096788749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/111.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.3934051904
Short name	T225
Test name
Test status
Simulation time	431190284893 ps
CPU time	442.9 seconds
Started	Sep 09 04:54:55 AM UTC 24
Finished	Sep 09 05:02:23 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934051904 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3934051904
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/112.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.2395041174
Short name	T310
Test name
Test status
Simulation time	49481867670 ps
CPU time	127.69 seconds
Started	Sep 09 04:55:15 AM UTC 24
Finished	Sep 09 04:57:25 AM UTC 24
Peak memory	199452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395041174 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2395041174
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/114.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3993155332
Short name	T317
Test name
Test status
Simulation time	39747321047 ps
CPU time	110.91 seconds
Started	Sep 09 04:55:23 AM UTC 24
Finished	Sep 09 04:57:16 AM UTC 24
Peak memory	199608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993155332 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3993155332
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/116.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.1423222941
Short name	T453
Test name
Test status
Simulation time	41917470184 ps
CPU time	1405.4 seconds
Started	Sep 09 04:56:24 AM UTC 24
Finished	Sep 09 05:20:05 AM UTC 24
Peak memory	202320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423222941 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1423222941
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/119.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1266786526
Short name	T112
Test name
Test status
Simulation time	381136516301 ps
CPU time	694.39 seconds
Started	Sep 09 04:27:24 AM UTC 24
Finished	Sep 09 04:39:07 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266786526 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1266786526
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.2715186907
Short name	T388
Test name
Test status
Simulation time	422383998550 ps
CPU time	228.6 seconds
Started	Sep 09 04:27:16 AM UTC 24
Finished	Sep 09 04:31:08 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715186907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2715186907
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3227258248
Short name	T117
Test name
Test status
Simulation time	50840247762 ps
CPU time	53.58 seconds
Started	Sep 09 04:27:15 AM UTC 24
Finished	Sep 09 04:28:11 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227258248 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3227258248
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2213777935
Short name	T36
Test name
Test status
Simulation time	593090657 ps
CPU time	1.18 seconds
Started	Sep 09 04:27:25 AM UTC 24
Finished	Sep 09 04:27:27 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213777935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2213777935
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/12.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.250996994
Short name	T200
Test name
Test status
Simulation time	32383953501 ps
CPU time	68.29 seconds
Started	Sep 09 04:56:51 AM UTC 24
Finished	Sep 09 04:58:01 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250996994 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.250996994
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/122.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.2949921682
Short name	T226
Test name
Test status
Simulation time	80908922608 ps
CPU time	462.42 seconds
Started	Sep 09 04:57:30 AM UTC 24
Finished	Sep 09 05:05:19 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949921682 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2949921682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/125.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.317578041
Short name	T336
Test name
Test status
Simulation time	47203464515 ps
CPU time	78.32 seconds
Started	Sep 09 04:57:47 AM UTC 24
Finished	Sep 09 04:59:08 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317578041 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.317578041
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/126.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.247163951
Short name	T367
Test name
Test status
Simulation time	66104157829 ps
CPU time	63.46 seconds
Started	Sep 09 04:57:56 AM UTC 24
Finished	Sep 09 04:59:01 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247163951 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.247163951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/127.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1893516832
Short name	T267
Test name
Test status
Simulation time	39782848923 ps
CPU time	166.43 seconds
Started	Sep 09 04:58:05 AM UTC 24
Finished	Sep 09 05:00:54 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893516832 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1893516832
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/129.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.2827396769
Short name	T61
Test name
Test status
Simulation time	140280353567 ps
CPU time	164.74 seconds
Started	Sep 09 04:27:30 AM UTC 24
Finished	Sep 09 04:30:17 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827396769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2827396769
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.202470767
Short name	T116
Test name
Test status
Simulation time	62634331546 ps
CPU time	556.21 seconds
Started	Sep 09 04:27:28 AM UTC 24
Finished	Sep 09 04:36:51 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202470767 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.202470767
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.33374633
Short name	T380
Test name
Test status
Simulation time	267488672 ps
CPU time	1.63 seconds
Started	Sep 09 04:27:42 AM UTC 24
Finished	Sep 09 04:27:45 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33374633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.33374633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3968941798
Short name	T100
Test name
Test status
Simulation time	270313891541 ps
CPU time	675.4 seconds
Started	Sep 09 04:27:44 AM UTC 24
Finished	Sep 09 04:39:07 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968941798 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.3968941798
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/13.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.916830271
Short name	T357
Test name
Test status
Simulation time	268814534255 ps
CPU time	1680.94 seconds
Started	Sep 09 04:58:09 AM UTC 24
Finished	Sep 09 05:26:28 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916830271 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.916830271
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/130.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.2336141466
Short name	T162
Test name
Test status
Simulation time	299895526910 ps
CPU time	926.92 seconds
Started	Sep 09 04:58:13 AM UTC 24
Finished	Sep 09 05:13:50 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336141466 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2336141466
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/131.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.3238737488
Short name	T274
Test name
Test status
Simulation time	95586297970 ps
CPU time	767.16 seconds
Started	Sep 09 04:58:27 AM UTC 24
Finished	Sep 09 05:11:23 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238737488 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3238737488
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/134.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2038095454
Short name	T319
Test name
Test status
Simulation time	107785928100 ps
CPU time	383.72 seconds
Started	Sep 09 04:58:38 AM UTC 24
Finished	Sep 09 05:05:07 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038095454 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2038095454
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/135.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.4067327653
Short name	T354
Test name
Test status
Simulation time	14589512197 ps
CPU time	62.83 seconds
Started	Sep 09 04:58:39 AM UTC 24
Finished	Sep 09 04:59:44 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067327653 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4067327653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/136.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.3309233972
Short name	T441
Test name
Test status
Simulation time	78814314676 ps
CPU time	81.43 seconds
Started	Sep 09 04:58:40 AM UTC 24
Finished	Sep 09 05:00:04 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309233972 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3309233972
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/137.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.781973001
Short name	T443
Test name
Test status
Simulation time	245140264876 ps
CPU time	157.75 seconds
Started	Sep 09 04:58:44 AM UTC 24
Finished	Sep 09 05:01:24 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781973001 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.781973001
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/138.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.3526449083
Short name	T333
Test name
Test status
Simulation time	907445267496 ps
CPU time	813.85 seconds
Started	Sep 09 04:27:49 AM UTC 24
Finished	Sep 09 04:41:32 AM UTC 24
Peak memory	202532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526449083 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3526449083
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.141782595
Short name	T379
Test name
Test status
Simulation time	116441269818 ps
CPU time	241.09 seconds
Started	Sep 09 04:27:46 AM UTC 24
Finished	Sep 09 04:31:51 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141782595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.141782595
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.878664008
Short name	T153
Test name
Test status
Simulation time	148400059271 ps
CPU time	169.04 seconds
Started	Sep 09 04:27:55 AM UTC 24
Finished	Sep 09 04:30:46 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878664008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.878664008
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.533139411
Short name	T12
Test name
Test status
Simulation time	17616000 ps
CPU time	0.82 seconds
Started	Sep 09 04:28:08 AM UTC 24
Finished	Sep 09 04:28:09 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533139411 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.533139411
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all_with_rand_reset.2685623608
Short name	T13
Test name
Test status
Simulation time	2209327949 ps
CPU time	21.42 seconds
Started	Sep 09 04:28:08 AM UTC 24
Finished	Sep 09 04:28:30 AM UTC 24
Peak memory	201976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2685623608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.rv_timer_stress_all_with_rand_reset.2685623608
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.1564252071
Short name	T442
Test name
Test status
Simulation time	41853401132 ps
CPU time	87.76 seconds
Started	Sep 09 04:59:08 AM UTC 24
Finished	Sep 09 05:00:38 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564252071 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1564252071
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/143.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.190992504
Short name	T179
Test name
Test status
Simulation time	73933934743 ps
CPU time	194.47 seconds
Started	Sep 09 04:59:32 AM UTC 24
Finished	Sep 09 05:02:50 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190992504 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.190992504
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/145.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2323692664
Short name	T173
Test name
Test status
Simulation time	168582285417 ps
CPU time	77.57 seconds
Started	Sep 09 04:59:32 AM UTC 24
Finished	Sep 09 05:00:52 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323692664 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2323692664
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/146.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.382867898
Short name	T302
Test name
Test status
Simulation time	303535050507 ps
CPU time	806.33 seconds
Started	Sep 09 04:59:58 AM UTC 24
Finished	Sep 09 05:13:34 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382867898 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.382867898
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/149.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.4193048556
Short name	T101
Test name
Test status
Simulation time	154489890436 ps
CPU time	327.59 seconds
Started	Sep 09 04:28:10 AM UTC 24
Finished	Sep 09 04:33:41 AM UTC 24
Peak memory	199792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193048556 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.4193048556
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.412658035
Short name	T392
Test name
Test status
Simulation time	159271442290 ps
CPU time	217.64 seconds
Started	Sep 09 04:28:10 AM UTC 24
Finished	Sep 09 04:31:50 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412658035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.412658035
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.194347025
Short name	T149
Test name
Test status
Simulation time	30310574328 ps
CPU time	83.73 seconds
Started	Sep 09 04:28:10 AM UTC 24
Finished	Sep 09 04:29:35 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194347025 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.194347025
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.3012841991
Short name	T156
Test name
Test status
Simulation time	88460012973 ps
CPU time	344.81 seconds
Started	Sep 09 04:28:12 AM UTC 24
Finished	Sep 09 04:34:01 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012841991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3012841991
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/15.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.132905694
Short name	T325
Test name
Test status
Simulation time	59252320231 ps
CPU time	155.31 seconds
Started	Sep 09 05:00:06 AM UTC 24
Finished	Sep 09 05:02:44 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132905694 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.132905694
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/150.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.336107864
Short name	T245
Test name
Test status
Simulation time	196234152642 ps
CPU time	367.41 seconds
Started	Sep 09 05:00:10 AM UTC 24
Finished	Sep 09 05:06:22 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336107864 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.336107864
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/151.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2619444634
Short name	T370
Test name
Test status
Simulation time	599808032340 ps
CPU time	309.7 seconds
Started	Sep 09 05:00:17 AM UTC 24
Finished	Sep 09 05:05:31 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619444634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2619444634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/152.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.3658235221
Short name	T273
Test name
Test status
Simulation time	126624376918 ps
CPU time	517.49 seconds
Started	Sep 09 05:00:38 AM UTC 24
Finished	Sep 09 05:09:23 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658235221 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3658235221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/154.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.3887506230
Short name	T252
Test name
Test status
Simulation time	62031679514 ps
CPU time	228.33 seconds
Started	Sep 09 05:00:44 AM UTC 24
Finished	Sep 09 05:04:36 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887506230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3887506230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/155.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.3469628100
Short name	T376
Test name
Test status
Simulation time	575394596900 ps
CPU time	402.07 seconds
Started	Sep 09 05:00:52 AM UTC 24
Finished	Sep 09 05:07:40 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469628100 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3469628100
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/156.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.4210637768
Short name	T177
Test name
Test status
Simulation time	73604913982 ps
CPU time	101.71 seconds
Started	Sep 09 05:00:53 AM UTC 24
Finished	Sep 09 05:02:37 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210637768 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4210637768
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/157.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.525993840
Short name	T328
Test name
Test status
Simulation time	320476319910 ps
CPU time	251.93 seconds
Started	Sep 09 05:00:55 AM UTC 24
Finished	Sep 09 05:05:10 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525993840 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.525993840
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/158.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.2937649029
Short name	T360
Test name
Test status
Simulation time	31799503726 ps
CPU time	245.1 seconds
Started	Sep 09 05:00:59 AM UTC 24
Finished	Sep 09 05:05:07 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937649029 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2937649029
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/159.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.3917268803
Short name	T103
Test name
Test status
Simulation time	895503685795 ps
CPU time	237.41 seconds
Started	Sep 09 04:28:24 AM UTC 24
Finished	Sep 09 04:32:25 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917268803 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3917268803
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.231789911
Short name	T393
Test name
Test status
Simulation time	261608681944 ps
CPU time	224.55 seconds
Started	Sep 09 04:28:24 AM UTC 24
Finished	Sep 09 04:32:12 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231789911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.231789911
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.3336923445
Short name	T60
Test name
Test status
Simulation time	72944213961 ps
CPU time	97.04 seconds
Started	Sep 09 04:28:37 AM UTC 24
Finished	Sep 09 04:30:16 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336923445 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.3336923445
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all_with_rand_reset.722033029
Short name	T17
Test name
Test status
Simulation time	18208442272 ps
CPU time	71.45 seconds
Started	Sep 09 04:28:32 AM UTC 24
Finished	Sep 09 04:29:46 AM UTC 24
Peak memory	203836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=722033029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.722033029
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.590184639
Short name	T188
Test name
Test status
Simulation time	1370726693509 ps
CPU time	775.37 seconds
Started	Sep 09 05:01:25 AM UTC 24
Finished	Sep 09 05:14:29 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590184639 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.590184639
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/161.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3382450620
Short name	T337
Test name
Test status
Simulation time	156689227613 ps
CPU time	159.35 seconds
Started	Sep 09 05:01:59 AM UTC 24
Finished	Sep 09 05:04:41 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382450620 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3382450620
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/162.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.1175480164
Short name	T278
Test name
Test status
Simulation time	364335434639 ps
CPU time	426.72 seconds
Started	Sep 09 05:02:13 AM UTC 24
Finished	Sep 09 05:09:25 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175480164 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1175480164
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/163.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.125383867
Short name	T444
Test name
Test status
Simulation time	7884509398 ps
CPU time	18.29 seconds
Started	Sep 09 05:02:23 AM UTC 24
Finished	Sep 09 05:02:43 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125383867 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.125383867
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/164.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.2367906655
Short name	T445
Test name
Test status
Simulation time	71015438224 ps
CPU time	123.78 seconds
Started	Sep 09 05:02:37 AM UTC 24
Finished	Sep 09 05:04:42 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367906655 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2367906655
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/165.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.1166585615
Short name	T335
Test name
Test status
Simulation time	98057847221 ps
CPU time	226.31 seconds
Started	Sep 09 05:02:38 AM UTC 24
Finished	Sep 09 05:06:28 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166585615 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1166585615
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/166.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.373093218
Short name	T283
Test name
Test status
Simulation time	898688411817 ps
CPU time	242.31 seconds
Started	Sep 09 05:02:45 AM UTC 24
Finished	Sep 09 05:06:50 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373093218 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.373093218
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/168.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.1633399828
Short name	T258
Test name
Test status
Simulation time	1711562036245 ps
CPU time	1002.6 seconds
Started	Sep 09 04:29:09 AM UTC 24
Finished	Sep 09 04:46:02 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633399828 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1633399828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.38140004
Short name	T390
Test name
Test status
Simulation time	84137526455 ps
CPU time	141.31 seconds
Started	Sep 09 04:28:56 AM UTC 24
Finished	Sep 09 04:31:20 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38140004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.38140004
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2800222369
Short name	T136
Test name
Test status
Simulation time	221022118144 ps
CPU time	1085.89 seconds
Started	Sep 09 04:28:42 AM UTC 24
Finished	Sep 09 04:47:00 AM UTC 24
Peak memory	202520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800222369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2800222369
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.1477203838
Short name	T307
Test name
Test status
Simulation time	104125293361 ps
CPU time	237.89 seconds
Started	Sep 09 04:29:19 AM UTC 24
Finished	Sep 09 04:33:20 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477203838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1477203838
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.3123104333
Short name	T51
Test name
Test status
Simulation time	770929625583 ps
CPU time	411.06 seconds
Started	Sep 09 04:29:31 AM UTC 24
Finished	Sep 09 04:36:27 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123104333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.3123104333
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/17.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.2027146612
Short name	T375
Test name
Test status
Simulation time	57214697130 ps
CPU time	83.59 seconds
Started	Sep 09 05:02:55 AM UTC 24
Finished	Sep 09 05:04:20 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027146612 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2027146612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/170.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.3154861803
Short name	T195
Test name
Test status
Simulation time	168299787398 ps
CPU time	338.41 seconds
Started	Sep 09 05:03:41 AM UTC 24
Finished	Sep 09 05:09:24 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154861803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3154861803
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/173.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.3902745891
Short name	T373
Test name
Test status
Simulation time	39940304496 ps
CPU time	148.49 seconds
Started	Sep 09 05:03:47 AM UTC 24
Finished	Sep 09 05:06:18 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902745891 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3902745891
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/174.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.2333446167
Short name	T288
Test name
Test status
Simulation time	278696496415 ps
CPU time	999.31 seconds
Started	Sep 09 05:03:59 AM UTC 24
Finished	Sep 09 05:20:51 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333446167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2333446167
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/175.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.379442039
Short name	T305
Test name
Test status
Simulation time	619677531416 ps
CPU time	283.93 seconds
Started	Sep 09 05:04:05 AM UTC 24
Finished	Sep 09 05:08:52 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379442039 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.379442039
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/177.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.2059869532
Short name	T231
Test name
Test status
Simulation time	97629196553 ps
CPU time	483.82 seconds
Started	Sep 09 05:04:21 AM UTC 24
Finished	Sep 09 05:12:30 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059869532 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2059869532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/178.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.338332991
Short name	T451
Test name
Test status
Simulation time	134898854366 ps
CPU time	744.76 seconds
Started	Sep 09 05:04:37 AM UTC 24
Finished	Sep 09 05:17:11 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338332991 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.338332991
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/179.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3236864526
Short name	T105
Test name
Test status
Simulation time	112221114876 ps
CPU time	62.47 seconds
Started	Sep 09 04:29:36 AM UTC 24
Finished	Sep 09 04:30:40 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236864526 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3236864526
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.460877305
Short name	T396
Test name
Test status
Simulation time	391702027654 ps
CPU time	172.96 seconds
Started	Sep 09 04:29:33 AM UTC 24
Finished	Sep 09 04:32:29 AM UTC 24
Peak memory	199752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460877305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.460877305
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.927112987
Short name	T65
Test name
Test status
Simulation time	60297141885 ps
CPU time	58.82 seconds
Started	Sep 09 04:29:32 AM UTC 24
Finished	Sep 09 04:30:32 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927112987 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.927112987
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.3083472591
Short name	T386
Test name
Test status
Simulation time	294378399 ps
CPU time	1.02 seconds
Started	Sep 09 04:29:46 AM UTC 24
Finished	Sep 09 04:29:48 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083472591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3083472591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/18.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3243271336
Short name	T197
Test name
Test status
Simulation time	318828763937 ps
CPU time	992 seconds
Started	Sep 09 05:04:44 AM UTC 24
Finished	Sep 09 05:21:28 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243271336 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3243271336
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/182.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.2430165526
Short name	T364
Test name
Test status
Simulation time	77945325211 ps
CPU time	344.95 seconds
Started	Sep 09 05:05:07 AM UTC 24
Finished	Sep 09 05:10:57 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430165526 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2430165526
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/184.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.1068755348
Short name	T368
Test name
Test status
Simulation time	70387104487 ps
CPU time	674.3 seconds
Started	Sep 09 05:05:09 AM UTC 24
Finished	Sep 09 05:16:31 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068755348 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1068755348
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/185.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.3158320685
Short name	T362
Test name
Test status
Simulation time	74931522015 ps
CPU time	1346.55 seconds
Started	Sep 09 05:05:20 AM UTC 24
Finished	Sep 09 05:28:02 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158320685 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3158320685
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/187.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.930037543
Short name	T446
Test name
Test status
Simulation time	69877701440 ps
CPU time	64.02 seconds
Started	Sep 09 05:05:26 AM UTC 24
Finished	Sep 09 05:06:32 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930037543 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.930037543
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/188.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.2020126622
Short name	T371
Test name
Test status
Simulation time	58752302621 ps
CPU time	163.66 seconds
Started	Sep 09 05:05:32 AM UTC 24
Finished	Sep 09 05:08:18 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020126622 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2020126622
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/189.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.1872172077
Short name	T67
Test name
Test status
Simulation time	7407172351 ps
CPU time	20.68 seconds
Started	Sep 09 04:30:12 AM UTC 24
Finished	Sep 09 04:30:34 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872172077 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1872172077
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.2419958215
Short name	T398
Test name
Test status
Simulation time	77678182314 ps
CPU time	150.23 seconds
Started	Sep 09 04:30:01 AM UTC 24
Finished	Sep 09 04:32:35 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419958215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2419958215
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.3300073368
Short name	T68
Test name
Test status
Simulation time	33077013217 ps
CPU time	32.37 seconds
Started	Sep 09 04:30:00 AM UTC 24
Finished	Sep 09 04:30:35 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300073368 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3300073368
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.174700735
Short name	T132
Test name
Test status
Simulation time	51340983088 ps
CPU time	87.99 seconds
Started	Sep 09 04:30:14 AM UTC 24
Finished	Sep 09 04:31:44 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174700735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.174700735
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.2026896791
Short name	T63
Test name
Test status
Simulation time	51464351 ps
CPU time	0.73 seconds
Started	Sep 09 04:30:18 AM UTC 24
Finished	Sep 09 04:30:20 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026896791 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.2026896791
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/19.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.3806221524
Short name	T284
Test name
Test status
Simulation time	84944762384 ps
CPU time	112.05 seconds
Started	Sep 09 05:05:40 AM UTC 24
Finished	Sep 09 05:07:34 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806221524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3806221524
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/190.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.1042186028
Short name	T447
Test name
Test status
Simulation time	90383982621 ps
CPU time	133.87 seconds
Started	Sep 09 05:05:43 AM UTC 24
Finished	Sep 09 05:07:59 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042186028 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1042186028
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/191.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.2516777738
Short name	T251
Test name
Test status
Simulation time	165584200148 ps
CPU time	123.57 seconds
Started	Sep 09 05:05:48 AM UTC 24
Finished	Sep 09 05:07:54 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516777738 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2516777738
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/192.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.3999579827
Short name	T276
Test name
Test status
Simulation time	24445065527 ps
CPU time	61.68 seconds
Started	Sep 09 05:06:14 AM UTC 24
Finished	Sep 09 05:07:18 AM UTC 24
Peak memory	199608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999579827 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3999579827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/193.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.2347987159
Short name	T262
Test name
Test status
Simulation time	328271953980 ps
CPU time	273.26 seconds
Started	Sep 09 05:06:19 AM UTC 24
Finished	Sep 09 05:10:57 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347987159 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2347987159
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/194.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.3152545579
Short name	T452
Test name
Test status
Simulation time	52782073973 ps
CPU time	648.09 seconds
Started	Sep 09 05:06:22 AM UTC 24
Finished	Sep 09 05:17:19 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152545579 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3152545579
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/195.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3436640855
Short name	T247
Test name
Test status
Simulation time	371409771127 ps
CPU time	436.08 seconds
Started	Sep 09 05:06:29 AM UTC 24
Finished	Sep 09 05:13:50 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436640855 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3436640855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/196.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1964378442
Short name	T448
Test name
Test status
Simulation time	72901590782 ps
CPU time	114.5 seconds
Started	Sep 09 05:06:50 AM UTC 24
Finished	Sep 09 05:08:46 AM UTC 24
Peak memory	199604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964378442 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1964378442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/198.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2177329973
Short name	T449
Test name
Test status
Simulation time	88113784006 ps
CPU time	229.84 seconds
Started	Sep 09 05:06:51 AM UTC 24
Finished	Sep 09 05:10:44 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177329973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2177329973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/199.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2077526587
Short name	T98
Test name
Test status
Simulation time	187636528080 ps
CPU time	474.22 seconds
Started	Sep 09 04:25:18 AM UTC 24
Finished	Sep 09 04:33:18 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077526587 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2077526587
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.648393979
Short name	T378
Test name
Test status
Simulation time	246823479990 ps
CPU time	142.02 seconds
Started	Sep 09 04:25:16 AM UTC 24
Finished	Sep 09 04:27:40 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648393979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.648393979
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.3935668965
Short name	T16
Test name
Test status
Simulation time	58435459650 ps
CPU time	89.66 seconds
Started	Sep 09 04:25:14 AM UTC 24
Finished	Sep 09 04:26:46 AM UTC 24
Peak memory	199528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935668965 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3935668965
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.2531354939
Short name	T4
Test name
Test status
Simulation time	30425112 ps
CPU time	0.85 seconds
Started	Sep 09 04:25:23 AM UTC 24
Finished	Sep 09 04:25:25 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531354939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2531354939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1174764577
Short name	T5
Test name
Test status
Simulation time	34983919 ps
CPU time	1.09 seconds
Started	Sep 09 04:25:27 AM UTC 24
Finished	Sep 09 04:25:29 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174764577 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1174764577
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2513900162
Short name	T205
Test name
Test status
Simulation time	3770091834117 ps
CPU time	2796.66 seconds
Started	Sep 09 04:25:25 AM UTC 24
Finished	Sep 09 05:12:31 AM UTC 24
Peak memory	202496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513900162 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2513900162
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/2.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.4154080354
Short name	T95
Test name
Test status
Simulation time	25151433188 ps
CPU time	46.31 seconds
Started	Sep 09 04:30:22 AM UTC 24
Finished	Sep 09 04:31:09 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154080354 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.4154080354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3561374680
Short name	T405
Test name
Test status
Simulation time	235258643323 ps
CPU time	246.27 seconds
Started	Sep 09 04:30:21 AM UTC 24
Finished	Sep 09 04:34:30 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561374680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3561374680
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.3147984605
Short name	T66
Test name
Test status
Simulation time	841772430 ps
CPU time	0.87 seconds
Started	Sep 09 04:30:31 AM UTC 24
Finished	Sep 09 04:30:33 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147984605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3147984605
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/20.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1047621651
Short name	T45
Test name
Test status
Simulation time	528033474839 ps
CPU time	282.8 seconds
Started	Sep 09 04:30:41 AM UTC 24
Finished	Sep 09 04:35:27 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047621651 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1047621651
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2886380106
Short name	T397
Test name
Test status
Simulation time	83154489962 ps
CPU time	115.14 seconds
Started	Sep 09 04:30:35 AM UTC 24
Finished	Sep 09 04:32:32 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886380106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2886380106
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.795686809
Short name	T118
Test name
Test status
Simulation time	129191163543 ps
CPU time	417.52 seconds
Started	Sep 09 04:30:35 AM UTC 24
Finished	Sep 09 04:37:38 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795686809 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.795686809
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.1943685696
Short name	T152
Test name
Test status
Simulation time	24987184694 ps
CPU time	75.91 seconds
Started	Sep 09 04:30:47 AM UTC 24
Finished	Sep 09 04:32:05 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943685696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1943685696
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.1303960963
Short name	T24
Test name
Test status
Simulation time	3074605915 ps
CPU time	37.33 seconds
Started	Sep 09 04:30:48 AM UTC 24
Finished	Sep 09 04:31:27 AM UTC 24
Peak memory	203960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1303960963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.rv_timer_stress_all_with_rand_reset.1303960963
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.988203498
Short name	T345
Test name
Test status
Simulation time	4054793332738 ps
CPU time	980.7 seconds
Started	Sep 09 04:31:09 AM UTC 24
Finished	Sep 09 04:47:40 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988203498 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.988203498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.4031012585
Short name	T381
Test name
Test status
Simulation time	57908876349 ps
CPU time	49.45 seconds
Started	Sep 09 04:31:01 AM UTC 24
Finished	Sep 09 04:31:52 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031012585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4031012585
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1083432302
Short name	T389
Test name
Test status
Simulation time	116596892 ps
CPU time	1.11 seconds
Started	Sep 09 04:31:11 AM UTC 24
Finished	Sep 09 04:31:13 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083432302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1083432302
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.4051584824
Short name	T102
Test name
Test status
Simulation time	2224139955752 ps
CPU time	597.69 seconds
Started	Sep 09 04:31:29 AM UTC 24
Finished	Sep 09 04:41:34 AM UTC 24
Peak memory	199552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051584824 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.4051584824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.854795796
Short name	T49
Test name
Test status
Simulation time	702230385627 ps
CPU time	277.62 seconds
Started	Sep 09 04:31:29 AM UTC 24
Finished	Sep 09 04:36:10 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854795796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.854795796
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1728915906
Short name	T104
Test name
Test status
Simulation time	56626499868 ps
CPU time	71.48 seconds
Started	Sep 09 04:31:21 AM UTC 24
Finished	Sep 09 04:32:34 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728915906 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1728915906
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.1895076396
Short name	T47
Test name
Test status
Simulation time	39280475642 ps
CPU time	269.24 seconds
Started	Sep 09 04:31:29 AM UTC 24
Finished	Sep 09 04:36:02 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895076396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1895076396
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/23.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2424050437
Short name	T254
Test name
Test status
Simulation time	2279573876288 ps
CPU time	659.6 seconds
Started	Sep 09 04:32:03 AM UTC 24
Finished	Sep 09 04:43:11 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424050437 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2424050437
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.4170279514
Short name	T412
Test name
Test status
Simulation time	188899596862 ps
CPU time	379.29 seconds
Started	Sep 09 04:31:53 AM UTC 24
Finished	Sep 09 04:38:17 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170279514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4170279514
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.269677982
Short name	T131
Test name
Test status
Simulation time	47808213757 ps
CPU time	304.72 seconds
Started	Sep 09 04:31:51 AM UTC 24
Finished	Sep 09 04:37:00 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269677982 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.269677982
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.920041644
Short name	T377
Test name
Test status
Simulation time	928405871 ps
CPU time	2.77 seconds
Started	Sep 09 04:32:05 AM UTC 24
Finished	Sep 09 04:32:09 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920041644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.920041644
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/24.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.3034165787
Short name	T338
Test name
Test status
Simulation time	2593163492492 ps
CPU time	1029.56 seconds
Started	Sep 09 04:32:18 AM UTC 24
Finished	Sep 09 04:49:38 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034165787 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3034165787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.3514609506
Short name	T402
Test name
Test status
Simulation time	65465414665 ps
CPU time	60.87 seconds
Started	Sep 09 04:32:17 AM UTC 24
Finished	Sep 09 04:33:20 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514609506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3514609506
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.2551035999
Short name	T145
Test name
Test status
Simulation time	147183641031 ps
CPU time	99.49 seconds
Started	Sep 09 04:32:17 AM UTC 24
Finished	Sep 09 04:33:59 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551035999 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2551035999
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2733519567
Short name	T395
Test name
Test status
Simulation time	482068231 ps
CPU time	1.08 seconds
Started	Sep 09 04:32:22 AM UTC 24
Finished	Sep 09 04:32:24 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733519567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2733519567
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.88235100
Short name	T411
Test name
Test status
Simulation time	200858992683 ps
CPU time	333.08 seconds
Started	Sep 09 04:32:27 AM UTC 24
Finished	Sep 09 04:38:04 AM UTC 24
Peak memory	199760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88235100 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.88235100
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.3547618392
Short name	T25
Test name
Test status
Simulation time	661816426 ps
CPU time	6.88 seconds
Started	Sep 09 04:32:25 AM UTC 24
Finished	Sep 09 04:32:33 AM UTC 24
Peak memory	201776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3547618392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.rv_timer_stress_all_with_rand_reset.3547618392
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1823950183
Short name	T130
Test name
Test status
Simulation time	1241993084212 ps
CPU time	645.44 seconds
Started	Sep 09 04:32:33 AM UTC 24
Finished	Sep 09 04:43:26 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823950183 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1823950183
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1111593355
Short name	T403
Test name
Test status
Simulation time	74296175878 ps
CPU time	85.32 seconds
Started	Sep 09 04:32:33 AM UTC 24
Finished	Sep 09 04:34:00 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111593355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1111593355
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.1864606562
Short name	T46
Test name
Test status
Simulation time	124214710670 ps
CPU time	198.71 seconds
Started	Sep 09 04:32:31 AM UTC 24
Finished	Sep 09 04:35:52 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864606562 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1864606562
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1401687498
Short name	T248
Test name
Test status
Simulation time	77772325180 ps
CPU time	860.53 seconds
Started	Sep 09 04:32:33 AM UTC 24
Finished	Sep 09 04:47:03 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401687498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1401687498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all_with_rand_reset.152412825
Short name	T26
Test name
Test status
Simulation time	5880798037 ps
CPU time	54.75 seconds
Started	Sep 09 04:32:35 AM UTC 24
Finished	Sep 09 04:33:32 AM UTC 24
Peak memory	204032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=152412825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.152412825
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/26.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.2505021820
Short name	T201
Test name
Test status
Simulation time	84391852067 ps
CPU time	44.66 seconds
Started	Sep 09 04:32:40 AM UTC 24
Finished	Sep 09 04:33:26 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505021820 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2505021820
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.3584917434
Short name	T406
Test name
Test status
Simulation time	276125924173 ps
CPU time	245.32 seconds
Started	Sep 09 04:32:39 AM UTC 24
Finished	Sep 09 04:36:48 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584917434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3584917434
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.736178255
Short name	T110
Test name
Test status
Simulation time	195441108115 ps
CPU time	75.81 seconds
Started	Sep 09 04:32:37 AM UTC 24
Finished	Sep 09 04:33:55 AM UTC 24
Peak memory	199460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736178255 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.736178255
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.3700280617
Short name	T400
Test name
Test status
Simulation time	101407441 ps
CPU time	1.04 seconds
Started	Sep 09 04:32:41 AM UTC 24
Finished	Sep 09 04:32:44 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700280617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3700280617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/27.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.3064237489
Short name	T211
Test name
Test status
Simulation time	252724381 ps
CPU time	1.51 seconds
Started	Sep 09 04:33:19 AM UTC 24
Finished	Sep 09 04:33:21 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064237489 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3064237489
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3524498950
Short name	T413
Test name
Test status
Simulation time	111473980842 ps
CPU time	316.01 seconds
Started	Sep 09 04:33:05 AM UTC 24
Finished	Sep 09 04:38:25 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524498950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3524498950
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.1217178380
Short name	T150
Test name
Test status
Simulation time	109055476174 ps
CPU time	528.12 seconds
Started	Sep 09 04:33:04 AM UTC 24
Finished	Sep 09 04:41:58 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217178380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1217178380
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.3218437051
Short name	T351
Test name
Test status
Simulation time	40523508248 ps
CPU time	211.08 seconds
Started	Sep 09 04:33:21 AM UTC 24
Finished	Sep 09 04:36:55 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218437051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3218437051
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1750601345
Short name	T332
Test name
Test status
Simulation time	180456297662 ps
CPU time	299.66 seconds
Started	Sep 09 04:33:22 AM UTC 24
Finished	Sep 09 04:38:25 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750601345 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1750601345
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.4271711684
Short name	T122
Test name
Test status
Simulation time	370651602248 ps
CPU time	184.73 seconds
Started	Sep 09 04:33:32 AM UTC 24
Finished	Sep 09 04:36:40 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271711684 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.4271711684
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.2862291510
Short name	T409
Test name
Test status
Simulation time	100546504210 ps
CPU time	246.27 seconds
Started	Sep 09 04:33:30 AM UTC 24
Finished	Sep 09 04:37:40 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862291510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2862291510
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.4061061160
Short name	T129
Test name
Test status
Simulation time	554006237228 ps
CPU time	422.93 seconds
Started	Sep 09 04:33:27 AM UTC 24
Finished	Sep 09 04:40:36 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061061160 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4061061160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.17815022
Short name	T208
Test name
Test status
Simulation time	202880890166 ps
CPU time	1121.16 seconds
Started	Sep 09 04:33:57 AM UTC 24
Finished	Sep 09 04:52:51 AM UTC 24
Peak memory	202560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17815022 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.17815022
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/29.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.1599907670
Short name	T23
Test name
Test status
Simulation time	109567597708 ps
CPU time	57.59 seconds
Started	Sep 09 04:25:30 AM UTC 24
Finished	Sep 09 04:26:29 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599907670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1599907670
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3850710159
Short name	T99
Test name
Test status
Simulation time	148924585705 ps
CPU time	773.83 seconds
Started	Sep 09 04:25:27 AM UTC 24
Finished	Sep 09 04:38:29 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850710159 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3850710159
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.2397882497
Short name	T33
Test name
Test status
Simulation time	108880968292 ps
CPU time	87.08 seconds
Started	Sep 09 04:25:34 AM UTC 24
Finished	Sep 09 04:27:03 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397882497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2397882497
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.4259353666
Short name	T6
Test name
Test status
Simulation time	110702575 ps
CPU time	1.24 seconds
Started	Sep 09 04:25:42 AM UTC 24
Finished	Sep 09 04:25:44 AM UTC 24
Peak memory	228940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259353666 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4259353666
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.1088936934
Short name	T399
Test name
Test status
Simulation time	263422888058 ps
CPU time	413.89 seconds
Started	Sep 09 04:25:42 AM UTC 24
Finished	Sep 09 04:32:41 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088936934 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.1088936934
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/3.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.123073521
Short name	T151
Test name
Test status
Simulation time	171418390941 ps
CPU time	583.29 seconds
Started	Sep 09 04:34:02 AM UTC 24
Finished	Sep 09 04:43:52 AM UTC 24
Peak memory	199584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123073521 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.123073521
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.704299853
Short name	T410
Test name
Test status
Simulation time	614418737013 ps
CPU time	235.62 seconds
Started	Sep 09 04:34:01 AM UTC 24
Finished	Sep 09 04:37:59 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704299853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.704299853
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3246091780
Short name	T228
Test name
Test status
Simulation time	147611041546 ps
CPU time	1069.91 seconds
Started	Sep 09 04:34:00 AM UTC 24
Finished	Sep 09 04:52:02 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246091780 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3246091780
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.3864504975
Short name	T404
Test name
Test status
Simulation time	7041984889 ps
CPU time	9.83 seconds
Started	Sep 09 04:34:17 AM UTC 24
Finished	Sep 09 04:34:28 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864504975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3864504975
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.123580867
Short name	T421
Test name
Test status
Simulation time	144994584197 ps
CPU time	438.75 seconds
Started	Sep 09 04:34:29 AM UTC 24
Finished	Sep 09 04:41:54 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123580867 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.123580867
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.1229663456
Short name	T27
Test name
Test status
Simulation time	8275035921 ps
CPU time	50.62 seconds
Started	Sep 09 04:34:19 AM UTC 24
Finished	Sep 09 04:35:11 AM UTC 24
Peak memory	203924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1229663456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.rv_timer_stress_all_with_rand_reset.1229663456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.934099478
Short name	T408
Test name
Test status
Simulation time	221676638441 ps
CPU time	123.55 seconds
Started	Sep 09 04:34:55 AM UTC 24
Finished	Sep 09 04:37:02 AM UTC 24
Peak memory	199752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934099478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.934099478
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.3913228118
Short name	T50
Test name
Test status
Simulation time	47685505217 ps
CPU time	110.55 seconds
Started	Sep 09 04:34:31 AM UTC 24
Finished	Sep 09 04:36:24 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913228118 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3913228118
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/31.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.3063195135
Short name	T184
Test name
Test status
Simulation time	1802011886134 ps
CPU time	1424.43 seconds
Started	Sep 09 04:36:10 AM UTC 24
Finished	Sep 09 05:00:10 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063195135 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3063195135
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.4115778093
Short name	T407
Test name
Test status
Simulation time	24952334572 ps
CPU time	46.61 seconds
Started	Sep 09 04:36:03 AM UTC 24
Finished	Sep 09 04:36:51 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115778093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4115778093
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.3489808664
Short name	T164
Test name
Test status
Simulation time	3207901673369 ps
CPU time	1083.6 seconds
Started	Sep 09 04:35:53 AM UTC 24
Finished	Sep 09 04:54:08 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489808664 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3489808664
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.3092329549
Short name	T137
Test name
Test status
Simulation time	225777155929 ps
CPU time	93.15 seconds
Started	Sep 09 04:36:11 AM UTC 24
Finished	Sep 09 04:37:46 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092329549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3092329549
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/32.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1449970278
Short name	T134
Test name
Test status
Simulation time	49566097938 ps
CPU time	77.76 seconds
Started	Sep 09 04:36:41 AM UTC 24
Finished	Sep 09 04:38:01 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449970278 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1449970278
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.3999513873
Short name	T416
Test name
Test status
Simulation time	76987293036 ps
CPU time	167.82 seconds
Started	Sep 09 04:36:40 AM UTC 24
Finished	Sep 09 04:39:31 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999513873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3999513873
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.2651343837
Short name	T244
Test name
Test status
Simulation time	1896015602 ps
CPU time	8.07 seconds
Started	Sep 09 04:36:30 AM UTC 24
Finished	Sep 09 04:36:39 AM UTC 24
Peak memory	199532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651343837 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2651343837
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/33.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.3741004957
Short name	T157
Test name
Test status
Simulation time	38734385533 ps
CPU time	66.07 seconds
Started	Sep 09 04:36:58 AM UTC 24
Finished	Sep 09 04:38:05 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741004957 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.3741004957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.3813066896
Short name	T419
Test name
Test status
Simulation time	807278334905 ps
CPU time	214.36 seconds
Started	Sep 09 04:36:56 AM UTC 24
Finished	Sep 09 04:40:33 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813066896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3813066896
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.4060061724
Short name	T170
Test name
Test status
Simulation time	273929839732 ps
CPU time	703.69 seconds
Started	Sep 09 04:36:52 AM UTC 24
Finished	Sep 09 04:48:44 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060061724 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4060061724
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.1862487223
Short name	T142
Test name
Test status
Simulation time	15505589637 ps
CPU time	48.16 seconds
Started	Sep 09 04:36:58 AM UTC 24
Finished	Sep 09 04:37:47 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862487223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1862487223
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.3294427146
Short name	T301
Test name
Test status
Simulation time	2708360585419 ps
CPU time	1806.62 seconds
Started	Sep 09 04:37:03 AM UTC 24
Finished	Sep 09 05:07:27 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294427146 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.3294427146
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/34.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.1056341775
Short name	T417
Test name
Test status
Simulation time	63362396190 ps
CPU time	115.29 seconds
Started	Sep 09 04:37:34 AM UTC 24
Finished	Sep 09 04:39:31 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056341775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1056341775
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2381406103
Short name	T212
Test name
Test status
Simulation time	420782863798 ps
CPU time	416.85 seconds
Started	Sep 09 04:37:15 AM UTC 24
Finished	Sep 09 04:44:18 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381406103 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2381406103
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.3704685004
Short name	T414
Test name
Test status
Simulation time	89993400061 ps
CPU time	67.05 seconds
Started	Sep 09 04:37:48 AM UTC 24
Finished	Sep 09 04:38:57 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704685004 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.3704685004
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/35.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.1779755153
Short name	T183
Test name
Test status
Simulation time	260812515361 ps
CPU time	409.06 seconds
Started	Sep 09 04:38:04 AM UTC 24
Finished	Sep 09 04:44:58 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779755153 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1779755153
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3904817443
Short name	T415
Test name
Test status
Simulation time	39831379841 ps
CPU time	59.38 seconds
Started	Sep 09 04:38:01 AM UTC 24
Finished	Sep 09 04:39:02 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904817443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3904817443
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3925749920
Short name	T143
Test name
Test status
Simulation time	16213082635 ps
CPU time	22.03 seconds
Started	Sep 09 04:38:00 AM UTC 24
Finished	Sep 09 04:38:24 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925749920 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3925749920
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.845264245
Short name	T221
Test name
Test status
Simulation time	231065325969 ps
CPU time	1638.03 seconds
Started	Sep 09 04:38:07 AM UTC 24
Finished	Sep 09 05:05:42 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845264245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.845264245
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/36.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.138863870
Short name	T313
Test name
Test status
Simulation time	1736927473275 ps
CPU time	337.15 seconds
Started	Sep 09 04:38:26 AM UTC 24
Finished	Sep 09 04:44:07 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138863870 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.138863870
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.1222431552
Short name	T418
Test name
Test status
Simulation time	180004324964 ps
CPU time	96.21 seconds
Started	Sep 09 04:38:26 AM UTC 24
Finished	Sep 09 04:40:04 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222431552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1222431552
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.3222124940
Short name	T191
Test name
Test status
Simulation time	334668258135 ps
CPU time	518.87 seconds
Started	Sep 09 04:38:24 AM UTC 24
Finished	Sep 09 04:47:09 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222124940 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3222124940
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2530087878
Short name	T128
Test name
Test status
Simulation time	25659290374 ps
CPU time	240.32 seconds
Started	Sep 09 04:38:30 AM UTC 24
Finished	Sep 09 04:42:34 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530087878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2530087878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.4138760878
Short name	T432
Test name
Test status
Simulation time	204955476350 ps
CPU time	477.02 seconds
Started	Sep 09 04:38:35 AM UTC 24
Finished	Sep 09 04:46:38 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138760878 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.4138760878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/37.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.194848333
Short name	T144
Test name
Test status
Simulation time	150798778890 ps
CPU time	184.11 seconds
Started	Sep 09 04:39:07 AM UTC 24
Finished	Sep 09 04:42:14 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194848333 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.194848333
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2600491658
Short name	T431
Test name
Test status
Simulation time	708451548080 ps
CPU time	431.41 seconds
Started	Sep 09 04:39:03 AM UTC 24
Finished	Sep 09 04:46:20 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600491658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2600491658
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.1392881538
Short name	T292
Test name
Test status
Simulation time	31561290548 ps
CPU time	39.98 seconds
Started	Sep 09 04:39:07 AM UTC 24
Finished	Sep 09 04:39:49 AM UTC 24
Peak memory	199916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392881538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1392881538
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/38.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.499041214
Short name	T182
Test name
Test status
Simulation time	619149969344 ps
CPU time	444.54 seconds
Started	Sep 09 04:39:30 AM UTC 24
Finished	Sep 09 04:47:00 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499041214 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.499041214
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.3058626733
Short name	T420
Test name
Test status
Simulation time	27974832819 ps
CPU time	101.38 seconds
Started	Sep 09 04:39:28 AM UTC 24
Finished	Sep 09 04:41:11 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058626733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3058626733
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.950159148
Short name	T311
Test name
Test status
Simulation time	99021199386 ps
CPU time	346.17 seconds
Started	Sep 09 04:39:26 AM UTC 24
Finished	Sep 09 04:45:16 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950159148 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.950159148
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2458746000
Short name	T120
Test name
Test status
Simulation time	105444326740 ps
CPU time	94 seconds
Started	Sep 09 04:39:32 AM UTC 24
Finished	Sep 09 04:41:08 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458746000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2458746000
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all_with_rand_reset.2023342386
Short name	T28
Test name
Test status
Simulation time	3333445680 ps
CPU time	9.79 seconds
Started	Sep 09 04:39:32 AM UTC 24
Finished	Sep 09 04:39:43 AM UTC 24
Peak memory	201784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2023342386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.rv_timer_stress_all_with_rand_reset.2023342386
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/39.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.62662860
Short name	T135
Test name
Test status
Simulation time	463187587899 ps
CPU time	815.92 seconds
Started	Sep 09 04:25:44 AM UTC 24
Finished	Sep 09 04:39:29 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62662860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.62662860
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.3854922631
Short name	T32
Test name
Test status
Simulation time	404976083605 ps
CPU time	75.4 seconds
Started	Sep 09 04:25:44 AM UTC 24
Finished	Sep 09 04:27:01 AM UTC 24
Peak memory	199912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854922631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3854922631
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.416198901
Short name	T35
Test name
Test status
Simulation time	49617539516 ps
CPU time	91.07 seconds
Started	Sep 09 04:25:42 AM UTC 24
Finished	Sep 09 04:27:15 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416198901 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.416198901
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.3161136214
Short name	T14
Test name
Test status
Simulation time	43148919605 ps
CPU time	28.68 seconds
Started	Sep 09 04:25:44 AM UTC 24
Finished	Sep 09 04:26:14 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161136214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3161136214
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.2138879502
Short name	T7
Test name
Test status
Simulation time	272997975 ps
CPU time	1.21 seconds
Started	Sep 09 04:25:49 AM UTC 24
Finished	Sep 09 04:25:51 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138879502 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2138879502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.165308642
Short name	T175
Test name
Test status
Simulation time	374030803761 ps
CPU time	692.26 seconds
Started	Sep 09 04:40:34 AM UTC 24
Finished	Sep 09 04:52:14 AM UTC 24
Peak memory	199584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165308642 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.165308642
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.913286803
Short name	T422
Test name
Test status
Simulation time	191568414658 ps
CPU time	129.04 seconds
Started	Sep 09 04:40:05 AM UTC 24
Finished	Sep 09 04:42:16 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913286803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.913286803
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.3799641114
Short name	T199
Test name
Test status
Simulation time	159298978025 ps
CPU time	370.97 seconds
Started	Sep 09 04:39:50 AM UTC 24
Finished	Sep 09 04:46:06 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799641114 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3799641114
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.4228441401
Short name	T299
Test name
Test status
Simulation time	102998091622 ps
CPU time	238.74 seconds
Started	Sep 09 04:40:36 AM UTC 24
Finished	Sep 09 04:44:39 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228441401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4228441401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.2587514170
Short name	T29
Test name
Test status
Simulation time	2105587190 ps
CPU time	35.02 seconds
Started	Sep 09 04:40:44 AM UTC 24
Finished	Sep 09 04:41:21 AM UTC 24
Peak memory	201776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2587514170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.rv_timer_stress_all_with_rand_reset.2587514170
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.907185558
Short name	T185
Test name
Test status
Simulation time	157742333550 ps
CPU time	59.25 seconds
Started	Sep 09 04:41:22 AM UTC 24
Finished	Sep 09 04:42:23 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907185558 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.907185558
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.2472896813
Short name	T429
Test name
Test status
Simulation time	89036119707 ps
CPU time	270.23 seconds
Started	Sep 09 04:41:12 AM UTC 24
Finished	Sep 09 04:45:46 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472896813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2472896813
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.213469194
Short name	T272
Test name
Test status
Simulation time	91903956764 ps
CPU time	601.36 seconds
Started	Sep 09 04:41:09 AM UTC 24
Finished	Sep 09 04:51:18 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213469194 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.213469194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.2311172422
Short name	T339
Test name
Test status
Simulation time	47427239125 ps
CPU time	460.9 seconds
Started	Sep 09 04:41:34 AM UTC 24
Finished	Sep 09 04:49:21 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311172422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2311172422
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/41.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3677935250
Short name	T168
Test name
Test status
Simulation time	185171245458 ps
CPU time	164.94 seconds
Started	Sep 09 04:41:59 AM UTC 24
Finished	Sep 09 04:44:47 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677935250 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3677935250
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.1783468948
Short name	T425
Test name
Test status
Simulation time	73205828799 ps
CPU time	176.85 seconds
Started	Sep 09 04:41:54 AM UTC 24
Finished	Sep 09 04:44:54 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783468948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1783468948
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.3834150313
Short name	T266
Test name
Test status
Simulation time	90863580186 ps
CPU time	1050.91 seconds
Started	Sep 09 04:41:53 AM UTC 24
Finished	Sep 09 04:59:37 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834150313 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3834150313
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.3296181903
Short name	T437
Test name
Test status
Simulation time	98044366621 ps
CPU time	447.09 seconds
Started	Sep 09 04:42:16 AM UTC 24
Finished	Sep 09 04:49:48 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296181903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3296181903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all_with_rand_reset.2357108088
Short name	T30
Test name
Test status
Simulation time	4022560228 ps
CPU time	29.93 seconds
Started	Sep 09 04:42:18 AM UTC 24
Finished	Sep 09 04:42:49 AM UTC 24
Peak memory	205936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2357108088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.rv_timer_stress_all_with_rand_reset.2357108088
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.3571209554
Short name	T169
Test name
Test status
Simulation time	228716081886 ps
CPU time	317.57 seconds
Started	Sep 09 04:42:51 AM UTC 24
Finished	Sep 09 04:48:12 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571209554 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3571209554
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.1431676695
Short name	T427
Test name
Test status
Simulation time	192933246356 ps
CPU time	166.18 seconds
Started	Sep 09 04:42:50 AM UTC 24
Finished	Sep 09 04:45:38 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431676695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1431676695
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3525434524
Short name	T265
Test name
Test status
Simulation time	512242015278 ps
CPU time	528.89 seconds
Started	Sep 09 04:42:35 AM UTC 24
Finished	Sep 09 04:51:30 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525434524 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3525434524
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2715070184
Short name	T316
Test name
Test status
Simulation time	40428785605 ps
CPU time	94.28 seconds
Started	Sep 09 04:43:12 AM UTC 24
Finished	Sep 09 04:44:48 AM UTC 24
Peak memory	199720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715070184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2715070184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.1815487303
Short name	T423
Test name
Test status
Simulation time	29896216 ps
CPU time	0.91 seconds
Started	Sep 09 04:43:26 AM UTC 24
Finished	Sep 09 04:43:28 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815487303 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.1815487303
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/43.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.4123906818
Short name	T434
Test name
Test status
Simulation time	157832507957 ps
CPU time	273.53 seconds
Started	Sep 09 04:43:53 AM UTC 24
Finished	Sep 09 04:48:31 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123906818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4123906818
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.1489108739
Short name	T154
Test name
Test status
Simulation time	138599888022 ps
CPU time	144.44 seconds
Started	Sep 09 04:43:29 AM UTC 24
Finished	Sep 09 04:45:56 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489108739 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1489108739
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2021537658
Short name	T424
Test name
Test status
Simulation time	41754367 ps
CPU time	0.89 seconds
Started	Sep 09 04:44:08 AM UTC 24
Finished	Sep 09 04:44:09 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021537658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2021537658
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.725415545
Short name	T436
Test name
Test status
Simulation time	713878668157 ps
CPU time	283.5 seconds
Started	Sep 09 04:44:19 AM UTC 24
Finished	Sep 09 04:49:06 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725415545 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.725415545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.361278436
Short name	T426
Test name
Test status
Simulation time	11121550267 ps
CPU time	54.73 seconds
Started	Sep 09 04:44:11 AM UTC 24
Finished	Sep 09 04:45:07 AM UTC 24
Peak memory	204096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=361278436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.361278436
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2539470845
Short name	T222
Test name
Test status
Simulation time	402295120688 ps
CPU time	321.95 seconds
Started	Sep 09 04:44:40 AM UTC 24
Finished	Sep 09 04:50:06 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539470845 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2539470845
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.354271554
Short name	T428
Test name
Test status
Simulation time	151690124892 ps
CPU time	61.06 seconds
Started	Sep 09 04:44:36 AM UTC 24
Finished	Sep 09 04:45:39 AM UTC 24
Peak memory	199880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354271554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.354271554
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.3530514772
Short name	T440
Test name
Test status
Simulation time	70778098757 ps
CPU time	875.29 seconds
Started	Sep 09 04:44:22 AM UTC 24
Finished	Sep 09 04:59:08 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530514772 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3530514772
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1616590931
Short name	T349
Test name
Test status
Simulation time	31419311855 ps
CPU time	76.6 seconds
Started	Sep 09 04:44:45 AM UTC 24
Finished	Sep 09 04:46:03 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616590931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1616590931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3486820995
Short name	T59
Test name
Test status
Simulation time	848127919555 ps
CPU time	1968.97 seconds
Started	Sep 09 04:44:48 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486820995 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3486820995
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all_with_rand_reset.1637664955
Short name	T38
Test name
Test status
Simulation time	4761004404 ps
CPU time	58.39 seconds
Started	Sep 09 04:44:45 AM UTC 24
Finished	Sep 09 04:45:45 AM UTC 24
Peak memory	204024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1637664955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.rv_timer_stress_all_with_rand_reset.1637664955
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/45.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.4152527344
Short name	T300
Test name
Test status
Simulation time	123288499089 ps
CPU time	232.19 seconds
Started	Sep 09 04:44:58 AM UTC 24
Finished	Sep 09 04:48:54 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152527344 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.4152527344
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.2643719188
Short name	T430
Test name
Test status
Simulation time	128383907966 ps
CPU time	61.46 seconds
Started	Sep 09 04:44:54 AM UTC 24
Finished	Sep 09 04:45:57 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643719188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2643719188
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.694878597
Short name	T450
Test name
Test status
Simulation time	183839625772 ps
CPU time	1910.04 seconds
Started	Sep 09 04:44:49 AM UTC 24
Finished	Sep 09 05:17:00 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694878597 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.694878597
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.1762906910
Short name	T298
Test name
Test status
Simulation time	137256294296 ps
CPU time	424.32 seconds
Started	Sep 09 04:45:08 AM UTC 24
Finished	Sep 09 04:52:17 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762906910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1762906910
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.782262359
Short name	T237
Test name
Test status
Simulation time	188754270466 ps
CPU time	452.41 seconds
Started	Sep 09 04:45:17 AM UTC 24
Finished	Sep 09 04:52:54 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782262359 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.782262359
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/46.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.2083273704
Short name	T282
Test name
Test status
Simulation time	89031310136 ps
CPU time	38.55 seconds
Started	Sep 09 04:45:40 AM UTC 24
Finished	Sep 09 04:46:20 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083273704 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2083273704
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.1558789954
Short name	T433
Test name
Test status
Simulation time	227574867539 ps
CPU time	167.38 seconds
Started	Sep 09 04:45:39 AM UTC 24
Finished	Sep 09 04:48:29 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558789954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1558789954
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.4037333740
Short name	T209
Test name
Test status
Simulation time	101338210624 ps
CPU time	486.46 seconds
Started	Sep 09 04:45:29 AM UTC 24
Finished	Sep 09 04:53:42 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037333740 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4037333740
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.499108781
Short name	T255
Test name
Test status
Simulation time	3611772323 ps
CPU time	12.62 seconds
Started	Sep 09 04:45:46 AM UTC 24
Finished	Sep 09 04:46:00 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499108781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.499108781
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/47.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.486469249
Short name	T348
Test name
Test status
Simulation time	541414211507 ps
CPU time	1108.18 seconds
Started	Sep 09 04:46:04 AM UTC 24
Finished	Sep 09 05:04:43 AM UTC 24
Peak memory	202324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486469249 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.486469249
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.529523003
Short name	T435
Test name
Test status
Simulation time	103522354568 ps
CPU time	161.54 seconds
Started	Sep 09 04:46:00 AM UTC 24
Finished	Sep 09 04:48:45 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529523003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.529523003
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.996233694
Short name	T186
Test name
Test status
Simulation time	903378362232 ps
CPU time	271.28 seconds
Started	Sep 09 04:45:58 AM UTC 24
Finished	Sep 09 04:50:33 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996233694 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.996233694
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3172178820
Short name	T166
Test name
Test status
Simulation time	99116235640 ps
CPU time	187.4 seconds
Started	Sep 09 04:46:05 AM UTC 24
Finished	Sep 09 04:49:15 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172178820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3172178820
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.2989082105
Short name	T340
Test name
Test status
Simulation time	144972045955 ps
CPU time	2064.64 seconds
Started	Sep 09 04:46:13 AM UTC 24
Finished	Sep 09 05:20:59 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989082105 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.2989082105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/48.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.1626317822
Short name	T438
Test name
Test status
Simulation time	305263732978 ps
CPU time	286 seconds
Started	Sep 09 04:46:21 AM UTC 24
Finished	Sep 09 04:51:11 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626317822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1626317822
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2339702200
Short name	T353
Test name
Test status
Simulation time	47446460565 ps
CPU time	65.3 seconds
Started	Sep 09 04:46:21 AM UTC 24
Finished	Sep 09 04:47:28 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339702200 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2339702200
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.164934186
Short name	T270
Test name
Test status
Simulation time	89553171908 ps
CPU time	122.73 seconds
Started	Sep 09 04:46:35 AM UTC 24
Finished	Sep 09 04:48:40 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164934186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.164934186
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/49.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.3491206526
Short name	T9
Test name
Test status
Simulation time	37976112567 ps
CPU time	9.86 seconds
Started	Sep 09 04:25:53 AM UTC 24
Finished	Sep 09 04:26:04 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491206526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3491206526
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/5.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.2307002233
Short name	T347
Test name
Test status
Simulation time	82769767206 ps
CPU time	1357.39 seconds
Started	Sep 09 04:47:00 AM UTC 24
Finished	Sep 09 05:09:53 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307002233 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2307002233
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/50.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2407851216
Short name	T294
Test name
Test status
Simulation time	30683825322 ps
CPU time	105.82 seconds
Started	Sep 09 04:47:02 AM UTC 24
Finished	Sep 09 04:48:50 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407851216 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2407851216
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/51.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3623134952
Short name	T107
Test name
Test status
Simulation time	182708828752 ps
CPU time	146.1 seconds
Started	Sep 09 04:47:10 AM UTC 24
Finished	Sep 09 04:49:38 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623134952 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3623134952
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/53.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.2475580173
Short name	T253
Test name
Test status
Simulation time	301709619414 ps
CPU time	3295.25 seconds
Started	Sep 09 04:47:29 AM UTC 24
Finished	Sep 09 05:43:00 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475580173 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2475580173
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/54.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.2295009029
Short name	T318
Test name
Test status
Simulation time	1632519638924 ps
CPU time	971.24 seconds
Started	Sep 09 04:47:41 AM UTC 24
Finished	Sep 09 05:04:04 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295009029 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2295009029
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/55.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.2634620651
Short name	T256
Test name
Test status
Simulation time	31975700775 ps
CPU time	92.02 seconds
Started	Sep 09 04:48:13 AM UTC 24
Finished	Sep 09 04:49:47 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634620651 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2634620651
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/56.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2303068665
Short name	T192
Test name
Test status
Simulation time	554025197752 ps
CPU time	479.06 seconds
Started	Sep 09 04:48:18 AM UTC 24
Finished	Sep 09 04:56:23 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303068665 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2303068665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/57.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3520410105
Short name	T369
Test name
Test status
Simulation time	70628843857 ps
CPU time	712.79 seconds
Started	Sep 09 04:48:30 AM UTC 24
Finished	Sep 09 05:00:32 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520410105 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3520410105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/58.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.293718901
Short name	T44
Test name
Test status
Simulation time	1101337402297 ps
CPU time	556.49 seconds
Started	Sep 09 04:25:56 AM UTC 24
Finished	Sep 09 04:35:19 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293718901 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.293718901
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.2574585471
Short name	T391
Test name
Test status
Simulation time	307739252632 ps
CPU time	327.05 seconds
Started	Sep 09 04:25:56 AM UTC 24
Finished	Sep 09 04:31:27 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574585471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2574585471
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.674811999
Short name	T62
Test name
Test status
Simulation time	230875826547 ps
CPU time	260.37 seconds
Started	Sep 09 04:25:56 AM UTC 24
Finished	Sep 09 04:30:20 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674811999 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.674811999
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3222996680
Short name	T37
Test name
Test status
Simulation time	38790369426 ps
CPU time	100.19 seconds
Started	Sep 09 04:25:57 AM UTC 24
Finished	Sep 09 04:27:40 AM UTC 24
Peak memory	199796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222996680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3222996680
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.380335549
Short name	T108
Test name
Test status
Simulation time	116360745046 ps
CPU time	238.57 seconds
Started	Sep 09 04:25:58 AM UTC 24
Finished	Sep 09 04:30:00 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380335549 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.380335549
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/6.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2899677331
Short name	T220
Test name
Test status
Simulation time	72542860124 ps
CPU time	38.23 seconds
Started	Sep 09 04:48:41 AM UTC 24
Finished	Sep 09 04:49:20 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899677331 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2899677331
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/60.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.4148640591
Short name	T331
Test name
Test status
Simulation time	279947572792 ps
CPU time	149.73 seconds
Started	Sep 09 04:48:46 AM UTC 24
Finished	Sep 09 04:51:18 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148640591 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4148640591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/62.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2560839626
Short name	T269
Test name
Test status
Simulation time	22155179502 ps
CPU time	22.41 seconds
Started	Sep 09 04:48:55 AM UTC 24
Finished	Sep 09 04:49:18 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560839626 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2560839626
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/64.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1465321910
Short name	T289
Test name
Test status
Simulation time	178675178631 ps
CPU time	360.65 seconds
Started	Sep 09 04:49:16 AM UTC 24
Finished	Sep 09 04:55:22 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465321910 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1465321910
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/66.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.60473675
Short name	T326
Test name
Test status
Simulation time	252244627961 ps
CPU time	103.29 seconds
Started	Sep 09 04:49:19 AM UTC 24
Finished	Sep 09 04:51:04 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60473675 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.60473675
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/67.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.1475588688
Short name	T232
Test name
Test status
Simulation time	133451539899 ps
CPU time	410.96 seconds
Started	Sep 09 04:49:21 AM UTC 24
Finished	Sep 09 04:56:18 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475588688 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1475588688
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/68.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.1915444842
Short name	T217
Test name
Test status
Simulation time	61744427401 ps
CPU time	84.99 seconds
Started	Sep 09 04:49:21 AM UTC 24
Finished	Sep 09 04:50:49 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915444842 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1915444842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/69.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.2890220737
Short name	T64
Test name
Test status
Simulation time	492136942057 ps
CPU time	261.74 seconds
Started	Sep 09 04:26:04 AM UTC 24
Finished	Sep 09 04:30:30 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890220737 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2890220737
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.4104460662
Short name	T383
Test name
Test status
Simulation time	76857380677 ps
CPU time	168.44 seconds
Started	Sep 09 04:26:04 AM UTC 24
Finished	Sep 09 04:28:55 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104460662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4104460662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.984002947
Short name	T31
Test name
Test status
Simulation time	50321402163 ps
CPU time	45.95 seconds
Started	Sep 09 04:26:00 AM UTC 24
Finished	Sep 09 04:26:47 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984002947 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.984002947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3492080293
Short name	T147
Test name
Test status
Simulation time	202127260335 ps
CPU time	98 seconds
Started	Sep 09 04:26:05 AM UTC 24
Finished	Sep 09 04:27:45 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492080293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3492080293
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2512931407
Short name	T401
Test name
Test status
Simulation time	2311217183970 ps
CPU time	410.03 seconds
Started	Sep 09 04:26:07 AM UTC 24
Finished	Sep 09 04:33:02 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512931407 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2512931407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/7.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.2564246490
Short name	T190
Test name
Test status
Simulation time	319939914718 ps
CPU time	340.16 seconds
Started	Sep 09 04:49:37 AM UTC 24
Finished	Sep 09 04:55:22 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564246490 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2564246490
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/70.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.603995685
Short name	T181
Test name
Test status
Simulation time	85462341672 ps
CPU time	143.39 seconds
Started	Sep 09 04:49:39 AM UTC 24
Finished	Sep 09 04:52:04 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603995685 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.603995685
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/71.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.641889993
Short name	T261
Test name
Test status
Simulation time	54485283041 ps
CPU time	146.09 seconds
Started	Sep 09 04:49:40 AM UTC 24
Finished	Sep 09 04:52:08 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641889993 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.641889993
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/72.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3167601494
Short name	T327
Test name
Test status
Simulation time	220916358908 ps
CPU time	338 seconds
Started	Sep 09 04:49:41 AM UTC 24
Finished	Sep 09 04:55:24 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167601494 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3167601494
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/73.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.244098275
Short name	T314
Test name
Test status
Simulation time	361429356929 ps
CPU time	223.88 seconds
Started	Sep 09 04:49:48 AM UTC 24
Finished	Sep 09 04:53:35 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244098275 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.244098275
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/74.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.3653289053
Short name	T259
Test name
Test status
Simulation time	161042042423 ps
CPU time	620.06 seconds
Started	Sep 09 04:49:49 AM UTC 24
Finished	Sep 09 05:00:16 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653289053 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3653289053
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/75.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1582041599
Short name	T343
Test name
Test status
Simulation time	100783384818 ps
CPU time	377.34 seconds
Started	Sep 09 04:50:07 AM UTC 24
Finished	Sep 09 04:56:29 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582041599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1582041599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/76.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.1342293598
Short name	T189
Test name
Test status
Simulation time	69438385911 ps
CPU time	216.06 seconds
Started	Sep 09 04:50:15 AM UTC 24
Finished	Sep 09 04:53:54 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342293598 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1342293598
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/77.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.633442662
Short name	T330
Test name
Test status
Simulation time	275307921980 ps
CPU time	146.38 seconds
Started	Sep 09 04:50:34 AM UTC 24
Finished	Sep 09 04:53:03 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633442662 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.633442662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/78.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.636856979
Short name	T111
Test name
Test status
Simulation time	208533441566 ps
CPU time	409.1 seconds
Started	Sep 09 04:26:10 AM UTC 24
Finished	Sep 09 04:33:04 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636856979 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.636856979
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.453230959
Short name	T48
Test name
Test status
Simulation time	209315189404 ps
CPU time	578.55 seconds
Started	Sep 09 04:26:24 AM UTC 24
Finished	Sep 09 04:36:09 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453230959 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.453230959
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1920281254
Short name	T324
Test name
Test status
Simulation time	8734506777 ps
CPU time	21.01 seconds
Started	Sep 09 04:50:52 AM UTC 24
Finished	Sep 09 04:51:14 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920281254 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1920281254
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/80.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.2190626965
Short name	T233
Test name
Test status
Simulation time	53692917188 ps
CPU time	403.21 seconds
Started	Sep 09 04:51:06 AM UTC 24
Finished	Sep 09 04:57:55 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190626965 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2190626965
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/81.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3582135021
Short name	T286
Test name
Test status
Simulation time	325778172369 ps
CPU time	218.73 seconds
Started	Sep 09 04:51:12 AM UTC 24
Finished	Sep 09 04:54:54 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582135021 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3582135021
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/82.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.1485996799
Short name	T361
Test name
Test status
Simulation time	39758186083 ps
CPU time	419.85 seconds
Started	Sep 09 04:51:15 AM UTC 24
Finished	Sep 09 04:58:20 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485996799 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1485996799
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/83.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.2002023121
Short name	T297
Test name
Test status
Simulation time	208195006789 ps
CPU time	119.07 seconds
Started	Sep 09 04:51:19 AM UTC 24
Finished	Sep 09 04:53:20 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002023121 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2002023121
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/84.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1198483691
Short name	T309
Test name
Test status
Simulation time	438033400069 ps
CPU time	460.93 seconds
Started	Sep 09 04:51:19 AM UTC 24
Finished	Sep 09 04:59:06 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198483691 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1198483691
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/85.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2566250422
Short name	T352
Test name
Test status
Simulation time	159647385540 ps
CPU time	88.89 seconds
Started	Sep 09 04:51:31 AM UTC 24
Finished	Sep 09 04:53:02 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566250422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2566250422
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/86.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.666116387
Short name	T160
Test name
Test status
Simulation time	117331970273 ps
CPU time	188.73 seconds
Started	Sep 09 04:52:02 AM UTC 24
Finished	Sep 09 04:55:14 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666116387 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.666116387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/87.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.2227652755
Short name	T295
Test name
Test status
Simulation time	193828719347 ps
CPU time	356.13 seconds
Started	Sep 09 04:52:03 AM UTC 24
Finished	Sep 09 04:58:04 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227652755 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2227652755
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/88.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.341412266
Short name	T180
Test name
Test status
Simulation time	920135733476 ps
CPU time	1929.88 seconds
Started	Sep 09 04:52:05 AM UTC 24
Finished	Sep 09 05:24:37 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341412266 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.341412266
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/89.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.1293141504
Short name	T148
Test name
Test status
Simulation time	308235597526 ps
CPU time	178.81 seconds
Started	Sep 09 04:26:31 AM UTC 24
Finished	Sep 09 04:29:32 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293141504 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1293141504
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.4179792663
Short name	T382
Test name
Test status
Simulation time	335242994096 ps
CPU time	96.94 seconds
Started	Sep 09 04:26:30 AM UTC 24
Finished	Sep 09 04:28:09 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179792663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4179792663
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2400927065
Short name	T96
Test name
Test status
Simulation time	113271687647 ps
CPU time	285.68 seconds
Started	Sep 09 04:26:26 AM UTC 24
Finished	Sep 09 04:31:15 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400927065 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2400927065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.53156252
Short name	T121
Test name
Test status
Simulation time	129866942349 ps
CPU time	91.53 seconds
Started	Sep 09 04:26:32 AM UTC 24
Finished	Sep 09 04:28:05 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53156252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.53156252
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.1509952178
Short name	T123
Test name
Test status
Simulation time	473531554580 ps
CPU time	449.35 seconds
Started	Sep 09 04:26:41 AM UTC 24
Finished	Sep 09 04:34:16 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509952178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.1509952178
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/9.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.2810469527
Short name	T236
Test name
Test status
Simulation time	512214748819 ps
CPU time	355.6 seconds
Started	Sep 09 04:52:08 AM UTC 24
Finished	Sep 09 04:58:08 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810469527 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2810469527
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/90.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.1971504900
Short name	T224
Test name
Test status
Simulation time	66212117956 ps
CPU time	101.54 seconds
Started	Sep 09 04:52:10 AM UTC 24
Finished	Sep 09 04:53:53 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971504900 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1971504900
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/91.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.2047741767
Short name	T439
Test name
Test status
Simulation time	23338210860 ps
CPU time	71.42 seconds
Started	Sep 09 04:52:15 AM UTC 24
Finished	Sep 09 04:53:28 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047741767 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2047741767
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/92.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2049108606
Short name	T250
Test name
Test status
Simulation time	596015058997 ps
CPU time	270.96 seconds
Started	Sep 09 04:52:16 AM UTC 24
Finished	Sep 09 04:56:50 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049108606 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2049108606
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/93.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.645833940
Short name	T290
Test name
Test status
Simulation time	170934598029 ps
CPU time	308.37 seconds
Started	Sep 09 04:52:18 AM UTC 24
Finished	Sep 09 04:57:30 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645833940 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.645833940
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/94.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1634993409
Short name	T342
Test name
Test status
Simulation time	68229294342 ps
CPU time	68.46 seconds
Started	Sep 09 04:52:23 AM UTC 24
Finished	Sep 09 04:53:33 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634993409 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1634993409
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/95.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.2134652629
Short name	T174
Test name
Test status
Simulation time	128310833199 ps
CPU time	111.13 seconds
Started	Sep 09 04:52:52 AM UTC 24
Finished	Sep 09 04:54:45 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134652629 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2134652629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/96.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.7367532
Short name	T210
Test name
Test status
Simulation time	1244481022357 ps
CPU time	416.45 seconds
Started	Sep 09 04:52:55 AM UTC 24
Finished	Sep 09 04:59:57 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7367532 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.7367532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/97.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.3756969809
Short name	T346
Test name
Test status
Simulation time	182006579013 ps
CPU time	122.92 seconds
Started	Sep 09 04:53:02 AM UTC 24
Finished	Sep 09 04:55:07 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756969809 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3756969809
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/98.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3182316564
Short name	T344
Test name
Test status
Simulation time	456492722751 ps
CPU time	318.78 seconds
Started	Sep 09 04:53:03 AM UTC 24
Finished	Sep 09 04:58:27 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182316564 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3182316564
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/99.rv_timer_random/latest