Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 0 5 100.00
Crosses 4 0 4 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 1 0 1 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 4 0 4 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 136552308 1 T1 19 T3 187 T8 266


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 65650148 1 T1 10 T3 187 T8 256
auto[1] 70902160 1 T1 9 T8 10 T9 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 136546225 1 T1 19 T3 187 T8 266
auto[1] 6083 1 T9 13 T11 25 T13 2


Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 65646978 1 T1 10 T3 187 T8 256
all_values[0] auto[0] auto[1] 3170 1 T9 6 T11 8 T13 2
all_values[0] auto[1] auto[0] 70899247 1 T1 9 T8 10 T9 9
all_values[0] auto[1] auto[1] 2913 1 T9 7 T11 17 T12 42