Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.72	99.36	99.04	100.00		100.00	100.00	99.89

Total test records in report: 579

T503	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.794904894	Sep 11 02:12:55 AM UTC 24	Sep 11 02:12:58 AM UTC 24	18861127 ps
T504	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.507174274	Sep 11 02:12:57 AM UTC 24	Sep 11 02:12:59 AM UTC 24	13780240 ps
T505	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.2682408091	Sep 11 02:12:55 AM UTC 24	Sep 11 02:12:59 AM UTC 24	63075322 ps
T506	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3544856630	Sep 11 02:12:57 AM UTC 24	Sep 11 02:13:00 AM UTC 24	117155780 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.617251523	Sep 11 02:12:58 AM UTC 24	Sep 11 02:13:00 AM UTC 24	23738794 ps
T507	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1890479505	Sep 11 02:12:58 AM UTC 24	Sep 11 02:13:00 AM UTC 24	500898523 ps
T508	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2231761610	Sep 11 02:12:58 AM UTC 24	Sep 11 02:13:00 AM UTC 24	467701082 ps
T509	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1043572783	Sep 11 02:12:59 AM UTC 24	Sep 11 02:13:02 AM UTC 24	147834181 ps
T510	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.803866259	Sep 11 02:13:00 AM UTC 24	Sep 11 02:13:02 AM UTC 24	54502159 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1841638936	Sep 11 02:13:00 AM UTC 24	Sep 11 02:13:02 AM UTC 24	12884666 ps
T511	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2577725528	Sep 11 02:13:01 AM UTC 24	Sep 11 02:13:03 AM UTC 24	17457818 ps
T512	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2328962792	Sep 11 02:13:01 AM UTC 24	Sep 11 02:13:04 AM UTC 24	156669569 ps
T513	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2431252093	Sep 11 02:13:25 AM UTC 24	Sep 11 02:13:27 AM UTC 24	80617918 ps
T514	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2340158697	Sep 11 02:13:01 AM UTC 24	Sep 11 02:13:04 AM UTC 24	27031196 ps
T515	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1846441872	Sep 11 02:12:59 AM UTC 24	Sep 11 02:13:04 AM UTC 24	219602039 ps
T516	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3226335104	Sep 11 02:13:03 AM UTC 24	Sep 11 02:13:05 AM UTC 24	599871510 ps
T517	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3494503692	Sep 11 02:13:04 AM UTC 24	Sep 11 02:13:05 AM UTC 24	21825223 ps
T518	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1304732521	Sep 11 02:13:04 AM UTC 24	Sep 11 02:13:05 AM UTC 24	24637777 ps
T519	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3219630434	Sep 11 02:13:05 AM UTC 24	Sep 11 02:13:07 AM UTC 24	33703836 ps
T520	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3441003293	Sep 11 02:13:05 AM UTC 24	Sep 11 02:13:07 AM UTC 24	23829548 ps
T521	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3772645764	Sep 11 02:13:05 AM UTC 24	Sep 11 02:13:08 AM UTC 24	163110856 ps
T522	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.629939312	Sep 11 02:13:06 AM UTC 24	Sep 11 02:13:08 AM UTC 24	70699502 ps
T523	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3686638009	Sep 11 02:13:06 AM UTC 24	Sep 11 02:13:08 AM UTC 24	24880764 ps
T524	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3188593436	Sep 11 02:13:05 AM UTC 24	Sep 11 02:13:08 AM UTC 24	31081087 ps
T525	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3883264030	Sep 11 02:13:06 AM UTC 24	Sep 11 02:13:08 AM UTC 24	31817202 ps
T526	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1633071839	Sep 11 02:13:07 AM UTC 24	Sep 11 02:13:09 AM UTC 24	53154383 ps
T527	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.600828785	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	17439223 ps
T528	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1775149493	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	85056339 ps
T529	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2960184469	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	50021192 ps
T530	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1920250190	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	96731938 ps
T531	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.156418363	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	45572264 ps
T532	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1345037398	Sep 11 02:13:09 AM UTC 24	Sep 11 02:13:11 AM UTC 24	32931955 ps
T533	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2705180052	Sep 11 02:13:25 AM UTC 24	Sep 11 02:13:27 AM UTC 24	41330509 ps
T534	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3536011283	Sep 11 02:13:10 AM UTC 24	Sep 11 02:13:13 AM UTC 24	528988141 ps
T535	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3433192009	Sep 11 02:13:11 AM UTC 24	Sep 11 02:13:13 AM UTC 24	128920822 ps
T536	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3287125126	Sep 11 02:13:11 AM UTC 24	Sep 11 02:13:14 AM UTC 24	318029696 ps
T537	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.3994885557	Sep 11 02:13:12 AM UTC 24	Sep 11 02:13:14 AM UTC 24	14198198 ps
T538	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.982201807	Sep 11 02:13:12 AM UTC 24	Sep 11 02:13:14 AM UTC 24	153364075 ps
T539	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3198773012	Sep 11 02:13:12 AM UTC 24	Sep 11 02:13:15 AM UTC 24	82090830 ps
T540	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3299424270	Sep 11 02:13:14 AM UTC 24	Sep 11 02:13:15 AM UTC 24	32384582 ps
T541	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1581535950	Sep 11 02:13:14 AM UTC 24	Sep 11 02:13:16 AM UTC 24	74478504 ps
T542	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1318888698	Sep 11 02:13:12 AM UTC 24	Sep 11 02:13:17 AM UTC 24	184962609 ps
T543	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3010218851	Sep 11 02:13:14 AM UTC 24	Sep 11 02:13:17 AM UTC 24	100375582 ps
T544	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4028286462	Sep 11 02:13:15 AM UTC 24	Sep 11 02:13:17 AM UTC 24	31478240 ps
T545	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1987124937	Sep 11 02:13:15 AM UTC 24	Sep 11 02:13:17 AM UTC 24	59627886 ps
T546	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3843562681	Sep 11 02:13:16 AM UTC 24	Sep 11 02:13:18 AM UTC 24	13636997 ps
T547	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.631556907	Sep 11 02:13:16 AM UTC 24	Sep 11 02:13:18 AM UTC 24	51409221 ps
T548	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.882860589	Sep 11 02:13:16 AM UTC 24	Sep 11 02:13:18 AM UTC 24	53915029 ps
T549	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3088230877	Sep 11 02:13:17 AM UTC 24	Sep 11 02:13:19 AM UTC 24	11944719 ps
T550	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1935804655	Sep 11 02:13:17 AM UTC 24	Sep 11 02:13:19 AM UTC 24	14542135 ps
T551	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3071850889	Sep 11 02:13:17 AM UTC 24	Sep 11 02:13:19 AM UTC 24	59948251 ps
T552	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.953102680	Sep 11 02:13:17 AM UTC 24	Sep 11 02:13:20 AM UTC 24	54129441 ps
T553	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2948575222	Sep 11 02:13:19 AM UTC 24	Sep 11 02:13:20 AM UTC 24	54829557 ps
T554	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.4078709958	Sep 11 02:13:19 AM UTC 24	Sep 11 02:13:21 AM UTC 24	54378818 ps
T555	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3507578293	Sep 11 02:13:19 AM UTC 24	Sep 11 02:13:21 AM UTC 24	35484370 ps
T556	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1915894864	Sep 11 02:13:16 AM UTC 24	Sep 11 02:13:21 AM UTC 24	330356524 ps
T557	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3330948958	Sep 11 02:13:20 AM UTC 24	Sep 11 02:13:22 AM UTC 24	33381895 ps
T558	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.618187563	Sep 11 02:13:20 AM UTC 24	Sep 11 02:13:22 AM UTC 24	67750166 ps
T559	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1856127051	Sep 11 02:13:20 AM UTC 24	Sep 11 02:13:22 AM UTC 24	21215794 ps
T560	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1425689310	Sep 11 02:13:21 AM UTC 24	Sep 11 02:13:23 AM UTC 24	17390822 ps
T561	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3607509832	Sep 11 02:13:21 AM UTC 24	Sep 11 02:13:23 AM UTC 24	13039363 ps
T562	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1339289976	Sep 11 02:13:21 AM UTC 24	Sep 11 02:13:23 AM UTC 24	23280752 ps
T563	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.902338411	Sep 11 02:13:21 AM UTC 24	Sep 11 02:13:23 AM UTC 24	18582225 ps
T564	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1724548177	Sep 11 02:13:22 AM UTC 24	Sep 11 02:13:24 AM UTC 24	47608487 ps
T565	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2443095000	Sep 11 02:13:22 AM UTC 24	Sep 11 02:13:24 AM UTC 24	14196603 ps
T566	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3514993176	Sep 11 02:13:22 AM UTC 24	Sep 11 02:13:24 AM UTC 24	15487303 ps
T567	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3443148636	Sep 11 02:13:23 AM UTC 24	Sep 11 02:13:24 AM UTC 24	13984567 ps
T568	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.2476311658	Sep 11 02:13:24 AM UTC 24	Sep 11 02:13:26 AM UTC 24	35718879 ps
T569	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.365274374	Sep 11 02:13:24 AM UTC 24	Sep 11 02:13:26 AM UTC 24	14342891 ps
T570	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.3779040703	Sep 11 02:13:24 AM UTC 24	Sep 11 02:13:26 AM UTC 24	14844327 ps
T571	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3493949546	Sep 11 02:13:24 AM UTC 24	Sep 11 02:13:26 AM UTC 24	45402328 ps
T572	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.1010292882	Sep 11 02:13:25 AM UTC 24	Sep 11 02:13:27 AM UTC 24	64259573 ps
T573	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2370358858	Sep 11 02:13:25 AM UTC 24	Sep 11 02:13:27 AM UTC 24	15995818 ps
T574	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3494999341	Sep 11 02:13:26 AM UTC 24	Sep 11 02:13:28 AM UTC 24	11836068 ps
T575	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2965522687	Sep 11 02:13:26 AM UTC 24	Sep 11 02:13:28 AM UTC 24	51584675 ps
T576	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3724346309	Sep 11 02:13:26 AM UTC 24	Sep 11 02:13:28 AM UTC 24	37127248 ps
T577	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3556298506	Sep 11 02:13:26 AM UTC 24	Sep 11 02:13:28 AM UTC 24	26048359 ps
T578	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3662050645	Sep 11 02:13:28 AM UTC 24	Sep 11 02:13:30 AM UTC 24	11913751 ps
T579	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1300137747	Sep 11 02:13:28 AM UTC 24	Sep 11 02:13:30 AM UTC 24	22620725 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.3157385408
Short name	T8
Test name
Test status
Simulation time	746996173 ps
CPU time	1.07 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:28:19 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157385408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3157385408
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all_with_rand_reset.2013257889
Short name	T12
Test name
Test status
Simulation time	5189919670 ps
CPU time	17.66 seconds
Started	Sep 11 01:28:21 AM UTC 24
Finished	Sep 11 01:28:40 AM UTC 24
Peak memory	203936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2013257889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.rv_timer_stress_all_with_rand_reset.2013257889
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1901407885
Short name	T20
Test name
Test status
Simulation time	437529782 ps
CPU time	2.1 seconds
Started	Sep 11 02:11:48 AM UTC 24
Finished	Sep 11 02:11:51 AM UTC 24
Peak memory	200888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901407885 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1901407885
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.3224592558
Short name	T87
Test name
Test status
Simulation time	354426734343 ps
CPU time	425.86 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:35:28 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224592558 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3224592558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.2136682644
Short name	T203
Test name
Test status
Simulation time	604187362395 ps
CPU time	1321.04 seconds
Started	Sep 11 01:36:17 AM UTC 24
Finished	Sep 11 01:58:34 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136682644 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.2136682644
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.3213910040
Short name	T57
Test name
Test status
Simulation time	2067696541975 ps
CPU time	921.11 seconds
Started	Sep 11 01:28:20 AM UTC 24
Finished	Sep 11 01:43:51 AM UTC 24
Peak memory	202464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213910040 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.3213910040
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.2603253583
Short name	T6
Test name
Test status
Simulation time	212559506 ps
CPU time	0.86 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 01:28:18 AM UTC 24
Peak memory	230920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603253583 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2603253583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.549547680
Short name	T216
Test name
Test status
Simulation time	1563785923149 ps
CPU time	1156.03 seconds
Started	Sep 11 01:29:40 AM UTC 24
Finished	Sep 11 01:49:09 AM UTC 24
Peak memory	202556 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549547680 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.549547680
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.1288967812
Short name	T55
Test name
Test status
Simulation time	1870189957863 ps
CPU time	810.79 seconds
Started	Sep 11 01:28:06 AM UTC 24
Finished	Sep 11 01:41:46 AM UTC 24
Peak memory	202516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288967812 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.1288967812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.1400858425
Short name	T285
Test name
Test status
Simulation time	1090406274463 ps
CPU time	1752.08 seconds
Started	Sep 11 01:46:59 AM UTC 24
Finished	Sep 11 02:16:32 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400858425 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.1400858425
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.1207721693
Short name	T346
Test name
Test status
Simulation time	481798310103 ps
CPU time	3715.46 seconds
Started	Sep 11 01:31:40 AM UTC 24
Finished	Sep 11 02:34:16 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207721693 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.1207721693
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.3361210766
Short name	T16
Test name
Test status
Simulation time	71716498234 ps
CPU time	59.63 seconds
Started	Sep 11 01:28:55 AM UTC 24
Finished	Sep 11 01:29:56 AM UTC 24
Peak memory	199840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361210766 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3361210766
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2313472689
Short name	T100
Test name
Test status
Simulation time	265533781238 ps
CPU time	374.26 seconds
Started	Sep 11 01:34:51 AM UTC 24
Finished	Sep 11 01:41:10 AM UTC 24
Peak memory	199740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313472689 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2313472689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1711148626
Short name	T24
Test name
Test status
Simulation time	43696474 ps
CPU time	0.84 seconds
Started	Sep 11 02:11:52 AM UTC 24
Finished	Sep 11 02:11:54 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711148626 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1711148626
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2535069889
Short name	T147
Test name
Test status
Simulation time	939409668023 ps
CPU time	2172.38 seconds
Started	Sep 11 01:37:11 AM UTC 24
Finished	Sep 11 02:13:45 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535069889 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2535069889
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.3936512977
Short name	T353
Test name
Test status
Simulation time	1132624799514 ps
CPU time	5038.25 seconds
Started	Sep 11 01:49:36 AM UTC 24
Finished	Sep 11 03:14:28 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936512977 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.3936512977
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3892552425
Short name	T215
Test name
Test status
Simulation time	3307211583280 ps
CPU time	1742.22 seconds
Started	Sep 11 01:48:47 AM UTC 24
Finished	Sep 11 02:18:08 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892552425 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3892552425
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.3832765648
Short name	T196
Test name
Test status
Simulation time	5337556578543 ps
CPU time	3688.57 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 02:30:27 AM UTC 24
Peak memory	202244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832765648 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.3832765648
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.2504095146
Short name	T324
Test name
Test status
Simulation time	299661941088 ps
CPU time	546.51 seconds
Started	Sep 11 01:39:36 AM UTC 24
Finished	Sep 11 01:48:48 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504095146 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.2504095146
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/31.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.4217173915
Short name	T58
Test name
Test status
Simulation time	1008067404296 ps
CPU time	666.77 seconds
Started	Sep 11 01:33:29 AM UTC 24
Finished	Sep 11 01:44:44 AM UTC 24
Peak memory	199804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217173915 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.4217173915
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.250800209
Short name	T209
Test name
Test status
Simulation time	952439620603 ps
CPU time	2589.12 seconds
Started	Sep 11 01:34:22 AM UTC 24
Finished	Sep 11 02:17:59 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250800209 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.250800209
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3154110211
Short name	T175
Test name
Test status
Simulation time	2755352601148 ps
CPU time	1706.38 seconds
Started	Sep 11 01:29:10 AM UTC 24
Finished	Sep 11 01:57:55 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154110211 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.3154110211
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.2803158708
Short name	T253
Test name
Test status
Simulation time	154784419832 ps
CPU time	589.01 seconds
Started	Sep 11 01:39:40 AM UTC 24
Finished	Sep 11 01:49:35 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803158708 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2803158708
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.1926568632
Short name	T192
Test name
Test status
Simulation time	1097958101338 ps
CPU time	916.16 seconds
Started	Sep 11 01:32:36 AM UTC 24
Finished	Sep 11 01:48:02 AM UTC 24
Peak memory	199912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926568632 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.1926568632
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.2923833056
Short name	T312
Test name
Test status
Simulation time	725784628315 ps
CPU time	2922.44 seconds
Started	Sep 11 01:28:52 AM UTC 24
Finished	Sep 11 02:18:05 AM UTC 24
Peak memory	202648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923833056 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.2923833056
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2779450424
Short name	T94
Test name
Test status
Simulation time	165168595932 ps
CPU time	423.87 seconds
Started	Sep 11 01:28:26 AM UTC 24
Finished	Sep 11 01:35:35 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779450424 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2779450424
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.3563407404
Short name	T259
Test name
Test status
Simulation time	503456277567 ps
CPU time	469.98 seconds
Started	Sep 11 02:06:41 AM UTC 24
Finished	Sep 11 02:14:37 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563407404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3563407404
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/156.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.1517742946
Short name	T111
Test name
Test status
Simulation time	834500358157 ps
CPU time	586.86 seconds
Started	Sep 11 01:28:01 AM UTC 24
Finished	Sep 11 01:37:55 AM UTC 24
Peak memory	202548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517742946 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1517742946
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2174658619
Short name	T152
Test name
Test status
Simulation time	951223747291 ps
CPU time	1384.88 seconds
Started	Sep 11 01:42:24 AM UTC 24
Finished	Sep 11 02:05:44 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174658619 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.2174658619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.4199766987
Short name	T260
Test name
Test status
Simulation time	165756036899 ps
CPU time	1118.54 seconds
Started	Sep 11 02:04:00 AM UTC 24
Finished	Sep 11 02:22:51 AM UTC 24
Peak memory	202484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199766987 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4199766987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/141.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.3280514249
Short name	T90
Test name
Test status
Simulation time	227563612562 ps
CPU time	361.03 seconds
Started	Sep 11 01:29:49 AM UTC 24
Finished	Sep 11 01:35:54 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280514249 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3280514249
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.1415872361
Short name	T226
Test name
Test status
Simulation time	856786147552 ps
CPU time	532.87 seconds
Started	Sep 11 01:57:40 AM UTC 24
Finished	Sep 11 02:06:39 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415872361 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1415872361
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/99.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.303242423
Short name	T295
Test name
Test status
Simulation time	107807952709 ps
CPU time	358.21 seconds
Started	Sep 11 02:05:44 AM UTC 24
Finished	Sep 11 02:11:47 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303242423 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.303242423
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/150.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.1746970463
Short name	T170
Test name
Test status
Simulation time	3199670467790 ps
CPU time	1808.93 seconds
Started	Sep 11 01:35:32 AM UTC 24
Finished	Sep 11 02:06:02 AM UTC 24
Peak memory	202424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746970463 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.1746970463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.1208688353
Short name	T47
Test name
Test status
Simulation time	415927845973 ps
CPU time	205.69 seconds
Started	Sep 11 01:28:20 AM UTC 24
Finished	Sep 11 01:31:49 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208688353 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1208688353
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.426335689
Short name	T449
Test name
Test status
Simulation time	610450445677 ps
CPU time	1926.96 seconds
Started	Sep 11 01:57:51 AM UTC 24
Finished	Sep 11 02:30:20 AM UTC 24
Peak memory	202348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426335689 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.426335689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/101.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.2190280711
Short name	T234
Test name
Test status
Simulation time	663443164057 ps
CPU time	258.95 seconds
Started	Sep 11 02:04:43 AM UTC 24
Finished	Sep 11 02:09:06 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190280711 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2190280711
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/144.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1410273603
Short name	T182
Test name
Test status
Simulation time	391747881444 ps
CPU time	314.64 seconds
Started	Sep 11 02:04:46 AM UTC 24
Finished	Sep 11 02:10:05 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410273603 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1410273603
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/145.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.4184992457
Short name	T173
Test name
Test status
Simulation time	211226764270 ps
CPU time	653.74 seconds
Started	Sep 11 02:10:44 AM UTC 24
Finished	Sep 11 02:21:46 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184992457 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4184992457
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/194.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.3324786545
Short name	T191
Test name
Test status
Simulation time	4319030381177 ps
CPU time	875.86 seconds
Started	Sep 11 01:42:58 AM UTC 24
Finished	Sep 11 01:57:44 AM UTC 24
Peak memory	199804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324786545 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.3324786545
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2261627179
Short name	T97
Test name
Test status
Simulation time	149793318428 ps
CPU time	255.7 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:32:36 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261627179 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2261627179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.2545838449
Short name	T177
Test name
Test status
Simulation time	172553576564 ps
CPU time	1453.7 seconds
Started	Sep 11 01:28:31 AM UTC 24
Finished	Sep 11 01:53:01 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545838449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.2545838449
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.3877447391
Short name	T248
Test name
Test status
Simulation time	189586089714 ps
CPU time	588.51 seconds
Started	Sep 11 02:05:05 AM UTC 24
Finished	Sep 11 02:15:01 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877447391 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3877447391
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/147.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.3547914959
Short name	T162
Test name
Test status
Simulation time	604902999934 ps
CPU time	1194.44 seconds
Started	Sep 11 02:07:00 AM UTC 24
Finished	Sep 11 02:27:09 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547914959 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3547914959
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/160.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.572523485
Short name	T307
Test name
Test status
Simulation time	257074394208 ps
CPU time	1469.49 seconds
Started	Sep 11 02:10:39 AM UTC 24
Finished	Sep 11 02:35:25 AM UTC 24
Peak memory	202520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572523485 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.572523485
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/192.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1340367917
Short name	T195
Test name
Test status
Simulation time	1674184915637 ps
CPU time	863.71 seconds
Started	Sep 11 01:40:55 AM UTC 24
Finished	Sep 11 01:55:28 AM UTC 24
Peak memory	202520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340367917 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.1340367917
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.553749102
Short name	T185
Test name
Test status
Simulation time	142848440665 ps
CPU time	537.58 seconds
Started	Sep 11 01:43:12 AM UTC 24
Finished	Sep 11 01:52:16 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553749102 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.553749102
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.3067929945
Short name	T224
Test name
Test status
Simulation time	905655629018 ps
CPU time	1181.54 seconds
Started	Sep 11 01:44:26 AM UTC 24
Finished	Sep 11 02:04:21 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067929945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3067929945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.1854513551
Short name	T161
Test name
Test status
Simulation time	146343079679 ps
CPU time	675.58 seconds
Started	Sep 11 01:54:11 AM UTC 24
Finished	Sep 11 02:05:35 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854513551 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1854513551
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/69.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.1350092152
Short name	T263
Test name
Test status
Simulation time	89523668679 ps
CPU time	166.74 seconds
Started	Sep 11 01:55:48 AM UTC 24
Finished	Sep 11 01:58:38 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350092152 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1350092152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/81.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.2169611359
Short name	T213
Test name
Test status
Simulation time	228209357849 ps
CPU time	303.03 seconds
Started	Sep 11 01:58:35 AM UTC 24
Finished	Sep 11 02:03:43 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169611359 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2169611359
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/104.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.1707345382
Short name	T368
Test name
Test status
Simulation time	962941698030 ps
CPU time	1203.35 seconds
Started	Sep 11 02:02:33 AM UTC 24
Finished	Sep 11 02:22:51 AM UTC 24
Peak memory	202548 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707345382 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1707345382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/127.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.822060295
Short name	T240
Test name
Test status
Simulation time	23103707817 ps
CPU time	77.88 seconds
Started	Sep 11 02:07:42 AM UTC 24
Finished	Sep 11 02:09:01 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822060295 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.822060295
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/165.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.1951789013
Short name	T445
Test name
Test status
Simulation time	125603880034 ps
CPU time	595.76 seconds
Started	Sep 11 02:09:03 AM UTC 24
Finished	Sep 11 02:19:06 AM UTC 24
Peak memory	199900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951789013 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1951789013
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/176.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.1961455892
Short name	T189
Test name
Test status
Simulation time	77048071642 ps
CPU time	401.61 seconds
Started	Sep 11 02:10:20 AM UTC 24
Finished	Sep 11 02:17:07 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961455892 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1961455892
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/188.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.288340445
Short name	T168
Test name
Test status
Simulation time	559131783094 ps
CPU time	569.63 seconds
Started	Sep 11 01:35:01 AM UTC 24
Finished	Sep 11 01:44:37 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288340445 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.288340445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.2114475429
Short name	T148
Test name
Test status
Simulation time	249672895702 ps
CPU time	417.24 seconds
Started	Sep 11 01:38:59 AM UTC 24
Finished	Sep 11 01:46:01 AM UTC 24
Peak memory	199808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114475429 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2114475429
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.233636131
Short name	T154
Test name
Test status
Simulation time	1115854108679 ps
CPU time	839.59 seconds
Started	Sep 11 01:41:55 AM UTC 24
Finished	Sep 11 01:56:05 AM UTC 24
Peak memory	199804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233636131 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.233636131
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.4164836277
Short name	T144
Test name
Test status
Simulation time	156460829970 ps
CPU time	264.29 seconds
Started	Sep 11 01:44:19 AM UTC 24
Finished	Sep 11 01:48:47 AM UTC 24
Peak memory	199740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164836277 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.4164836277
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1609557879
Short name	T62
Test name
Test status
Simulation time	89877457 ps
CPU time	4.5 seconds
Started	Sep 11 02:11:55 AM UTC 24
Finished	Sep 11 02:12:01 AM UTC 24
Peak memory	201004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609557879 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.1609557879
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1770651011
Short name	T72
Test name
Test status
Simulation time	34204366 ps
CPU time	1.13 seconds
Started	Sep 11 02:11:58 AM UTC 24
Finished	Sep 11 02:12:00 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770651011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.1770651011
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2149870703
Short name	T52
Test name
Test status
Simulation time	562198414922 ps
CPU time	261.59 seconds
Started	Sep 11 01:28:03 AM UTC 24
Finished	Sep 11 01:32:28 AM UTC 24
Peak memory	202588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149870703 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2149870703
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.4244098857
Short name	T127
Test name
Test status
Simulation time	109809550836 ps
CPU time	114.21 seconds
Started	Sep 11 01:28:41 AM UTC 24
Finished	Sep 11 01:30:38 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244098857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4244098857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.894325583
Short name	T362
Test name
Test status
Simulation time	224735822454 ps
CPU time	1862.01 seconds
Started	Sep 11 02:03:10 AM UTC 24
Finished	Sep 11 02:34:33 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894325583 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.894325583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/133.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2520677857
Short name	T193
Test name
Test status
Simulation time	127556460790 ps
CPU time	320.02 seconds
Started	Sep 11 02:05:01 AM UTC 24
Finished	Sep 11 02:10:26 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520677857 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2520677857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/146.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.3775056511
Short name	T122
Test name
Test status
Simulation time	332306559748 ps
CPU time	662.31 seconds
Started	Sep 11 01:29:57 AM UTC 24
Finished	Sep 11 01:41:07 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775056511 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3775056511
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.2798413306
Short name	T315
Test name
Test status
Simulation time	445363745352 ps
CPU time	619.5 seconds
Started	Sep 11 02:06:31 AM UTC 24
Finished	Sep 11 02:16:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798413306 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2798413306
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/154.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.1985177334
Short name	T333
Test name
Test status
Simulation time	143721309021 ps
CPU time	395.73 seconds
Started	Sep 11 02:09:34 AM UTC 24
Finished	Sep 11 02:16:15 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985177334 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1985177334
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/179.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.3037436986
Short name	T300
Test name
Test status
Simulation time	167634903857 ps
CPU time	544.44 seconds
Started	Sep 11 02:10:35 AM UTC 24
Finished	Sep 11 02:19:46 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037436986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3037436986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/191.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1611996019
Short name	T211
Test name
Test status
Simulation time	160934554515 ps
CPU time	437.6 seconds
Started	Sep 11 02:11:20 AM UTC 24
Finished	Sep 11 02:18:44 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611996019 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1611996019
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/198.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.109912118
Short name	T276
Test name
Test status
Simulation time	685787850705 ps
CPU time	692 seconds
Started	Sep 11 01:35:36 AM UTC 24
Finished	Sep 11 01:47:16 AM UTC 24
Peak memory	199740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109912118 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.109912118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.4088131262
Short name	T150
Test name
Test status
Simulation time	1194710710468 ps
CPU time	847.27 seconds
Started	Sep 11 01:36:04 AM UTC 24
Finished	Sep 11 01:50:21 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088131262 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.4088131262
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3901953978
Short name	T288
Test name
Test status
Simulation time	537205050371 ps
CPU time	602.92 seconds
Started	Sep 11 01:46:59 AM UTC 24
Finished	Sep 11 01:57:09 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901953978 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3901953978
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.706941185
Short name	T271
Test name
Test status
Simulation time	155343800118 ps
CPU time	210.02 seconds
Started	Sep 11 01:56:08 AM UTC 24
Finished	Sep 11 01:59:41 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706941185 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.706941185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/85.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.1409592328
Short name	T49
Test name
Test status
Simulation time	121016273303 ps
CPU time	223.08 seconds
Started	Sep 11 01:28:21 AM UTC 24
Finished	Sep 11 01:32:08 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409592328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1409592328
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.2410593356
Short name	T134
Test name
Test status
Simulation time	441415478973 ps
CPU time	491.28 seconds
Started	Sep 11 01:28:00 AM UTC 24
Finished	Sep 11 01:36:17 AM UTC 24
Peak memory	202332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410593356 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2410593356
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1811826208
Short name	T332
Test name
Test status
Simulation time	353553615746 ps
CPU time	198.18 seconds
Started	Sep 11 01:58:39 AM UTC 24
Finished	Sep 11 02:02:00 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811826208 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1811826208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/105.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.211839706
Short name	T290
Test name
Test status
Simulation time	3093097699295 ps
CPU time	1393.29 seconds
Started	Sep 11 01:28:28 AM UTC 24
Finished	Sep 11 01:51:57 AM UTC 24
Peak memory	202400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211839706 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.211839706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1996470268
Short name	T34
Test name
Test status
Simulation time	36563270060 ps
CPU time	58.5 seconds
Started	Sep 11 01:28:29 AM UTC 24
Finished	Sep 11 01:29:29 AM UTC 24
Peak memory	199612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996470268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1996470268
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.2162167052
Short name	T297
Test name
Test status
Simulation time	372207415440 ps
CPU time	999.8 seconds
Started	Sep 11 01:59:42 AM UTC 24
Finished	Sep 11 02:16:34 AM UTC 24
Peak memory	202612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162167052 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2162167052
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/110.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.2992992875
Short name	T236
Test name
Test status
Simulation time	251717963101 ps
CPU time	856.09 seconds
Started	Sep 11 02:01:26 AM UTC 24
Finished	Sep 11 02:15:52 AM UTC 24
Peak memory	202520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992992875 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2992992875
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/118.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.30251218
Short name	T214
Test name
Test status
Simulation time	461549786080 ps
CPU time	346.2 seconds
Started	Sep 11 02:01:27 AM UTC 24
Finished	Sep 11 02:07:18 AM UTC 24
Peak memory	199672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30251218 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.30251218
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/119.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2903031115
Short name	T183
Test name
Test status
Simulation time	105080619481 ps
CPU time	734.24 seconds
Started	Sep 11 01:28:32 AM UTC 24
Finished	Sep 11 01:40:55 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903031115 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2903031115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.3147841582
Short name	T261
Test name
Test status
Simulation time	89020644504 ps
CPU time	136.15 seconds
Started	Sep 11 02:02:09 AM UTC 24
Finished	Sep 11 02:04:27 AM UTC 24
Peak memory	199900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147841582 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3147841582
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/123.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.4089108076
Short name	T328
Test name
Test status
Simulation time	47627939713 ps
CPU time	41.19 seconds
Started	Sep 11 02:02:26 AM UTC 24
Finished	Sep 11 02:03:09 AM UTC 24
Peak memory	199900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089108076 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4089108076
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/125.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.3151859471
Short name	T268
Test name
Test status
Simulation time	491608165255 ps
CPU time	2263.02 seconds
Started	Sep 11 02:03:04 AM UTC 24
Finished	Sep 11 02:41:14 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151859471 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3151859471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/132.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.3707184923
Short name	T128
Test name
Test status
Simulation time	162858838457 ps
CPU time	501.12 seconds
Started	Sep 11 01:29:17 AM UTC 24
Finished	Sep 11 01:37:44 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707184923 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3707184923
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2780206790
Short name	T252
Test name
Test status
Simulation time	520572867094 ps
CPU time	477.91 seconds
Started	Sep 11 01:29:31 AM UTC 24
Finished	Sep 11 01:37:35 AM UTC 24
Peak memory	199608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780206790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2780206790
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.3057215767
Short name	T199
Test name
Test status
Simulation time	303389450507 ps
CPU time	365.22 seconds
Started	Sep 11 02:04:00 AM UTC 24
Finished	Sep 11 02:10:10 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057215767 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3057215767
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/140.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3802445888
Short name	T294
Test name
Test status
Simulation time	2997177226452 ps
CPU time	1630.77 seconds
Started	Sep 11 01:31:34 AM UTC 24
Finished	Sep 11 01:59:03 AM UTC 24
Peak memory	202332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802445888 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3802445888
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1696678455
Short name	T369
Test name
Test status
Simulation time	320952846617 ps
CPU time	191.19 seconds
Started	Sep 11 02:09:58 AM UTC 24
Finished	Sep 11 02:13:12 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696678455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1696678455
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/183.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.713618612
Short name	T237
Test name
Test status
Simulation time	530760379017 ps
CPU time	636.42 seconds
Started	Sep 11 02:11:12 AM UTC 24
Finished	Sep 11 02:21:57 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713618612 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.713618612
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/195.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.488303968
Short name	T167
Test name
Test status
Simulation time	63881950113 ps
CPU time	845.32 seconds
Started	Sep 11 01:28:15 AM UTC 24
Finished	Sep 11 01:42:31 AM UTC 24
Peak memory	202484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488303968 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.488303968
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.866308661
Short name	T323
Test name
Test status
Simulation time	354669902653 ps
CPU time	603.29 seconds
Started	Sep 11 01:43:27 AM UTC 24
Finished	Sep 11 01:53:37 AM UTC 24
Peak memory	199576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866308661 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.866308661
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.2188467824
Short name	T155
Test name
Test status
Simulation time	304603813625 ps
CPU time	170.94 seconds
Started	Sep 11 01:57:38 AM UTC 24
Finished	Sep 11 02:00:31 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188467824 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2188467824
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/98.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3784328351
Short name	T38
Test name
Test status
Simulation time	117189385 ps
CPU time	0.97 seconds
Started	Sep 11 02:11:55 AM UTC 24
Finished	Sep 11 02:11:57 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784328351 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.3784328351
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4290116152
Short name	T453
Test name
Test status
Simulation time	14084371 ps
CPU time	0.98 seconds
Started	Sep 11 02:11:59 AM UTC 24
Finished	Sep 11 02:12:01 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4290116152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.4290116152
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.3649494539
Short name	T25
Test name
Test status
Simulation time	43385104 ps
CPU time	0.88 seconds
Started	Sep 11 02:11:52 AM UTC 24
Finished	Sep 11 02:11:54 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649494539 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3649494539
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.1019941216
Short name	T452
Test name
Test status
Simulation time	12545477 ps
CPU time	0.86 seconds
Started	Sep 11 02:11:49 AM UTC 24
Finished	Sep 11 02:11:51 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019941216 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1019941216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.682936706
Short name	T451
Test name
Test status
Simulation time	950679286 ps
CPU time	2.52 seconds
Started	Sep 11 02:11:45 AM UTC 24
Finished	Sep 11 02:11:48 AM UTC 24
Peak memory	200876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682936706 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.682936706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1661341167
Short name	T63
Test name
Test status
Simulation time	35198171 ps
CPU time	0.93 seconds
Started	Sep 11 02:12:07 AM UTC 24
Finished	Sep 11 02:12:09 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661341167 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.1661341167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2490280691
Short name	T39
Test name
Test status
Simulation time	1181103561 ps
CPU time	3.83 seconds
Started	Sep 11 02:12:06 AM UTC 24
Finished	Sep 11 02:12:10 AM UTC 24
Peak memory	200740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490280691 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.2490280691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1806498242
Short name	T455
Test name
Test status
Simulation time	90582322 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:05 AM UTC 24
Finished	Sep 11 02:12:06 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806498242 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.1806498242
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3649421650
Short name	T40
Test name
Test status
Simulation time	26126943 ps
CPU time	0.94 seconds
Started	Sep 11 02:12:10 AM UTC 24
Finished	Sep 11 02:12:12 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3649421650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.3649421650
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1111681210
Short name	T80
Test name
Test status
Simulation time	22563034 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:05 AM UTC 24
Finished	Sep 11 02:12:06 AM UTC 24
Peak memory	198848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111681210 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1111681210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1613579399
Short name	T454
Test name
Test status
Simulation time	17071047 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:02 AM UTC 24
Finished	Sep 11 02:12:04 AM UTC 24
Peak memory	198904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613579399 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1613579399
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2799691037
Short name	T54
Test name
Test status
Simulation time	36037466 ps
CPU time	0.94 seconds
Started	Sep 11 02:12:07 AM UTC 24
Finished	Sep 11 02:12:09 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799691037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.2799691037
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.4232701496
Short name	T53
Test name
Test status
Simulation time	84397749 ps
CPU time	1.55 seconds
Started	Sep 11 02:12:01 AM UTC 24
Finished	Sep 11 02:12:04 AM UTC 24
Peak memory	199100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232701496 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4232701496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1993539022
Short name	T21
Test name
Test status
Simulation time	101124255 ps
CPU time	1.66 seconds
Started	Sep 11 02:12:01 AM UTC 24
Finished	Sep 11 02:12:04 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993539022 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1993539022
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1698603324
Short name	T497
Test name
Test status
Simulation time	50013094 ps
CPU time	0.95 seconds
Started	Sep 11 02:12:53 AM UTC 24
Finished	Sep 11 02:12:55 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1698603324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.1698603324
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.374076341
Short name	T495
Test name
Test status
Simulation time	30246525 ps
CPU time	0.79 seconds
Started	Sep 11 02:12:52 AM UTC 24
Finished	Sep 11 02:12:54 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374076341 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.374076341
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.3188596691
Short name	T492
Test name
Test status
Simulation time	36500593 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:51 AM UTC 24
Finished	Sep 11 02:12:53 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188596691 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3188596691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.66560560
Short name	T496
Test name
Test status
Simulation time	17150524 ps
CPU time	1.05 seconds
Started	Sep 11 02:12:52 AM UTC 24
Finished	Sep 11 02:12:54 AM UTC 24
Peak memory	199104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66560560 -assert nopostproc + UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.66560560
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1598504980
Short name	T494
Test name
Test status
Simulation time	384132729 ps
CPU time	1.74 seconds
Started	Sep 11 02:12:51 AM UTC 24
Finished	Sep 11 02:12:53 AM UTC 24
Peak memory	199096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598504980 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1598504980
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.208476201
Short name	T493
Test name
Test status
Simulation time	73984134 ps
CPU time	1.61 seconds
Started	Sep 11 02:12:51 AM UTC 24
Finished	Sep 11 02:12:53 AM UTC 24
Peak memory	198852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208476201 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.208476201
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.794904894
Short name	T503
Test name
Test status
Simulation time	18861127 ps
CPU time	1.33 seconds
Started	Sep 11 02:12:55 AM UTC 24
Finished	Sep 11 02:12:58 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=794904894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_cs r_mem_rw_with_rand_reset.794904894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.2847622244
Short name	T500
Test name
Test status
Simulation time	18802486 ps
CPU time	0.88 seconds
Started	Sep 11 02:12:54 AM UTC 24
Finished	Sep 11 02:12:56 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847622244 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2847622244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.1146623903
Short name	T498
Test name
Test status
Simulation time	13353964 ps
CPU time	0.83 seconds
Started	Sep 11 02:12:54 AM UTC 24
Finished	Sep 11 02:12:56 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146623903 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1146623903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3964474958
Short name	T499
Test name
Test status
Simulation time	21321983 ps
CPU time	0.79 seconds
Started	Sep 11 02:12:54 AM UTC 24
Finished	Sep 11 02:12:56 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964474958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.3964474958
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1828269830
Short name	T501
Test name
Test status
Simulation time	79453214 ps
CPU time	2.43 seconds
Started	Sep 11 02:12:53 AM UTC 24
Finished	Sep 11 02:12:57 AM UTC 24
Peak memory	202792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828269830 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1828269830
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1031044906
Short name	T502
Test name
Test status
Simulation time	443440441 ps
CPU time	1.67 seconds
Started	Sep 11 02:12:54 AM UTC 24
Finished	Sep 11 02:12:57 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031044906 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.1031044906
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2231761610
Short name	T508
Test name
Test status
Simulation time	467701082 ps
CPU time	1.22 seconds
Started	Sep 11 02:12:58 AM UTC 24
Finished	Sep 11 02:13:00 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2231761610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.2231761610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.617251523
Short name	T70
Test name
Test status
Simulation time	23738794 ps
CPU time	0.85 seconds
Started	Sep 11 02:12:58 AM UTC 24
Finished	Sep 11 02:13:00 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617251523 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.617251523
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.507174274
Short name	T504
Test name
Test status
Simulation time	13780240 ps
CPU time	0.83 seconds
Started	Sep 11 02:12:57 AM UTC 24
Finished	Sep 11 02:12:59 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507174274 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.507174274
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1890479505
Short name	T507
Test name
Test status
Simulation time	500898523 ps
CPU time	1.08 seconds
Started	Sep 11 02:12:58 AM UTC 24
Finished	Sep 11 02:13:00 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890479505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.1890479505
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.2682408091
Short name	T505
Test name
Test status
Simulation time	63075322 ps
CPU time	2.07 seconds
Started	Sep 11 02:12:55 AM UTC 24
Finished	Sep 11 02:12:59 AM UTC 24
Peak memory	200672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682408091 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2682408091
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3544856630
Short name	T506
Test name
Test status
Simulation time	117155780 ps
CPU time	2.12 seconds
Started	Sep 11 02:12:57 AM UTC 24
Finished	Sep 11 02:13:00 AM UTC 24
Peak memory	200824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544856630 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.3544856630
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2577725528
Short name	T511
Test name
Test status
Simulation time	17457818 ps
CPU time	0.92 seconds
Started	Sep 11 02:13:01 AM UTC 24
Finished	Sep 11 02:13:03 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2577725528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2577725528
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1841638936
Short name	T71
Test name
Test status
Simulation time	12884666 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:00 AM UTC 24
Finished	Sep 11 02:13:02 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841638936 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1841638936
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.803866259
Short name	T510
Test name
Test status
Simulation time	54502159 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:00 AM UTC 24
Finished	Sep 11 02:13:02 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803866259 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.803866259
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2328962792
Short name	T512
Test name
Test status
Simulation time	156669569 ps
CPU time	1.16 seconds
Started	Sep 11 02:13:01 AM UTC 24
Finished	Sep 11 02:13:04 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328962792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.2328962792
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1846441872
Short name	T515
Test name
Test status
Simulation time	219602039 ps
CPU time	4.14 seconds
Started	Sep 11 02:12:59 AM UTC 24
Finished	Sep 11 02:13:04 AM UTC 24
Peak memory	202720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846441872 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1846441872
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1043572783
Short name	T509
Test name
Test status
Simulation time	147834181 ps
CPU time	1.59 seconds
Started	Sep 11 02:12:59 AM UTC 24
Finished	Sep 11 02:13:02 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043572783 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.1043572783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3441003293
Short name	T520
Test name
Test status
Simulation time	23829548 ps
CPU time	1.45 seconds
Started	Sep 11 02:13:05 AM UTC 24
Finished	Sep 11 02:13:07 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3441003293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.3441003293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3494503692
Short name	T517
Test name
Test status
Simulation time	21825223 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:04 AM UTC 24
Finished	Sep 11 02:13:05 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494503692 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3494503692
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1304732521
Short name	T518
Test name
Test status
Simulation time	24637777 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:04 AM UTC 24
Finished	Sep 11 02:13:05 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304732521 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1304732521
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3219630434
Short name	T519
Test name
Test status
Simulation time	33703836 ps
CPU time	1.1 seconds
Started	Sep 11 02:13:05 AM UTC 24
Finished	Sep 11 02:13:07 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219630434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3219630434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2340158697
Short name	T514
Test name
Test status
Simulation time	27031196 ps
CPU time	1.69 seconds
Started	Sep 11 02:13:01 AM UTC 24
Finished	Sep 11 02:13:04 AM UTC 24
Peak memory	199096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340158697 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2340158697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3226335104
Short name	T516
Test name
Test status
Simulation time	599871510 ps
CPU time	1.17 seconds
Started	Sep 11 02:13:03 AM UTC 24
Finished	Sep 11 02:13:05 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226335104 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.3226335104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1633071839
Short name	T526
Test name
Test status
Simulation time	53154383 ps
CPU time	1.12 seconds
Started	Sep 11 02:13:07 AM UTC 24
Finished	Sep 11 02:13:09 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1633071839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1633071839
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3686638009
Short name	T523
Test name
Test status
Simulation time	24880764 ps
CPU time	0.81 seconds
Started	Sep 11 02:13:06 AM UTC 24
Finished	Sep 11 02:13:08 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686638009 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3686638009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.629939312
Short name	T522
Test name
Test status
Simulation time	70699502 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:06 AM UTC 24
Finished	Sep 11 02:13:08 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629939312 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.629939312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3883264030
Short name	T525
Test name
Test status
Simulation time	31817202 ps
CPU time	0.94 seconds
Started	Sep 11 02:13:06 AM UTC 24
Finished	Sep 11 02:13:08 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883264030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.3883264030
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3188593436
Short name	T524
Test name
Test status
Simulation time	31081087 ps
CPU time	2.14 seconds
Started	Sep 11 02:13:05 AM UTC 24
Finished	Sep 11 02:13:08 AM UTC 24
Peak memory	202720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188593436 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3188593436
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3772645764
Short name	T521
Test name
Test status
Simulation time	163110856 ps
CPU time	1.53 seconds
Started	Sep 11 02:13:05 AM UTC 24
Finished	Sep 11 02:13:08 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772645764 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3772645764
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.156418363
Short name	T531
Test name
Test status
Simulation time	45572264 ps
CPU time	1.13 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=156418363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.156418363
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1775149493
Short name	T528
Test name
Test status
Simulation time	85056339 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	199048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775149493 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1775149493
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.600828785
Short name	T527
Test name
Test status
Simulation time	17439223 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600828785 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.600828785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1920250190
Short name	T530
Test name
Test status
Simulation time	96731938 ps
CPU time	1.08 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920250190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.1920250190
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1345037398
Short name	T532
Test name
Test status
Simulation time	32931955 ps
CPU time	1.49 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345037398 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1345037398
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2960184469
Short name	T529
Test name
Test status
Simulation time	50021192 ps
CPU time	1.24 seconds
Started	Sep 11 02:13:09 AM UTC 24
Finished	Sep 11 02:13:11 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960184469 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.2960184469
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.982201807
Short name	T538
Test name
Test status
Simulation time	153364075 ps
CPU time	1.11 seconds
Started	Sep 11 02:13:12 AM UTC 24
Finished	Sep 11 02:13:14 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=982201807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_cs r_mem_rw_with_rand_reset.982201807
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.3994885557
Short name	T537
Test name
Test status
Simulation time	14198198 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:12 AM UTC 24
Finished	Sep 11 02:13:14 AM UTC 24
Peak memory	199040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994885557 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3994885557
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3433192009
Short name	T535
Test name
Test status
Simulation time	128920822 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:11 AM UTC 24
Finished	Sep 11 02:13:13 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433192009 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3433192009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3198773012
Short name	T539
Test name
Test status
Simulation time	82090830 ps
CPU time	1.25 seconds
Started	Sep 11 02:13:12 AM UTC 24
Finished	Sep 11 02:13:15 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198773012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.3198773012
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3536011283
Short name	T534
Test name
Test status
Simulation time	528988141 ps
CPU time	1.65 seconds
Started	Sep 11 02:13:10 AM UTC 24
Finished	Sep 11 02:13:13 AM UTC 24
Peak memory	199096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536011283 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3536011283
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3287125126
Short name	T536
Test name
Test status
Simulation time	318029696 ps
CPU time	1.67 seconds
Started	Sep 11 02:13:11 AM UTC 24
Finished	Sep 11 02:13:14 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287125126 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.3287125126
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1987124937
Short name	T545
Test name
Test status
Simulation time	59627886 ps
CPU time	1.18 seconds
Started	Sep 11 02:13:15 AM UTC 24
Finished	Sep 11 02:13:17 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1987124937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1987124937
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1581535950
Short name	T541
Test name
Test status
Simulation time	74478504 ps
CPU time	0.86 seconds
Started	Sep 11 02:13:14 AM UTC 24
Finished	Sep 11 02:13:16 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581535950 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1581535950
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3299424270
Short name	T540
Test name
Test status
Simulation time	32384582 ps
CPU time	0.81 seconds
Started	Sep 11 02:13:14 AM UTC 24
Finished	Sep 11 02:13:15 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299424270 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3299424270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4028286462
Short name	T544
Test name
Test status
Simulation time	31478240 ps
CPU time	0.94 seconds
Started	Sep 11 02:13:15 AM UTC 24
Finished	Sep 11 02:13:17 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028286462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.4028286462
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1318888698
Short name	T542
Test name
Test status
Simulation time	184962609 ps
CPU time	3.14 seconds
Started	Sep 11 02:13:12 AM UTC 24
Finished	Sep 11 02:13:17 AM UTC 24
Peak memory	200672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318888698 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1318888698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3010218851
Short name	T543
Test name
Test status
Simulation time	100375582 ps
CPU time	2.09 seconds
Started	Sep 11 02:13:14 AM UTC 24
Finished	Sep 11 02:13:17 AM UTC 24
Peak memory	200692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010218851 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.3010218851
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.953102680
Short name	T552
Test name
Test status
Simulation time	54129441 ps
CPU time	1.74 seconds
Started	Sep 11 02:13:17 AM UTC 24
Finished	Sep 11 02:13:20 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=953102680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_cs r_mem_rw_with_rand_reset.953102680
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.631556907
Short name	T547
Test name
Test status
Simulation time	51409221 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:16 AM UTC 24
Finished	Sep 11 02:13:18 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631556907 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.631556907
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3843562681
Short name	T546
Test name
Test status
Simulation time	13636997 ps
CPU time	0.8 seconds
Started	Sep 11 02:13:16 AM UTC 24
Finished	Sep 11 02:13:18 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843562681 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3843562681
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3071850889
Short name	T551
Test name
Test status
Simulation time	59948251 ps
CPU time	1.1 seconds
Started	Sep 11 02:13:17 AM UTC 24
Finished	Sep 11 02:13:19 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071850889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.3071850889
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1915894864
Short name	T556
Test name
Test status
Simulation time	330356524 ps
CPU time	3.89 seconds
Started	Sep 11 02:13:16 AM UTC 24
Finished	Sep 11 02:13:21 AM UTC 24
Peak memory	200680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915894864 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1915894864
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.882860589
Short name	T548
Test name
Test status
Simulation time	53915029 ps
CPU time	1.27 seconds
Started	Sep 11 02:13:16 AM UTC 24
Finished	Sep 11 02:13:18 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882860589 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.882860589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.30659914
Short name	T458
Test name
Test status
Simulation time	57782737 ps
CPU time	0.92 seconds
Started	Sep 11 02:12:14 AM UTC 24
Finished	Sep 11 02:12:16 AM UTC 24
Peak memory	198264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30659914 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.30659914
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3655064574
Short name	T41
Test name
Test status
Simulation time	263045551 ps
CPU time	2.32 seconds
Started	Sep 11 02:12:14 AM UTC 24
Finished	Sep 11 02:12:18 AM UTC 24
Peak memory	200880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655064574 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.3655064574
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1311852555
Short name	T81
Test name
Test status
Simulation time	45506149 ps
CPU time	0.84 seconds
Started	Sep 11 02:12:12 AM UTC 24
Finished	Sep 11 02:12:14 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311852555 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.1311852555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2535706127
Short name	T459
Test name
Test status
Simulation time	37835304 ps
CPU time	0.92 seconds
Started	Sep 11 02:12:17 AM UTC 24
Finished	Sep 11 02:12:19 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2535706127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2535706127
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1744809797
Short name	T64
Test name
Test status
Simulation time	23574877 ps
CPU time	0.91 seconds
Started	Sep 11 02:12:14 AM UTC 24
Finished	Sep 11 02:12:16 AM UTC 24
Peak memory	197720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744809797 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1744809797
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2778970024
Short name	T457
Test name
Test status
Simulation time	42980021 ps
CPU time	0.7 seconds
Started	Sep 11 02:12:12 AM UTC 24
Finished	Sep 11 02:12:14 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778970024 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2778970024
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.414056379
Short name	T42
Test name
Test status
Simulation time	40224510 ps
CPU time	1.26 seconds
Started	Sep 11 02:12:16 AM UTC 24
Finished	Sep 11 02:12:18 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414056379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.414056379
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2547980663
Short name	T456
Test name
Test status
Simulation time	43699991 ps
CPU time	2.62 seconds
Started	Sep 11 02:12:10 AM UTC 24
Finished	Sep 11 02:12:14 AM UTC 24
Peak memory	200692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547980663 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2547980663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.988629757
Short name	T22
Test name
Test status
Simulation time	250567670 ps
CPU time	1.62 seconds
Started	Sep 11 02:12:11 AM UTC 24
Finished	Sep 11 02:12:14 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988629757 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.988629757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3088230877
Short name	T549
Test name
Test status
Simulation time	11944719 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:17 AM UTC 24
Finished	Sep 11 02:13:19 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088230877 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3088230877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1935804655
Short name	T550
Test name
Test status
Simulation time	14542135 ps
CPU time	0.86 seconds
Started	Sep 11 02:13:17 AM UTC 24
Finished	Sep 11 02:13:19 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935804655 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1935804655
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2948575222
Short name	T553
Test name
Test status
Simulation time	54829557 ps
CPU time	0.86 seconds
Started	Sep 11 02:13:19 AM UTC 24
Finished	Sep 11 02:13:20 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948575222 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2948575222
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.4078709958
Short name	T554
Test name
Test status
Simulation time	54378818 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:19 AM UTC 24
Finished	Sep 11 02:13:21 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078709958 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4078709958
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3507578293
Short name	T555
Test name
Test status
Simulation time	35484370 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:19 AM UTC 24
Finished	Sep 11 02:13:21 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507578293 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3507578293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3330948958
Short name	T557
Test name
Test status
Simulation time	33381895 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:20 AM UTC 24
Finished	Sep 11 02:13:22 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330948958 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3330948958
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.618187563
Short name	T558
Test name
Test status
Simulation time	67750166 ps
CPU time	0.83 seconds
Started	Sep 11 02:13:20 AM UTC 24
Finished	Sep 11 02:13:22 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618187563 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.618187563
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1856127051
Short name	T559
Test name
Test status
Simulation time	21215794 ps
CPU time	0.8 seconds
Started	Sep 11 02:13:20 AM UTC 24
Finished	Sep 11 02:13:22 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856127051 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1856127051
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1425689310
Short name	T560
Test name
Test status
Simulation time	17390822 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:21 AM UTC 24
Finished	Sep 11 02:13:23 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425689310 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1425689310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3607509832
Short name	T561
Test name
Test status
Simulation time	13039363 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:21 AM UTC 24
Finished	Sep 11 02:13:23 AM UTC 24
Peak memory	198960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607509832 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3607509832
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4055460455
Short name	T66
Test name
Test status
Simulation time	17131909 ps
CPU time	1.13 seconds
Started	Sep 11 02:12:22 AM UTC 24
Finished	Sep 11 02:12:24 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055460455 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.4055460455
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3680738427
Short name	T462
Test name
Test status
Simulation time	455618566 ps
CPU time	2.08 seconds
Started	Sep 11 02:12:21 AM UTC 24
Finished	Sep 11 02:12:24 AM UTC 24
Peak memory	200812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680738427 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.3680738427
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3257102415
Short name	T43
Test name
Test status
Simulation time	20979070 ps
CPU time	0.81 seconds
Started	Sep 11 02:12:20 AM UTC 24
Finished	Sep 11 02:12:22 AM UTC 24
Peak memory	199036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257102415 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.3257102415
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.697256350
Short name	T463
Test name
Test status
Simulation time	34132451 ps
CPU time	1.25 seconds
Started	Sep 11 02:12:22 AM UTC 24
Finished	Sep 11 02:12:25 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=697256350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr _mem_rw_with_rand_reset.697256350
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.3572865784
Short name	T65
Test name
Test status
Simulation time	42032129 ps
CPU time	0.84 seconds
Started	Sep 11 02:12:20 AM UTC 24
Finished	Sep 11 02:12:22 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572865784 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3572865784
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.991407460
Short name	T461
Test name
Test status
Simulation time	41087531 ps
CPU time	0.81 seconds
Started	Sep 11 02:12:19 AM UTC 24
Finished	Sep 11 02:12:21 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991407460 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.991407460
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1501322442
Short name	T73
Test name
Test status
Simulation time	51018377 ps
CPU time	1.09 seconds
Started	Sep 11 02:12:22 AM UTC 24
Finished	Sep 11 02:12:24 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501322442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.1501322442
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.1766718818
Short name	T460
Test name
Test status
Simulation time	130493060 ps
CPU time	1.88 seconds
Started	Sep 11 02:12:17 AM UTC 24
Finished	Sep 11 02:12:20 AM UTC 24
Peak memory	199100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766718818 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1766718818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1519528978
Short name	T84
Test name
Test status
Simulation time	124291911 ps
CPU time	1.22 seconds
Started	Sep 11 02:12:19 AM UTC 24
Finished	Sep 11 02:12:21 AM UTC 24
Peak memory	199104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519528978 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.1519528978
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.1339289976
Short name	T562
Test name
Test status
Simulation time	23280752 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:21 AM UTC 24
Finished	Sep 11 02:13:23 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339289976 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1339289976
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.902338411
Short name	T563
Test name
Test status
Simulation time	18582225 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:21 AM UTC 24
Finished	Sep 11 02:13:23 AM UTC 24
Peak memory	198908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902338411 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.902338411
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/31.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1724548177
Short name	T564
Test name
Test status
Simulation time	47608487 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:22 AM UTC 24
Finished	Sep 11 02:13:24 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724548177 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1724548177
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.2443095000
Short name	T565
Test name
Test status
Simulation time	14196603 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:22 AM UTC 24
Finished	Sep 11 02:13:24 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443095000 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2443095000
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/33.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3514993176
Short name	T566
Test name
Test status
Simulation time	15487303 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:22 AM UTC 24
Finished	Sep 11 02:13:24 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514993176 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3514993176
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3443148636
Short name	T567
Test name
Test status
Simulation time	13984567 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:23 AM UTC 24
Finished	Sep 11 02:13:24 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443148636 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3443148636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.365274374
Short name	T569
Test name
Test status
Simulation time	14342891 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:24 AM UTC 24
Finished	Sep 11 02:13:26 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365274374 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.365274374
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.2476311658
Short name	T568
Test name
Test status
Simulation time	35718879 ps
CPU time	0.79 seconds
Started	Sep 11 02:13:24 AM UTC 24
Finished	Sep 11 02:13:26 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476311658 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2476311658
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.3779040703
Short name	T570
Test name
Test status
Simulation time	14844327 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:24 AM UTC 24
Finished	Sep 11 02:13:26 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779040703 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3779040703
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3493949546
Short name	T571
Test name
Test status
Simulation time	45402328 ps
CPU time	0.88 seconds
Started	Sep 11 02:13:24 AM UTC 24
Finished	Sep 11 02:13:26 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493949546 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3493949546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.416838072
Short name	T467
Test name
Test status
Simulation time	26516229 ps
CPU time	1.07 seconds
Started	Sep 11 02:12:29 AM UTC 24
Finished	Sep 11 02:12:31 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416838072 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.416838072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1068413701
Short name	T469
Test name
Test status
Simulation time	767370088 ps
CPU time	3.7 seconds
Started	Sep 11 02:12:29 AM UTC 24
Finished	Sep 11 02:12:34 AM UTC 24
Peak memory	200680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068413701 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1068413701
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3094490400
Short name	T67
Test name
Test status
Simulation time	28653775 ps
CPU time	0.89 seconds
Started	Sep 11 02:12:26 AM UTC 24
Finished	Sep 11 02:12:28 AM UTC 24
Peak memory	199040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094490400 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.3094490400
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2732244517
Short name	T468
Test name
Test status
Simulation time	78418640 ps
CPU time	1.11 seconds
Started	Sep 11 02:12:30 AM UTC 24
Finished	Sep 11 02:12:32 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2732244517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.2732244517
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.989266116
Short name	T466
Test name
Test status
Simulation time	14684925 ps
CPU time	0.84 seconds
Started	Sep 11 02:12:28 AM UTC 24
Finished	Sep 11 02:12:30 AM UTC 24
Peak memory	198848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989266116 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.989266116
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.3321982290
Short name	T464
Test name
Test status
Simulation time	16800281 ps
CPU time	0.85 seconds
Started	Sep 11 02:12:26 AM UTC 24
Finished	Sep 11 02:12:27 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321982290 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3321982290
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3826882082
Short name	T74
Test name
Test status
Simulation time	19382361 ps
CPU time	0.91 seconds
Started	Sep 11 02:12:30 AM UTC 24
Finished	Sep 11 02:12:32 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826882082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.3826882082
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1822592496
Short name	T465
Test name
Test status
Simulation time	218905120 ps
CPU time	1.8 seconds
Started	Sep 11 02:12:26 AM UTC 24
Finished	Sep 11 02:12:28 AM UTC 24
Peak memory	198844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822592496 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1822592496
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.728494373
Short name	T82
Test name
Test status
Simulation time	225705029 ps
CPU time	2.16 seconds
Started	Sep 11 02:12:26 AM UTC 24
Finished	Sep 11 02:12:29 AM UTC 24
Peak memory	200744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728494373 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.728494373
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2431252093
Short name	T513
Test name
Test status
Simulation time	80617918 ps
CPU time	0.86 seconds
Started	Sep 11 02:13:25 AM UTC 24
Finished	Sep 11 02:13:27 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431252093 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2431252093
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.1010292882
Short name	T572
Test name
Test status
Simulation time	64259573 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:25 AM UTC 24
Finished	Sep 11 02:13:27 AM UTC 24
Peak memory	198856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010292882 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1010292882
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2705180052
Short name	T533
Test name
Test status
Simulation time	41330509 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:25 AM UTC 24
Finished	Sep 11 02:13:27 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705180052 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2705180052
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2370358858
Short name	T573
Test name
Test status
Simulation time	15995818 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:25 AM UTC 24
Finished	Sep 11 02:13:27 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370358858 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2370358858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3494999341
Short name	T574
Test name
Test status
Simulation time	11836068 ps
CPU time	0.78 seconds
Started	Sep 11 02:13:26 AM UTC 24
Finished	Sep 11 02:13:28 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494999341 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3494999341
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2965522687
Short name	T575
Test name
Test status
Simulation time	51584675 ps
CPU time	0.87 seconds
Started	Sep 11 02:13:26 AM UTC 24
Finished	Sep 11 02:13:28 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965522687 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2965522687
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3724346309
Short name	T576
Test name
Test status
Simulation time	37127248 ps
CPU time	0.85 seconds
Started	Sep 11 02:13:26 AM UTC 24
Finished	Sep 11 02:13:28 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724346309 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3724346309
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3556298506
Short name	T577
Test name
Test status
Simulation time	26048359 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:26 AM UTC 24
Finished	Sep 11 02:13:28 AM UTC 24
Peak memory	198968 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556298506 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3556298506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1300137747
Short name	T579
Test name
Test status
Simulation time	22620725 ps
CPU time	0.84 seconds
Started	Sep 11 02:13:28 AM UTC 24
Finished	Sep 11 02:13:30 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300137747 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1300137747
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3662050645
Short name	T578
Test name
Test status
Simulation time	11913751 ps
CPU time	0.82 seconds
Started	Sep 11 02:13:28 AM UTC 24
Finished	Sep 11 02:13:30 AM UTC 24
Peak memory	198900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662050645 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3662050645
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2849897575
Short name	T474
Test name
Test status
Simulation time	327640067 ps
CPU time	1.64 seconds
Started	Sep 11 02:12:36 AM UTC 24
Finished	Sep 11 02:12:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2849897575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2849897575
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.4075171011
Short name	T68
Test name
Test status
Simulation time	19848808 ps
CPU time	0.85 seconds
Started	Sep 11 02:12:33 AM UTC 24
Finished	Sep 11 02:12:35 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075171011 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.4075171011
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.556620137
Short name	T472
Test name
Test status
Simulation time	98514176 ps
CPU time	0.77 seconds
Started	Sep 11 02:12:33 AM UTC 24
Finished	Sep 11 02:12:35 AM UTC 24
Peak memory	198904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556620137 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.556620137
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2551461215
Short name	T75
Test name
Test status
Simulation time	269560111 ps
CPU time	1.14 seconds
Started	Sep 11 02:12:34 AM UTC 24
Finished	Sep 11 02:12:37 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551461215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2551461215
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.351821086
Short name	T470
Test name
Test status
Simulation time	127233053 ps
CPU time	1.42 seconds
Started	Sep 11 02:12:32 AM UTC 24
Finished	Sep 11 02:12:35 AM UTC 24
Peak memory	199100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351821086 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.351821086
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1526633779
Short name	T471
Test name
Test status
Simulation time	173717401 ps
CPU time	1.9 seconds
Started	Sep 11 02:12:32 AM UTC 24
Finished	Sep 11 02:12:35 AM UTC 24
Peak memory	198852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526633779 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1526633779
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2351920890
Short name	T477
Test name
Test status
Simulation time	263732824 ps
CPU time	1.58 seconds
Started	Sep 11 02:12:39 AM UTC 24
Finished	Sep 11 02:12:42 AM UTC 24
Peak memory	201020 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2351920890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.2351920890
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2498997835
Short name	T69
Test name
Test status
Simulation time	14862448 ps
CPU time	0.86 seconds
Started	Sep 11 02:12:38 AM UTC 24
Finished	Sep 11 02:12:40 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498997835 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2498997835
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2194850555
Short name	T476
Test name
Test status
Simulation time	18769118 ps
CPU time	0.88 seconds
Started	Sep 11 02:12:37 AM UTC 24
Finished	Sep 11 02:12:39 AM UTC 24
Peak memory	198904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194850555 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2194850555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2825020189
Short name	T76
Test name
Test status
Simulation time	12679191 ps
CPU time	0.91 seconds
Started	Sep 11 02:12:38 AM UTC 24
Finished	Sep 11 02:12:40 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825020189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.2825020189
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.2385159312
Short name	T475
Test name
Test status
Simulation time	111213483 ps
CPU time	2.04 seconds
Started	Sep 11 02:12:36 AM UTC 24
Finished	Sep 11 02:12:39 AM UTC 24
Peak memory	200752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385159312 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2385159312
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.399449065
Short name	T473
Test name
Test status
Simulation time	64147688 ps
CPU time	1.07 seconds
Started	Sep 11 02:12:36 AM UTC 24
Finished	Sep 11 02:12:38 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399449065 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.399449065
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1523605528
Short name	T481
Test name
Test status
Simulation time	68142969 ps
CPU time	0.96 seconds
Started	Sep 11 02:12:42 AM UTC 24
Finished	Sep 11 02:12:45 AM UTC 24
Peak memory	198840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1523605528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.1523605528
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.2484618162
Short name	T479
Test name
Test status
Simulation time	14506193 ps
CPU time	0.85 seconds
Started	Sep 11 02:12:40 AM UTC 24
Finished	Sep 11 02:12:42 AM UTC 24
Peak memory	198848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484618162 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2484618162
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.917320167
Short name	T478
Test name
Test status
Simulation time	13568229 ps
CPU time	0.83 seconds
Started	Sep 11 02:12:40 AM UTC 24
Finished	Sep 11 02:12:42 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917320167 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.917320167
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3943771437
Short name	T77
Test name
Test status
Simulation time	53282128 ps
CPU time	0.88 seconds
Started	Sep 11 02:12:41 AM UTC 24
Finished	Sep 11 02:12:43 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943771437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.3943771437
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.1000606654
Short name	T480
Test name
Test status
Simulation time	289881497 ps
CPU time	2.35 seconds
Started	Sep 11 02:12:39 AM UTC 24
Finished	Sep 11 02:12:43 AM UTC 24
Peak memory	200680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000606654 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1000606654
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3966780688
Short name	T83
Test name
Test status
Simulation time	105597835 ps
CPU time	1.99 seconds
Started	Sep 11 02:12:39 AM UTC 24
Finished	Sep 11 02:12:42 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966780688 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.3966780688
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3125971115
Short name	T486
Test name
Test status
Simulation time	29301018 ps
CPU time	1.03 seconds
Started	Sep 11 02:12:46 AM UTC 24
Finished	Sep 11 02:12:48 AM UTC 24
Peak memory	198972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3125971115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.3125971115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.4031059909
Short name	T483
Test name
Test status
Simulation time	28596484 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:44 AM UTC 24
Finished	Sep 11 02:12:46 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031059909 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4031059909
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.564348127
Short name	T485
Test name
Test status
Simulation time	53018426 ps
CPU time	0.86 seconds
Started	Sep 11 02:12:44 AM UTC 24
Finished	Sep 11 02:12:46 AM UTC 24
Peak memory	198904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564348127 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.564348127
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3666418016
Short name	T78
Test name
Test status
Simulation time	104973473 ps
CPU time	1.08 seconds
Started	Sep 11 02:12:45 AM UTC 24
Finished	Sep 11 02:12:47 AM UTC 24
Peak memory	198912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666418016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.3666418016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1238456114
Short name	T484
Test name
Test status
Simulation time	609581277 ps
CPU time	2.07 seconds
Started	Sep 11 02:12:43 AM UTC 24
Finished	Sep 11 02:12:46 AM UTC 24
Peak memory	200752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238456114 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1238456114
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4180408732
Short name	T482
Test name
Test status
Simulation time	212213727 ps
CPU time	1.24 seconds
Started	Sep 11 02:12:43 AM UTC 24
Finished	Sep 11 02:12:45 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180408732 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.4180408732
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.880939392
Short name	T491
Test name
Test status
Simulation time	151382540 ps
CPU time	1.35 seconds
Started	Sep 11 02:12:49 AM UTC 24
Finished	Sep 11 02:12:52 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=880939392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr _mem_rw_with_rand_reset.880939392
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3307425148
Short name	T79
Test name
Test status
Simulation time	40925759 ps
CPU time	0.83 seconds
Started	Sep 11 02:12:47 AM UTC 24
Finished	Sep 11 02:12:49 AM UTC 24
Peak memory	199044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307425148 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3307425148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.2161693142
Short name	T487
Test name
Test status
Simulation time	17764128 ps
CPU time	0.82 seconds
Started	Sep 11 02:12:47 AM UTC 24
Finished	Sep 11 02:12:49 AM UTC 24
Peak memory	198976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161693142 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2161693142
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1061301063
Short name	T490
Test name
Test status
Simulation time	36743302 ps
CPU time	1.13 seconds
Started	Sep 11 02:12:48 AM UTC 24
Finished	Sep 11 02:12:51 AM UTC 24
Peak memory	199108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061301063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1061301063
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.2730370526
Short name	T488
Test name
Test status
Simulation time	118492183 ps
CPU time	1.9 seconds
Started	Sep 11 02:12:46 AM UTC 24
Finished	Sep 11 02:12:49 AM UTC 24
Peak memory	199100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730370526 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2730370526
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2008201869
Short name	T489
Test name
Test status
Simulation time	114878863 ps
CPU time	2.12 seconds
Started	Sep 11 02:12:47 AM UTC 24
Finished	Sep 11 02:12:50 AM UTC 24
Peak memory	200688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008201869 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.2008201869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.911838944
Short name	T3
Test name
Test status
Simulation time	2940412649 ps
CPU time	4.26 seconds
Started	Sep 11 01:28:00 AM UTC 24
Finished	Sep 11 01:28:05 AM UTC 24
Peak memory	199456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911838944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.911838944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.1906487737
Short name	T103
Test name
Test status
Simulation time	163005862280 ps
CPU time	152.84 seconds
Started	Sep 11 01:27:59 AM UTC 24
Finished	Sep 11 01:30:34 AM UTC 24
Peak memory	202444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906487737 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1906487737
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.4102160843
Short name	T1
Test name
Test status
Simulation time	81372230 ps
CPU time	0.55 seconds
Started	Sep 11 01:28:00 AM UTC 24
Finished	Sep 11 01:28:01 AM UTC 24
Peak memory	198936 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102160843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4102160843
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.272728716
Short name	T2
Test name
Test status
Simulation time	123940818 ps
CPU time	0.69 seconds
Started	Sep 11 01:28:01 AM UTC 24
Finished	Sep 11 01:28:03 AM UTC 24
Peak memory	230920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272728716 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.272728716
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.2576767825
Short name	T205
Test name
Test status
Simulation time	661885779407 ps
CPU time	2006.76 seconds
Started	Sep 11 01:28:01 AM UTC 24
Finished	Sep 11 02:01:47 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576767825 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.2576767825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.3729012031
Short name	T381
Test name
Test status
Simulation time	102651362013 ps
CPU time	138.57 seconds
Started	Sep 11 01:28:02 AM UTC 24
Finished	Sep 11 01:30:23 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729012031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3729012031
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3830849441
Short name	T139
Test name
Test status
Simulation time	54721284900 ps
CPU time	124.93 seconds
Started	Sep 11 01:28:03 AM UTC 24
Finished	Sep 11 01:30:10 AM UTC 24
Peak memory	199740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830849441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3830849441
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.1582864949
Short name	T4
Test name
Test status
Simulation time	244104795 ps
CPU time	0.7 seconds
Started	Sep 11 01:28:06 AM UTC 24
Finished	Sep 11 01:28:08 AM UTC 24
Peak memory	230916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582864949 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1582864949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.1735307159
Short name	T124
Test name
Test status
Simulation time	498967798744 ps
CPU time	396.68 seconds
Started	Sep 11 01:28:22 AM UTC 24
Finished	Sep 11 01:35:04 AM UTC 24
Peak memory	199720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735307159 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.1735307159
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.1660700442
Short name	T36
Test name
Test status
Simulation time	30759936970 ps
CPU time	84.66 seconds
Started	Sep 11 01:28:21 AM UTC 24
Finished	Sep 11 01:29:48 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660700442 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1660700442
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.2001286923
Short name	T10
Test name
Test status
Simulation time	64796019 ps
CPU time	0.97 seconds
Started	Sep 11 01:28:23 AM UTC 24
Finished	Sep 11 01:28:25 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001286923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2001286923
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.4275932325
Short name	T11
Test name
Test status
Simulation time	22916037 ps
CPU time	0.85 seconds
Started	Sep 11 01:28:23 AM UTC 24
Finished	Sep 11 01:28:25 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275932325 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.4275932325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2949645573
Short name	T258
Test name
Test status
Simulation time	21076210601 ps
CPU time	181.18 seconds
Started	Sep 11 01:57:45 AM UTC 24
Finished	Sep 11 02:00:49 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949645573 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2949645573
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/100.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3007150150
Short name	T371
Test name
Test status
Simulation time	20020658955 ps
CPU time	114.48 seconds
Started	Sep 11 01:57:56 AM UTC 24
Finished	Sep 11 01:59:53 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007150150 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3007150150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/102.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.1875605850
Short name	T308
Test name
Test status
Simulation time	206852717825 ps
CPU time	126.39 seconds
Started	Sep 11 01:58:25 AM UTC 24
Finished	Sep 11 02:00:34 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875605850 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1875605850
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/103.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.210447655
Short name	T322
Test name
Test status
Simulation time	216161258532 ps
CPU time	739.79 seconds
Started	Sep 11 01:58:51 AM UTC 24
Finished	Sep 11 02:11:20 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210447655 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.210447655
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/106.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.891168981
Short name	T232
Test name
Test status
Simulation time	118045832366 ps
CPU time	465.54 seconds
Started	Sep 11 01:59:03 AM UTC 24
Finished	Sep 11 02:06:55 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891168981 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.891168981
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/107.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.1661366075
Short name	T222
Test name
Test status
Simulation time	102950462649 ps
CPU time	440.18 seconds
Started	Sep 11 01:59:19 AM UTC 24
Finished	Sep 11 02:06:44 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661366075 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1661366075
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/108.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.2605610055
Short name	T354
Test name
Test status
Simulation time	32046107901 ps
CPU time	115.2 seconds
Started	Sep 11 01:59:27 AM UTC 24
Finished	Sep 11 02:01:24 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605610055 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2605610055
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/109.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.206812250
Short name	T390
Test name
Test status
Simulation time	146780375178 ps
CPU time	329.88 seconds
Started	Sep 11 01:28:26 AM UTC 24
Finished	Sep 11 01:34:00 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206812250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.206812250
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/11.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.2270730581
Short name	T279
Test name
Test status
Simulation time	278459839468 ps
CPU time	141.22 seconds
Started	Sep 11 01:59:45 AM UTC 24
Finished	Sep 11 02:02:08 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270730581 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2270730581
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/111.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.217602436
Short name	T345
Test name
Test status
Simulation time	58398530364 ps
CPU time	2348.1 seconds
Started	Sep 11 01:59:46 AM UTC 24
Finished	Sep 11 02:39:21 AM UTC 24
Peak memory	202404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217602436 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.217602436
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/112.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3820177689
Short name	T157
Test name
Test status
Simulation time	250053962325 ps
CPU time	240.94 seconds
Started	Sep 11 01:59:54 AM UTC 24
Finished	Sep 11 02:03:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820177689 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3820177689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/113.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.445391219
Short name	T438
Test name
Test status
Simulation time	33136910134 ps
CPU time	389.92 seconds
Started	Sep 11 02:00:01 AM UTC 24
Finished	Sep 11 02:06:40 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445391219 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.445391219
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/114.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.720475686
Short name	T201
Test name
Test status
Simulation time	102016761622 ps
CPU time	185.87 seconds
Started	Sep 11 02:00:32 AM UTC 24
Finished	Sep 11 02:03:41 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720475686 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.720475686
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/115.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3862514781
Short name	T448
Test name
Test status
Simulation time	127149904494 ps
CPU time	1657.76 seconds
Started	Sep 11 02:00:34 AM UTC 24
Finished	Sep 11 02:28:32 AM UTC 24
Peak memory	202352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862514781 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3862514781
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/116.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2904692769
Short name	T331
Test name
Test status
Simulation time	165300717048 ps
CPU time	313.17 seconds
Started	Sep 11 02:00:50 AM UTC 24
Finished	Sep 11 02:06:08 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904692769 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2904692769
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/117.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.3719699074
Short name	T133
Test name
Test status
Simulation time	362241067682 ps
CPU time	362.08 seconds
Started	Sep 11 01:28:41 AM UTC 24
Finished	Sep 11 01:34:48 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719699074 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.3719699074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1273624873
Short name	T384
Test name
Test status
Simulation time	325034429524 ps
CPU time	169.78 seconds
Started	Sep 11 01:28:38 AM UTC 24
Finished	Sep 11 01:31:31 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273624873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1273624873
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/12.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.1890203973
Short name	T233
Test name
Test status
Simulation time	132903832521 ps
CPU time	433.39 seconds
Started	Sep 11 02:01:28 AM UTC 24
Finished	Sep 11 02:08:47 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890203973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1890203973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/120.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3602131431
Short name	T284
Test name
Test status
Simulation time	213430168751 ps
CPU time	128.81 seconds
Started	Sep 11 02:01:48 AM UTC 24
Finished	Sep 11 02:03:59 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602131431 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3602131431
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/121.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1863293658
Short name	T321
Test name
Test status
Simulation time	12800156499 ps
CPU time	18.74 seconds
Started	Sep 11 02:02:01 AM UTC 24
Finished	Sep 11 02:02:21 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863293658 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1863293658
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/122.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.112586060
Short name	T351
Test name
Test status
Simulation time	656421415691 ps
CPU time	983.01 seconds
Started	Sep 11 02:02:22 AM UTC 24
Finished	Sep 11 02:18:57 AM UTC 24
Peak memory	202456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112586060 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.112586060
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/124.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.3575813044
Short name	T364
Test name
Test status
Simulation time	67778964621 ps
CPU time	301.52 seconds
Started	Sep 11 02:02:33 AM UTC 24
Finished	Sep 11 02:07:39 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575813044 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3575813044
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/126.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.364140850
Short name	T360
Test name
Test status
Simulation time	2633559730 ps
CPU time	15.71 seconds
Started	Sep 11 02:02:40 AM UTC 24
Finished	Sep 11 02:02:56 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364140850 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.364140850
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/128.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1003662785
Short name	T358
Test name
Test status
Simulation time	50297050163 ps
CPU time	134.92 seconds
Started	Sep 11 02:02:47 AM UTC 24
Finished	Sep 11 02:05:04 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003662785 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1003662785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/129.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.3083491966
Short name	T394
Test name
Test status
Simulation time	163496118857 ps
CPU time	426.55 seconds
Started	Sep 11 01:28:52 AM UTC 24
Finished	Sep 11 01:36:04 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083491966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3083491966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.2220256035
Short name	T88
Test name
Test status
Simulation time	188844809494 ps
CPU time	259.56 seconds
Started	Sep 11 01:28:52 AM UTC 24
Finished	Sep 11 01:33:15 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220256035 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2220256035
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.3258637077
Short name	T17
Test name
Test status
Simulation time	6900119045 ps
CPU time	6.12 seconds
Started	Sep 11 01:29:00 AM UTC 24
Finished	Sep 11 01:29:07 AM UTC 24
Peak memory	199748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258637077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3258637077
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all_with_rand_reset.1161127634
Short name	T18
Test name
Test status
Simulation time	5025630462 ps
CPU time	40.27 seconds
Started	Sep 11 01:29:08 AM UTC 24
Finished	Sep 11 01:29:50 AM UTC 24
Peak memory	204016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1161127634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.rv_timer_stress_all_with_rand_reset.1161127634
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.2638956805
Short name	T266
Test name
Test status
Simulation time	96977698691 ps
CPU time	407.5 seconds
Started	Sep 11 02:02:47 AM UTC 24
Finished	Sep 11 02:09:40 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638956805 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2638956805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/130.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.2417549768
Short name	T336
Test name
Test status
Simulation time	102694827406 ps
CPU time	103.55 seconds
Started	Sep 11 02:02:57 AM UTC 24
Finished	Sep 11 02:04:42 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417549768 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2417549768
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/131.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.829620501
Short name	T355
Test name
Test status
Simulation time	480501492009 ps
CPU time	259.02 seconds
Started	Sep 11 02:03:10 AM UTC 24
Finished	Sep 11 02:07:32 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829620501 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.829620501
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/134.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2017990988
Short name	T314
Test name
Test status
Simulation time	332222943438 ps
CPU time	415.6 seconds
Started	Sep 11 02:03:18 AM UTC 24
Finished	Sep 11 02:10:19 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017990988 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2017990988
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/135.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1825093812
Short name	T363
Test name
Test status
Simulation time	94652879839 ps
CPU time	269.01 seconds
Started	Sep 11 02:03:42 AM UTC 24
Finished	Sep 11 02:08:15 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825093812 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1825093812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/136.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.2168747988
Short name	T273
Test name
Test status
Simulation time	431283259949 ps
CPU time	163.95 seconds
Started	Sep 11 02:03:43 AM UTC 24
Finished	Sep 11 02:06:30 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168747988 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2168747988
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/137.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2212689866
Short name	T206
Test name
Test status
Simulation time	135334306676 ps
CPU time	90.91 seconds
Started	Sep 11 02:03:47 AM UTC 24
Finished	Sep 11 02:05:20 AM UTC 24
Peak memory	199524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212689866 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2212689866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/138.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.3695798021
Short name	T352
Test name
Test status
Simulation time	133511859980 ps
CPU time	300.43 seconds
Started	Sep 11 02:03:55 AM UTC 24
Finished	Sep 11 02:09:00 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695798021 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3695798021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/139.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.3702077297
Short name	T138
Test name
Test status
Simulation time	303363946799 ps
CPU time	706.74 seconds
Started	Sep 11 01:29:30 AM UTC 24
Finished	Sep 11 01:41:25 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702077297 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3702077297
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.1639171354
Short name	T385
Test name
Test status
Simulation time	75273063021 ps
CPU time	189.39 seconds
Started	Sep 11 01:29:21 AM UTC 24
Finished	Sep 11 01:32:33 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639171354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1639171354
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/14.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.3224558240
Short name	T296
Test name
Test status
Simulation time	68790553813 ps
CPU time	120.51 seconds
Started	Sep 11 02:04:22 AM UTC 24
Finished	Sep 11 02:06:24 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224558240 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3224558240
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/142.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.290876867
Short name	T251
Test name
Test status
Simulation time	312884873869 ps
CPU time	811.52 seconds
Started	Sep 11 02:04:28 AM UTC 24
Finished	Sep 11 02:18:09 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290876867 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.290876867
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/143.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.130902635
Short name	T262
Test name
Test status
Simulation time	174776764357 ps
CPU time	257 seconds
Started	Sep 11 02:05:21 AM UTC 24
Finished	Sep 11 02:09:41 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130902635 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.130902635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/148.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.3702490260
Short name	T325
Test name
Test status
Simulation time	345656473496 ps
CPU time	279.14 seconds
Started	Sep 11 02:05:35 AM UTC 24
Finished	Sep 11 02:10:18 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702490260 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3702490260
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/149.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.287085083
Short name	T382
Test name
Test status
Simulation time	219284794036 ps
CPU time	42.67 seconds
Started	Sep 11 01:29:51 AM UTC 24
Finished	Sep 11 01:30:35 AM UTC 24
Peak memory	199872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287085083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.287085083
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1753076476
Short name	T274
Test name
Test status
Simulation time	219458659556 ps
CPU time	152.44 seconds
Started	Sep 11 01:30:00 AM UTC 24
Finished	Sep 11 01:32:35 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753076476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1753076476
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.1201611549
Short name	T400
Test name
Test status
Simulation time	840230997362 ps
CPU time	533.01 seconds
Started	Sep 11 01:30:11 AM UTC 24
Finished	Sep 11 01:39:10 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201611549 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.1201611549
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/15.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.2196430992
Short name	T247
Test name
Test status
Simulation time	108723816356 ps
CPU time	135.43 seconds
Started	Sep 11 02:06:03 AM UTC 24
Finished	Sep 11 02:08:21 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196430992 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2196430992
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/151.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.568002096
Short name	T344
Test name
Test status
Simulation time	253766908477 ps
CPU time	115.49 seconds
Started	Sep 11 02:06:09 AM UTC 24
Finished	Sep 11 02:08:06 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568002096 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.568002096
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/152.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3715580305
Short name	T335
Test name
Test status
Simulation time	96360470780 ps
CPU time	89.65 seconds
Started	Sep 11 02:06:25 AM UTC 24
Finished	Sep 11 02:07:56 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715580305 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3715580305
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/153.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.720501310
Short name	T343
Test name
Test status
Simulation time	380770369162 ps
CPU time	450.49 seconds
Started	Sep 11 02:06:40 AM UTC 24
Finished	Sep 11 02:14:17 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720501310 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.720501310
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/155.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2981806382
Short name	T367
Test name
Test status
Simulation time	104865656449 ps
CPU time	693.98 seconds
Started	Sep 11 02:06:45 AM UTC 24
Finished	Sep 11 02:18:28 AM UTC 24
Peak memory	199740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981806382 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2981806382
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/157.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.524343226
Short name	T330
Test name
Test status
Simulation time	168730656072 ps
CPU time	187.56 seconds
Started	Sep 11 02:06:49 AM UTC 24
Finished	Sep 11 02:10:00 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524343226 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.524343226
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/158.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.2867825255
Short name	T440
Test name
Test status
Simulation time	85252994619 ps
CPU time	155.53 seconds
Started	Sep 11 02:06:55 AM UTC 24
Finished	Sep 11 02:09:33 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867825255 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2867825255
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/159.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.4079829589
Short name	T112
Test name
Test status
Simulation time	734376494880 ps
CPU time	451.86 seconds
Started	Sep 11 01:30:22 AM UTC 24
Finished	Sep 11 01:38:00 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079829589 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.4079829589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2793718098
Short name	T391
Test name
Test status
Simulation time	269496410914 ps
CPU time	225.96 seconds
Started	Sep 11 01:30:16 AM UTC 24
Finished	Sep 11 01:34:05 AM UTC 24
Peak memory	199652 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793718098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2793718098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.935181724
Short name	T98
Test name
Test status
Simulation time	159011887534 ps
CPU time	783.7 seconds
Started	Sep 11 01:30:13 AM UTC 24
Finished	Sep 11 01:43:26 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935181724 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.935181724
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2417055539
Short name	T140
Test name
Test status
Simulation time	15763977191 ps
CPU time	54.42 seconds
Started	Sep 11 01:30:24 AM UTC 24
Finished	Sep 11 01:31:21 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417055539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2417055539
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.213939133
Short name	T130
Test name
Test status
Simulation time	727423107969 ps
CPU time	619.59 seconds
Started	Sep 11 01:30:27 AM UTC 24
Finished	Sep 11 01:40:55 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213939133 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.213939133
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/16.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.9930979
Short name	T186
Test name
Test status
Simulation time	250117304897 ps
CPU time	119.86 seconds
Started	Sep 11 02:07:18 AM UTC 24
Finished	Sep 11 02:09:21 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9930979 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.9930979
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/161.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.1780768376
Short name	T283
Test name
Test status
Simulation time	111425750652 ps
CPU time	198.36 seconds
Started	Sep 11 02:07:21 AM UTC 24
Finished	Sep 11 02:10:43 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780768376 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1780768376
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/162.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.23303384
Short name	T443
Test name
Test status
Simulation time	801759769036 ps
CPU time	508.14 seconds
Started	Sep 11 02:07:33 AM UTC 24
Finished	Sep 11 02:16:07 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23303384 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.23303384
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/163.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.1586116559
Short name	T441
Test name
Test status
Simulation time	33925315859 ps
CPU time	171.49 seconds
Started	Sep 11 02:07:40 AM UTC 24
Finished	Sep 11 02:10:34 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586116559 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1586116559
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/164.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.3857920844
Short name	T366
Test name
Test status
Simulation time	87543600089 ps
CPU time	136.12 seconds
Started	Sep 11 02:07:57 AM UTC 24
Finished	Sep 11 02:10:15 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857920844 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3857920844
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/166.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2613067558
Short name	T347
Test name
Test status
Simulation time	217934748556 ps
CPU time	275.23 seconds
Started	Sep 11 02:07:58 AM UTC 24
Finished	Sep 11 02:12:37 AM UTC 24
Peak memory	199672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613067558 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2613067558
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/167.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.2725201668
Short name	T439
Test name
Test status
Simulation time	34517943105 ps
CPU time	30.74 seconds
Started	Sep 11 02:08:07 AM UTC 24
Finished	Sep 11 02:08:39 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725201668 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2725201668
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/168.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1266024094
Short name	T272
Test name
Test status
Simulation time	297790161627 ps
CPU time	273.96 seconds
Started	Sep 11 02:08:16 AM UTC 24
Finished	Sep 11 02:12:54 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266024094 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1266024094
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/169.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.2820376434
Short name	T202
Test name
Test status
Simulation time	1925023523573 ps
CPU time	809.91 seconds
Started	Sep 11 01:30:39 AM UTC 24
Finished	Sep 11 01:44:18 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820376434 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.2820376434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3586409764
Short name	T51
Test name
Test status
Simulation time	78728830646 ps
CPU time	104.86 seconds
Started	Sep 11 01:30:35 AM UTC 24
Finished	Sep 11 01:32:23 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586409764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3586409764
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.847653973
Short name	T278
Test name
Test status
Simulation time	108352029076 ps
CPU time	536.28 seconds
Started	Sep 11 01:30:35 AM UTC 24
Finished	Sep 11 01:39:39 AM UTC 24
Peak memory	199320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847653973 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.847653973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.2351280736
Short name	T45
Test name
Test status
Simulation time	68359939206 ps
CPU time	43.42 seconds
Started	Sep 11 01:30:53 AM UTC 24
Finished	Sep 11 01:31:38 AM UTC 24
Peak memory	199780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351280736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2351280736
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.2810804433
Short name	T59
Test name
Test status
Simulation time	774953138589 ps
CPU time	816.51 seconds
Started	Sep 11 01:31:13 AM UTC 24
Finished	Sep 11 01:44:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810804433 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.2810804433
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all_with_rand_reset.468911003
Short name	T19
Test name
Test status
Simulation time	2674583038 ps
CPU time	19.26 seconds
Started	Sep 11 01:31:13 AM UTC 24
Finished	Sep 11 01:31:33 AM UTC 24
Peak memory	202040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=468911003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.468911003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1945426243
Short name	T444
Test name
Test status
Simulation time	70620803012 ps
CPU time	476.35 seconds
Started	Sep 11 02:08:21 AM UTC 24
Finished	Sep 11 02:16:24 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945426243 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1945426243
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/170.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.2446871098
Short name	T198
Test name
Test status
Simulation time	47641673186 ps
CPU time	73.23 seconds
Started	Sep 11 02:08:28 AM UTC 24
Finished	Sep 11 02:09:43 AM UTC 24
Peak memory	199588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446871098 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2446871098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/171.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.3432829913
Short name	T337
Test name
Test status
Simulation time	187011780323 ps
CPU time	182.84 seconds
Started	Sep 11 02:08:37 AM UTC 24
Finished	Sep 11 02:11:43 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432829913 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3432829913
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/172.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.3484737882
Short name	T160
Test name
Test status
Simulation time	100329569110 ps
CPU time	404.47 seconds
Started	Sep 11 02:08:40 AM UTC 24
Finished	Sep 11 02:15:30 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484737882 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3484737882
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/173.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.542469089
Short name	T320
Test name
Test status
Simulation time	1666780192030 ps
CPU time	607.91 seconds
Started	Sep 11 02:08:47 AM UTC 24
Finished	Sep 11 02:19:03 AM UTC 24
Peak memory	199692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542469089 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.542469089
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/174.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1268789194
Short name	T375
Test name
Test status
Simulation time	34096390842 ps
CPU time	98.97 seconds
Started	Sep 11 02:09:01 AM UTC 24
Finished	Sep 11 02:10:42 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268789194 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1268789194
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/175.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.1816268336
Short name	T256
Test name
Test status
Simulation time	167584861427 ps
CPU time	325.88 seconds
Started	Sep 11 02:09:07 AM UTC 24
Finished	Sep 11 02:14:37 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816268336 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1816268336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/177.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.547879070
Short name	T377
Test name
Test status
Simulation time	44815514959 ps
CPU time	75.07 seconds
Started	Sep 11 02:09:22 AM UTC 24
Finished	Sep 11 02:10:39 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547879070 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.547879070
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/178.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.1013398027
Short name	T393
Test name
Test status
Simulation time	199045919907 ps
CPU time	226.39 seconds
Started	Sep 11 01:31:32 AM UTC 24
Finished	Sep 11 01:35:22 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013398027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1013398027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1017569188
Short name	T106
Test name
Test status
Simulation time	378314797618 ps
CPU time	246.42 seconds
Started	Sep 11 01:31:22 AM UTC 24
Finished	Sep 11 01:35:32 AM UTC 24
Peak memory	199732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017569188 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1017569188
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.807612407
Short name	T46
Test name
Test status
Simulation time	348359355 ps
CPU time	1.55 seconds
Started	Sep 11 01:31:37 AM UTC 24
Finished	Sep 11 01:31:40 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807612407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.807612407
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/18.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.1667242128
Short name	T255
Test name
Test status
Simulation time	112973755979 ps
CPU time	168.58 seconds
Started	Sep 11 02:09:40 AM UTC 24
Finished	Sep 11 02:12:32 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667242128 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1667242128
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/180.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2916897615
Short name	T303
Test name
Test status
Simulation time	129361951123 ps
CPU time	563.34 seconds
Started	Sep 11 02:09:42 AM UTC 24
Finished	Sep 11 02:19:12 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916897615 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2916897615
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/181.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.1208828545
Short name	T447
Test name
Test status
Simulation time	111371533577 ps
CPU time	1075.45 seconds
Started	Sep 11 02:09:44 AM UTC 24
Finished	Sep 11 02:27:52 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208828545 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1208828545
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/182.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.351823609
Short name	T350
Test name
Test status
Simulation time	856854361090 ps
CPU time	388.03 seconds
Started	Sep 11 02:10:00 AM UTC 24
Finished	Sep 11 02:16:34 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351823609 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.351823609
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/184.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.1775543921
Short name	T376
Test name
Test status
Simulation time	198898854377 ps
CPU time	384.62 seconds
Started	Sep 11 02:10:05 AM UTC 24
Finished	Sep 11 02:16:35 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775543921 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1775543921
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/185.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.226750583
Short name	T317
Test name
Test status
Simulation time	158696243534 ps
CPU time	675.2 seconds
Started	Sep 11 02:10:10 AM UTC 24
Finished	Sep 11 02:21:34 AM UTC 24
Peak memory	202444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226750583 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.226750583
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/186.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.2606158243
Short name	T341
Test name
Test status
Simulation time	56804127317 ps
CPU time	59.6 seconds
Started	Sep 11 02:10:16 AM UTC 24
Finished	Sep 11 02:11:17 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606158243 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2606158243
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/187.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.1762745803
Short name	T291
Test name
Test status
Simulation time	169861026979 ps
CPU time	1056.27 seconds
Started	Sep 11 02:10:20 AM UTC 24
Finished	Sep 11 02:28:07 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762745803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1762745803
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/189.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.1801364531
Short name	T135
Test name
Test status
Simulation time	818040287585 ps
CPU time	417.71 seconds
Started	Sep 11 01:31:57 AM UTC 24
Finished	Sep 11 01:39:00 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801364531 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1801364531
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1731770685
Short name	T126
Test name
Test status
Simulation time	172189020873 ps
CPU time	374.13 seconds
Started	Sep 11 01:31:47 AM UTC 24
Finished	Sep 11 01:38:06 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731770685 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1731770685
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.189046808
Short name	T92
Test name
Test status
Simulation time	72367016298 ps
CPU time	147.24 seconds
Started	Sep 11 01:32:07 AM UTC 24
Finished	Sep 11 01:34:36 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189046808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.189046808
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.18957476
Short name	T238
Test name
Test status
Simulation time	1063896055976 ps
CPU time	930.54 seconds
Started	Sep 11 01:32:11 AM UTC 24
Finished	Sep 11 01:47:52 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18957476 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.18957476
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1943672816
Short name	T264
Test name
Test status
Simulation time	194307888259 ps
CPU time	771.24 seconds
Started	Sep 11 02:10:27 AM UTC 24
Finished	Sep 11 02:23:28 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943672816 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1943672816
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/190.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.3682067272
Short name	T374
Test name
Test status
Simulation time	327434931763 ps
CPU time	1496.3 seconds
Started	Sep 11 02:10:42 AM UTC 24
Finished	Sep 11 02:35:56 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682067272 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3682067272
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/193.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3534917814
Short name	T450
Test name
Test status
Simulation time	263004167441 ps
CPU time	1767.85 seconds
Started	Sep 11 02:11:15 AM UTC 24
Finished	Sep 11 02:41:04 AM UTC 24
Peak memory	202404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534917814 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3534917814
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/196.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.2424764252
Short name	T356
Test name
Test status
Simulation time	293138965293 ps
CPU time	607.13 seconds
Started	Sep 11 02:11:17 AM UTC 24
Finished	Sep 11 02:21:32 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424764252 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2424764252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/197.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.127912621
Short name	T241
Test name
Test status
Simulation time	110207212809 ps
CPU time	374.15 seconds
Started	Sep 11 02:11:44 AM UTC 24
Finished	Sep 11 02:18:03 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127912621 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.127912621
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/199.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3685696471
Short name	T105
Test name
Test status
Simulation time	1324218816853 ps
CPU time	532.53 seconds
Started	Sep 11 01:28:07 AM UTC 24
Finished	Sep 11 01:37:06 AM UTC 24
Peak memory	202524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685696471 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3685696471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.4211557626
Short name	T389
Test name
Test status
Simulation time	221157246038 ps
CPU time	333.84 seconds
Started	Sep 11 01:28:07 AM UTC 24
Finished	Sep 11 01:33:45 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211557626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4211557626
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.990031196
Short name	T101
Test name
Test status
Simulation time	117217800979 ps
CPU time	396.5 seconds
Started	Sep 11 01:28:06 AM UTC 24
Finished	Sep 11 01:34:48 AM UTC 24
Peak memory	202348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990031196 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.990031196
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.976724229
Short name	T33
Test name
Test status
Simulation time	77828882170 ps
CPU time	70.52 seconds
Started	Sep 11 01:28:08 AM UTC 24
Finished	Sep 11 01:29:20 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976724229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.976724229
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.908391008
Short name	T5
Test name
Test status
Simulation time	63077145 ps
CPU time	0.78 seconds
Started	Sep 11 01:28:14 AM UTC 24
Finished	Sep 11 01:28:16 AM UTC 24
Peak memory	230920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908391008 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.908391008
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2054244986
Short name	T50
Test name
Test status
Simulation time	115215991831 ps
CPU time	235.76 seconds
Started	Sep 11 01:28:11 AM UTC 24
Finished	Sep 11 01:32:10 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054244986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2054244986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/2.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.3842075973
Short name	T131
Test name
Test status
Simulation time	327549872652 ps
CPU time	324.85 seconds
Started	Sep 11 01:32:29 AM UTC 24
Finished	Sep 11 01:37:58 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842075973 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.3842075973
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3598464264
Short name	T396
Test name
Test status
Simulation time	162190205778 ps
CPU time	324.2 seconds
Started	Sep 11 01:32:24 AM UTC 24
Finished	Sep 11 01:37:52 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598464264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3598464264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.626136621
Short name	T86
Test name
Test status
Simulation time	58062284988 ps
CPU time	153.53 seconds
Started	Sep 11 01:32:14 AM UTC 24
Finished	Sep 11 01:34:50 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626136621 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.626136621
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.226624171
Short name	T115
Test name
Test status
Simulation time	137282457111 ps
CPU time	216.13 seconds
Started	Sep 11 01:32:34 AM UTC 24
Finished	Sep 11 01:36:13 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226624171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.226624171
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.2380239902
Short name	T26
Test name
Test status
Simulation time	7724650484 ps
CPU time	50.83 seconds
Started	Sep 11 01:32:35 AM UTC 24
Finished	Sep 11 01:33:28 AM UTC 24
Peak memory	203880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2380239902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.rv_timer_stress_all_with_rand_reset.2380239902
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.813699358
Short name	T142
Test name
Test status
Simulation time	344957409949 ps
CPU time	540.95 seconds
Started	Sep 11 01:33:15 AM UTC 24
Finished	Sep 11 01:42:22 AM UTC 24
Peak memory	199716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813699358 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.813699358
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.1339170115
Short name	T395
Test name
Test status
Simulation time	154566009247 ps
CPU time	245.78 seconds
Started	Sep 11 01:32:47 AM UTC 24
Finished	Sep 11 01:36:57 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339170115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1339170115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.687604209
Short name	T93
Test name
Test status
Simulation time	47080860346 ps
CPU time	35.93 seconds
Started	Sep 11 01:32:37 AM UTC 24
Finished	Sep 11 01:33:14 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687604209 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.687604209
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.808423009
Short name	T388
Test name
Test status
Simulation time	776064936 ps
CPU time	1.34 seconds
Started	Sep 11 01:33:16 AM UTC 24
Finished	Sep 11 01:33:18 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808423009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.808423009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/21.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.4247182574
Short name	T104
Test name
Test status
Simulation time	99153682250 ps
CPU time	71.83 seconds
Started	Sep 11 01:33:46 AM UTC 24
Finished	Sep 11 01:35:00 AM UTC 24
Peak memory	199784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247182574 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.4247182574
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.2451116349
Short name	T399
Test name
Test status
Simulation time	590645349223 ps
CPU time	307.48 seconds
Started	Sep 11 01:33:46 AM UTC 24
Finished	Sep 11 01:38:58 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451116349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2451116349
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.305219445
Short name	T151
Test name
Test status
Simulation time	497011652924 ps
CPU time	1741.81 seconds
Started	Sep 11 01:33:42 AM UTC 24
Finished	Sep 11 02:03:03 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305219445 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.305219445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2994599003
Short name	T110
Test name
Test status
Simulation time	93971641284 ps
CPU time	322.99 seconds
Started	Sep 11 01:34:02 AM UTC 24
Finished	Sep 11 01:39:31 AM UTC 24
Peak memory	199844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994599003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2994599003
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/22.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.3097172576
Short name	T107
Test name
Test status
Simulation time	948191298954 ps
CPU time	456.56 seconds
Started	Sep 11 01:34:38 AM UTC 24
Finished	Sep 11 01:42:20 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097172576 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3097172576
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.3294475849
Short name	T402
Test name
Test status
Simulation time	655347538497 ps
CPU time	295.77 seconds
Started	Sep 11 01:34:30 AM UTC 24
Finished	Sep 11 01:39:30 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294475849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3294475849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1837948945
Short name	T125
Test name
Test status
Simulation time	85121308130 ps
CPU time	72.99 seconds
Started	Sep 11 01:34:22 AM UTC 24
Finished	Sep 11 01:35:37 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837948945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1837948945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2547342715
Short name	T91
Test name
Test status
Simulation time	135532523295 ps
CPU time	339.44 seconds
Started	Sep 11 01:34:49 AM UTC 24
Finished	Sep 11 01:40:33 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547342715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2547342715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/23.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2353091552
Short name	T141
Test name
Test status
Simulation time	38126728528 ps
CPU time	26.07 seconds
Started	Sep 11 01:35:23 AM UTC 24
Finished	Sep 11 01:35:50 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353091552 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2353091552
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.4254437179
Short name	T398
Test name
Test status
Simulation time	460511824604 ps
CPU time	182.98 seconds
Started	Sep 11 01:35:05 AM UTC 24
Finished	Sep 11 01:38:11 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254437179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4254437179
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.1674937789
Short name	T123
Test name
Test status
Simulation time	422420866749 ps
CPU time	254.14 seconds
Started	Sep 11 01:35:23 AM UTC 24
Finished	Sep 11 01:39:41 AM UTC 24
Peak memory	199744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674937789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1674937789
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/24.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.714998904
Short name	T95
Test name
Test status
Simulation time	20106548574 ps
CPU time	29.8 seconds
Started	Sep 11 01:35:45 AM UTC 24
Finished	Sep 11 01:36:16 AM UTC 24
Peak memory	199676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714998904 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.714998904
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.1804262395
Short name	T404
Test name
Test status
Simulation time	657398135535 ps
CPU time	327.85 seconds
Started	Sep 11 01:35:37 AM UTC 24
Finished	Sep 11 01:41:09 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804262395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1804262395
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.3449614633
Short name	T118
Test name
Test status
Simulation time	100909835106 ps
CPU time	41.01 seconds
Started	Sep 11 01:35:50 AM UTC 24
Finished	Sep 11 01:36:33 AM UTC 24
Peak memory	199456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449614633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3449614633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.1105069122
Short name	T403
Test name
Test status
Simulation time	268665161760 ps
CPU time	288.07 seconds
Started	Sep 11 01:35:52 AM UTC 24
Finished	Sep 11 01:40:44 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105069122 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.1105069122
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/25.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.3387757705
Short name	T397
Test name
Test status
Simulation time	190617242257 ps
CPU time	118.94 seconds
Started	Sep 11 01:35:59 AM UTC 24
Finished	Sep 11 01:38:00 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387757705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3387757705
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2649608385
Short name	T318
Test name
Test status
Simulation time	66896039382 ps
CPU time	154.49 seconds
Started	Sep 11 01:35:55 AM UTC 24
Finished	Sep 11 01:38:32 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649608385 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2649608385
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1213621127
Short name	T102
Test name
Test status
Simulation time	51792189562 ps
CPU time	149.64 seconds
Started	Sep 11 01:36:10 AM UTC 24
Finished	Sep 11 01:38:42 AM UTC 24
Peak memory	199672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213621127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1213621127
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/26.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.3644877026
Short name	T208
Test name
Test status
Simulation time	389355216182 ps
CPU time	633.38 seconds
Started	Sep 11 01:36:33 AM UTC 24
Finished	Sep 11 01:47:14 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644877026 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.3644877026
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.813330986
Short name	T401
Test name
Test status
Simulation time	225149420535 ps
CPU time	167.92 seconds
Started	Sep 11 01:36:28 AM UTC 24
Finished	Sep 11 01:39:19 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813330986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.813330986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.528887600
Short name	T132
Test name
Test status
Simulation time	473930654157 ps
CPU time	373.6 seconds
Started	Sep 11 01:36:18 AM UTC 24
Finished	Sep 11 01:42:37 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528887600 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.528887600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.1465227322
Short name	T99
Test name
Test status
Simulation time	262119533971 ps
CPU time	79.19 seconds
Started	Sep 11 01:36:58 AM UTC 24
Finished	Sep 11 01:38:19 AM UTC 24
Peak memory	199812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465227322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1465227322
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/27.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.4074918869
Short name	T146
Test name
Test status
Simulation time	3226790656189 ps
CPU time	988.41 seconds
Started	Sep 11 01:37:53 AM UTC 24
Finished	Sep 11 01:54:33 AM UTC 24
Peak memory	202588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074918869 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.4074918869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.1992367145
Short name	T405
Test name
Test status
Simulation time	614923532292 ps
CPU time	228.03 seconds
Started	Sep 11 01:37:45 AM UTC 24
Finished	Sep 11 01:41:36 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992367145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1992367145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.1832950554
Short name	T188
Test name
Test status
Simulation time	476909872117 ps
CPU time	407.61 seconds
Started	Sep 11 01:37:36 AM UTC 24
Finished	Sep 11 01:44:29 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832950554 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1832950554
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2836781419
Short name	T298
Test name
Test status
Simulation time	32387534877 ps
CPU time	73.04 seconds
Started	Sep 11 01:37:56 AM UTC 24
Finished	Sep 11 01:39:11 AM UTC 24
Peak memory	199608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836781419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2836781419
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.2245338007
Short name	T60
Test name
Test status
Simulation time	341650115955 ps
CPU time	428.48 seconds
Started	Sep 11 01:38:01 AM UTC 24
Finished	Sep 11 01:45:15 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245338007 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.2245338007
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.2372182756
Short name	T27
Test name
Test status
Simulation time	3881617900 ps
CPU time	44.95 seconds
Started	Sep 11 01:37:59 AM UTC 24
Finished	Sep 11 01:38:46 AM UTC 24
Peak memory	203880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2372182756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.2372182756
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.3209397285
Short name	T116
Test name
Test status
Simulation time	189618408873 ps
CPU time	163.22 seconds
Started	Sep 11 01:38:11 AM UTC 24
Finished	Sep 11 01:40:57 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209397285 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3209397285
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.1985468218
Short name	T407
Test name
Test status
Simulation time	490555510257 ps
CPU time	223.63 seconds
Started	Sep 11 01:38:07 AM UTC 24
Finished	Sep 11 01:41:54 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985468218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1985468218
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1020584858
Short name	T143
Test name
Test status
Simulation time	204761830363 ps
CPU time	216.9 seconds
Started	Sep 11 01:38:01 AM UTC 24
Finished	Sep 11 01:41:41 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020584858 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1020584858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.563930408
Short name	T136
Test name
Test status
Simulation time	5871536463 ps
CPU time	65.54 seconds
Started	Sep 11 01:38:20 AM UTC 24
Finished	Sep 11 01:39:27 AM UTC 24
Peak memory	199776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563930408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.563930408
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.234854514
Short name	T61
Test name
Test status
Simulation time	795214482985 ps
CPU time	488.19 seconds
Started	Sep 11 01:38:44 AM UTC 24
Finished	Sep 11 01:46:58 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234854514 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.234854514
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/29.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.4275513670
Short name	T48
Test name
Test status
Simulation time	475369304462 ps
CPU time	217.41 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 01:31:56 AM UTC 24
Peak memory	199484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275513670 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.4275513670
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3538636608
Short name	T392
Test name
Test status
Simulation time	637565463739 ps
CPU time	368.95 seconds
Started	Sep 11 01:28:15 AM UTC 24
Finished	Sep 11 01:34:29 AM UTC 24
Peak memory	199672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538636608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3538636608
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.3292462493
Short name	T13
Test name
Test status
Simulation time	8181161134 ps
CPU time	12.68 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 01:28:29 AM UTC 24
Peak memory	199452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292462493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3292462493
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3180808430
Short name	T342
Test name
Test status
Simulation time	1415024298832 ps
CPU time	3850.38 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 02:33:07 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180808430 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.3180808430
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/3.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.3037630211
Short name	T413
Test name
Test status
Simulation time	726337295219 ps
CPU time	417 seconds
Started	Sep 11 01:38:57 AM UTC 24
Finished	Sep 11 01:45:59 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037630211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3037630211
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.1581356413
Short name	T129
Test name
Test status
Simulation time	81900053457 ps
CPU time	160.17 seconds
Started	Sep 11 01:38:47 AM UTC 24
Finished	Sep 11 01:41:30 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581356413 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1581356413
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.821855098
Short name	T194
Test name
Test status
Simulation time	114049789460 ps
CPU time	284.07 seconds
Started	Sep 11 01:39:00 AM UTC 24
Finished	Sep 11 01:43:48 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821855098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.821855098
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.3798290121
Short name	T56
Test name
Test status
Simulation time	202509856448 ps
CPU time	221.82 seconds
Started	Sep 11 01:39:12 AM UTC 24
Finished	Sep 11 01:42:57 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798290121 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.3798290121
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/30.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.2778715885
Short name	T348
Test name
Test status
Simulation time	638424209130 ps
CPU time	579.63 seconds
Started	Sep 11 01:39:27 AM UTC 24
Finished	Sep 11 01:49:14 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778715885 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2778715885
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2601217970
Short name	T270
Test name
Test status
Simulation time	344837662125 ps
CPU time	227.97 seconds
Started	Sep 11 01:39:20 AM UTC 24
Finished	Sep 11 01:43:12 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601217970 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2601217970
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/31.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.4244686380
Short name	T373
Test name
Test status
Simulation time	197223303478 ps
CPU time	1200.11 seconds
Started	Sep 11 01:39:30 AM UTC 24
Finished	Sep 11 01:59:44 AM UTC 24
Peak memory	202416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244686380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4244686380
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/31.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.1806716892
Short name	T245
Test name
Test status
Simulation time	1293707606961 ps
CPU time	862.18 seconds
Started	Sep 11 01:39:50 AM UTC 24
Finished	Sep 11 01:54:22 AM UTC 24
Peak memory	202332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806716892 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1806716892
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.3274607698
Short name	T410
Test name
Test status
Simulation time	99793958127 ps
CPU time	236.25 seconds
Started	Sep 11 01:39:42 AM UTC 24
Finished	Sep 11 01:43:41 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274607698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3274607698
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.1530640021
Short name	T228
Test name
Test status
Simulation time	138225220522 ps
CPU time	808.75 seconds
Started	Sep 11 01:40:34 AM UTC 24
Finished	Sep 11 01:54:12 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530640021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1530640021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.2776313150
Short name	T28
Test name
Test status
Simulation time	1518405933 ps
CPU time	27.74 seconds
Started	Sep 11 01:40:45 AM UTC 24
Finished	Sep 11 01:41:14 AM UTC 24
Peak memory	203816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2776313150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.rv_timer_stress_all_with_rand_reset.2776313150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1298734561
Short name	T225
Test name
Test status
Simulation time	221016088876 ps
CPU time	217.11 seconds
Started	Sep 11 01:41:07 AM UTC 24
Finished	Sep 11 01:44:47 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298734561 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1298734561
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.3207260611
Short name	T108
Test name
Test status
Simulation time	482601162412 ps
CPU time	356.09 seconds
Started	Sep 11 01:40:56 AM UTC 24
Finished	Sep 11 01:46:57 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207260611 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3207260611
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/33.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3912955468
Short name	T119
Test name
Test status
Simulation time	650031861851 ps
CPU time	332.38 seconds
Started	Sep 11 01:41:10 AM UTC 24
Finished	Sep 11 01:46:47 AM UTC 24
Peak memory	199844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912955468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3912955468
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/33.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.976086699
Short name	T171
Test name
Test status
Simulation time	534997606367 ps
CPU time	511.8 seconds
Started	Sep 11 01:41:15 AM UTC 24
Finished	Sep 11 01:49:54 AM UTC 24
Peak memory	199640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976086699 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.976086699
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/33.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.2240112697
Short name	T293
Test name
Test status
Simulation time	1695887920429 ps
CPU time	1002.44 seconds
Started	Sep 11 01:41:31 AM UTC 24
Finished	Sep 11 01:58:24 AM UTC 24
Peak memory	202332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240112697 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.2240112697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.619313276
Short name	T408
Test name
Test status
Simulation time	136364879832 ps
CPU time	45.15 seconds
Started	Sep 11 01:41:26 AM UTC 24
Finished	Sep 11 01:42:12 AM UTC 24
Peak memory	199872 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619313276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.619313276
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.2353869186
Short name	T174
Test name
Test status
Simulation time	127599651398 ps
CPU time	709.41 seconds
Started	Sep 11 01:41:15 AM UTC 24
Finished	Sep 11 01:53:12 AM UTC 24
Peak memory	199896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353869186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2353869186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.2783483038
Short name	T406
Test name
Test status
Simulation time	299207071 ps
CPU time	1.09 seconds
Started	Sep 11 01:41:37 AM UTC 24
Finished	Sep 11 01:41:39 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783483038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2783483038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.3850729777
Short name	T145
Test name
Test status
Simulation time	720985806630 ps
CPU time	425.15 seconds
Started	Sep 11 01:41:42 AM UTC 24
Finished	Sep 11 01:48:53 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850729777 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.3850729777
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.3482881663
Short name	T29
Test name
Test status
Simulation time	21760011722 ps
CPU time	64.42 seconds
Started	Sep 11 01:41:40 AM UTC 24
Finished	Sep 11 01:42:46 AM UTC 24
Peak memory	203880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3482881663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.rv_timer_stress_all_with_rand_reset.3482881663
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.865381989
Short name	T412
Test name
Test status
Simulation time	85280920552 ps
CPU time	189.04 seconds
Started	Sep 11 01:41:49 AM UTC 24
Finished	Sep 11 01:45:01 AM UTC 24
Peak memory	199808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865381989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.865381989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.1841032606
Short name	T289
Test name
Test status
Simulation time	51173007393 ps
CPU time	106.17 seconds
Started	Sep 11 01:41:47 AM UTC 24
Finished	Sep 11 01:43:35 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841032606 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1841032606
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.808452857
Short name	T309
Test name
Test status
Simulation time	3518896021 ps
CPU time	10.4 seconds
Started	Sep 11 01:42:13 AM UTC 24
Finished	Sep 11 01:42:25 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808452857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.808452857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/35.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.3951190986
Short name	T304
Test name
Test status
Simulation time	483640935555 ps
CPU time	482.6 seconds
Started	Sep 11 01:42:33 AM UTC 24
Finished	Sep 11 01:50:42 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951190986 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3951190986
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3528636479
Short name	T414
Test name
Test status
Simulation time	258699105171 ps
CPU time	226.45 seconds
Started	Sep 11 01:42:32 AM UTC 24
Finished	Sep 11 01:46:21 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528636479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3528636479
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3515833516
Short name	T319
Test name
Test status
Simulation time	95063396125 ps
CPU time	259.85 seconds
Started	Sep 11 01:42:26 AM UTC 24
Finished	Sep 11 01:46:49 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515833516 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3515833516
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.47875256
Short name	T442
Test name
Test status
Simulation time	140701603475 ps
CPU time	1693.96 seconds
Started	Sep 11 01:42:38 AM UTC 24
Finished	Sep 11 02:11:11 AM UTC 24
Peak memory	202416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47875256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.47875256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all_with_rand_reset.634822056
Short name	T30
Test name
Test status
Simulation time	13457873798 ps
CPU time	24.51 seconds
Started	Sep 11 01:42:47 AM UTC 24
Finished	Sep 11 01:43:13 AM UTC 24
Peak memory	204124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=634822056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.634822056
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/36.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.3652414547
Short name	T419
Test name
Test status
Simulation time	143187585581 ps
CPU time	295.82 seconds
Started	Sep 11 01:43:13 AM UTC 24
Finished	Sep 11 01:48:13 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652414547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3652414547
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.437252490
Short name	T409
Test name
Test status
Simulation time	779829768 ps
CPU time	1 seconds
Started	Sep 11 01:43:36 AM UTC 24
Finished	Sep 11 01:43:38 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437252490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.437252490
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.2062142674
Short name	T349
Test name
Test status
Simulation time	68219561670 ps
CPU time	72.31 seconds
Started	Sep 11 01:43:43 AM UTC 24
Finished	Sep 11 01:44:56 AM UTC 24
Peak memory	199452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062142674 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.2062142674
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all_with_rand_reset.3940072832
Short name	T31
Test name
Test status
Simulation time	520064793 ps
CPU time	6.14 seconds
Started	Sep 11 01:43:39 AM UTC 24
Finished	Sep 11 01:43:47 AM UTC 24
Peak memory	201844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3940072832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.rv_timer_stress_all_with_rand_reset.3940072832
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.4100367282
Short name	T242
Test name
Test status
Simulation time	5109407747881 ps
CPU time	1462.31 seconds
Started	Sep 11 01:43:49 AM UTC 24
Finished	Sep 11 02:08:27 AM UTC 24
Peak memory	202460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100367282 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.4100367282
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.3810869988
Short name	T418
Test name
Test status
Simulation time	73930091803 ps
CPU time	237.14 seconds
Started	Sep 11 01:43:48 AM UTC 24
Finished	Sep 11 01:47:48 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810869988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3810869988
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2404330742
Short name	T153
Test name
Test status
Simulation time	61596527694 ps
CPU time	191.13 seconds
Started	Sep 11 01:43:44 AM UTC 24
Finished	Sep 11 01:46:58 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404330742 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2404330742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.3314661855
Short name	T327
Test name
Test status
Simulation time	31079146931 ps
CPU time	149.98 seconds
Started	Sep 11 01:43:52 AM UTC 24
Finished	Sep 11 01:46:24 AM UTC 24
Peak memory	199780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314661855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3314661855
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all_with_rand_reset.50034589
Short name	T32
Test name
Test status
Simulation time	4190212323 ps
CPU time	20.63 seconds
Started	Sep 11 01:44:16 AM UTC 24
Finished	Sep 11 01:44:38 AM UTC 24
Peak memory	202012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=50034589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.50034589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/38.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.1176607233
Short name	T372
Test name
Test status
Simulation time	7922225187360 ps
CPU time	2510.31 seconds
Started	Sep 11 01:44:38 AM UTC 24
Finished	Sep 11 02:26:58 AM UTC 24
Peak memory	202412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176607233 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.1176607233
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.4013225066
Short name	T416
Test name
Test status
Simulation time	252434590417 ps
CPU time	185.44 seconds
Started	Sep 11 01:44:29 AM UTC 24
Finished	Sep 11 01:47:37 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013225066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4013225066
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.1140903384
Short name	T411
Test name
Test status
Simulation time	994341552 ps
CPU time	0.98 seconds
Started	Sep 11 01:44:38 AM UTC 24
Finished	Sep 11 01:44:40 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140903384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1140903384
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3453685185
Short name	T244
Test name
Test status
Simulation time	457704628498 ps
CPU time	502.98 seconds
Started	Sep 11 01:44:44 AM UTC 24
Finished	Sep 11 01:53:14 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453685185 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.3453685185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/39.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3636237331
Short name	T109
Test name
Test status
Simulation time	172949134416 ps
CPU time	447.68 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:35:50 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636237331 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3636237331
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.628170438
Short name	T378
Test name
Test status
Simulation time	383876794516 ps
CPU time	105.34 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 01:30:03 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628170438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.628170438
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.743627330
Short name	T178
Test name
Test status
Simulation time	144527715580 ps
CPU time	1743.9 seconds
Started	Sep 11 01:28:16 AM UTC 24
Finished	Sep 11 01:57:39 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743627330 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.743627330
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.4081514044
Short name	T35
Test name
Test status
Simulation time	183064549117 ps
CPU time	81.13 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:29:40 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081514044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4081514044
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.742606434
Short name	T7
Test name
Test status
Simulation time	99344509 ps
CPU time	0.84 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:28:19 AM UTC 24
Peak memory	230920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742606434 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.742606434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.778563137
Short name	T387
Test name
Test status
Simulation time	160010712142 ps
CPU time	266.73 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:32:47 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778563137 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.778563137
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.207071103
Short name	T326
Test name
Test status
Simulation time	1632464188110 ps
CPU time	1122.54 seconds
Started	Sep 11 01:44:59 AM UTC 24
Finished	Sep 11 02:03:54 AM UTC 24
Peak memory	202440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207071103 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.207071103
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.2089528913
Short name	T423
Test name
Test status
Simulation time	158877904159 ps
CPU time	269.47 seconds
Started	Sep 11 01:44:58 AM UTC 24
Finished	Sep 11 01:49:31 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089528913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2089528913
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.123032989
Short name	T163
Test name
Test status
Simulation time	627346244780 ps
CPU time	374.43 seconds
Started	Sep 11 01:44:49 AM UTC 24
Finished	Sep 11 01:51:08 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123032989 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.123032989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1984954324
Short name	T370
Test name
Test status
Simulation time	68346690872 ps
CPU time	42.44 seconds
Started	Sep 11 01:45:02 AM UTC 24
Finished	Sep 11 01:45:46 AM UTC 24
Peak memory	199844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984954324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1984954324
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.1738739165
Short name	T434
Test name
Test status
Simulation time	315404587197 ps
CPU time	476.19 seconds
Started	Sep 11 01:45:16 AM UTC 24
Finished	Sep 11 01:53:17 AM UTC 24
Peak memory	199604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738739165 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.1738739165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/40.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.4108434524
Short name	T114
Test name
Test status
Simulation time	219228622393 ps
CPU time	96.92 seconds
Started	Sep 11 01:46:00 AM UTC 24
Finished	Sep 11 01:47:40 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108434524 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.4108434524
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.1797531165
Short name	T415
Test name
Test status
Simulation time	54833789281 ps
CPU time	105.06 seconds
Started	Sep 11 01:45:46 AM UTC 24
Finished	Sep 11 01:47:33 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797531165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1797531165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.4194794949
Short name	T299
Test name
Test status
Simulation time	55528809919 ps
CPU time	174.47 seconds
Started	Sep 11 01:45:40 AM UTC 24
Finished	Sep 11 01:48:37 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194794949 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4194794949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.4254620643
Short name	T359
Test name
Test status
Simulation time	92420571605 ps
CPU time	172.81 seconds
Started	Sep 11 01:46:02 AM UTC 24
Finished	Sep 11 01:48:58 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254620643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4254620643
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.3520570840
Short name	T207
Test name
Test status
Simulation time	1277018040751 ps
CPU time	1669.75 seconds
Started	Sep 11 01:46:25 AM UTC 24
Finished	Sep 11 02:14:32 AM UTC 24
Peak memory	202584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520570840 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.3520570840
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all_with_rand_reset.1796363888
Short name	T37
Test name
Test status
Simulation time	17724259385 ps
CPU time	31.52 seconds
Started	Sep 11 01:46:22 AM UTC 24
Finished	Sep 11 01:46:55 AM UTC 24
Peak memory	205964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1796363888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.rv_timer_stress_all_with_rand_reset.1796363888
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/41.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3916459912
Short name	T306
Test name
Test status
Simulation time	397340241188 ps
CPU time	559.49 seconds
Started	Sep 11 01:46:51 AM UTC 24
Finished	Sep 11 01:56:17 AM UTC 24
Peak memory	199720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916459912 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3916459912
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.4113891109
Short name	T429
Test name
Test status
Simulation time	698654718520 ps
CPU time	273.6 seconds
Started	Sep 11 01:46:49 AM UTC 24
Finished	Sep 11 01:51:26 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113891109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4113891109
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.108871869
Short name	T250
Test name
Test status
Simulation time	445904000427 ps
CPU time	767.79 seconds
Started	Sep 11 01:46:49 AM UTC 24
Finished	Sep 11 01:59:45 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108871869 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.108871869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.3422135758
Short name	T329
Test name
Test status
Simulation time	156540267861 ps
CPU time	123.07 seconds
Started	Sep 11 01:46:56 AM UTC 24
Finished	Sep 11 01:49:01 AM UTC 24
Peak memory	199612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422135758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3422135758
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/42.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.4188118229
Short name	T221
Test name
Test status
Simulation time	1049807315784 ps
CPU time	601.02 seconds
Started	Sep 11 01:47:17 AM UTC 24
Finished	Sep 11 01:57:25 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188118229 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.4188118229
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.2333408617
Short name	T426
Test name
Test status
Simulation time	442678535698 ps
CPU time	162.57 seconds
Started	Sep 11 01:47:15 AM UTC 24
Finished	Sep 11 01:50:00 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333408617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2333408617
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.4279147158
Short name	T339
Test name
Test status
Simulation time	9891028892 ps
CPU time	31.98 seconds
Started	Sep 11 01:47:29 AM UTC 24
Finished	Sep 11 01:48:02 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279147158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4279147158
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2216456362
Short name	T417
Test name
Test status
Simulation time	17111951 ps
CPU time	0.82 seconds
Started	Sep 11 01:47:38 AM UTC 24
Finished	Sep 11 01:47:41 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216456362 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.2216456362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/43.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.2731185597
Short name	T200
Test name
Test status
Simulation time	1168122856270 ps
CPU time	808.23 seconds
Started	Sep 11 01:47:50 AM UTC 24
Finished	Sep 11 02:01:27 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731185597 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.2731185597
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3490575072
Short name	T421
Test name
Test status
Simulation time	22550384802 ps
CPU time	49.66 seconds
Started	Sep 11 01:47:41 AM UTC 24
Finished	Sep 11 01:48:33 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490575072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3490575072
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.204497342
Short name	T243
Test name
Test status
Simulation time	67254775726 ps
CPU time	168.7 seconds
Started	Sep 11 01:47:40 AM UTC 24
Finished	Sep 11 01:50:32 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204497342 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.204497342
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2613346040
Short name	T422
Test name
Test status
Simulation time	18531271195 ps
CPU time	74.13 seconds
Started	Sep 11 01:47:53 AM UTC 24
Finished	Sep 11 01:49:09 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613346040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2613346040
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.3399942763
Short name	T435
Test name
Test status
Simulation time	225428817855 ps
CPU time	398.7 seconds
Started	Sep 11 01:48:03 AM UTC 24
Finished	Sep 11 01:54:46 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399942763 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.3399942763
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.1909010949
Short name	T420
Test name
Test status
Simulation time	2341127331 ps
CPU time	27.12 seconds
Started	Sep 11 01:48:03 AM UTC 24
Finished	Sep 11 01:48:31 AM UTC 24
Peak memory	204016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1909010949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.rv_timer_stress_all_with_rand_reset.1909010949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.280640220
Short name	T437
Test name
Test status
Simulation time	801180551528 ps
CPU time	447.05 seconds
Started	Sep 11 01:48:32 AM UTC 24
Finished	Sep 11 01:56:05 AM UTC 24
Peak memory	199584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280640220 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.280640220
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.2239432821
Short name	T425
Test name
Test status
Simulation time	78606330627 ps
CPU time	71.84 seconds
Started	Sep 11 01:48:25 AM UTC 24
Finished	Sep 11 01:49:39 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239432821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2239432821
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.3095065610
Short name	T269
Test name
Test status
Simulation time	128944559102 ps
CPU time	371.22 seconds
Started	Sep 11 01:48:14 AM UTC 24
Finished	Sep 11 01:54:30 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095065610 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3095065610
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.492047542
Short name	T305
Test name
Test status
Simulation time	47051129625 ps
CPU time	435.55 seconds
Started	Sep 11 01:48:34 AM UTC 24
Finished	Sep 11 01:55:55 AM UTC 24
Peak memory	199900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492047542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.492047542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/45.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.1810724027
Short name	T231
Test name
Test status
Simulation time	1399246225445 ps
CPU time	1057.41 seconds
Started	Sep 11 01:48:59 AM UTC 24
Finished	Sep 11 02:06:48 AM UTC 24
Peak memory	202524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810724027 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1810724027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.4042557148
Short name	T427
Test name
Test status
Simulation time	139317107738 ps
CPU time	117.8 seconds
Started	Sep 11 01:48:53 AM UTC 24
Finished	Sep 11 01:50:53 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042557148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4042557148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.2521016820
Short name	T230
Test name
Test status
Simulation time	110192604094 ps
CPU time	360.24 seconds
Started	Sep 11 01:48:49 AM UTC 24
Finished	Sep 11 01:54:54 AM UTC 24
Peak memory	199900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521016820 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2521016820
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.292436936
Short name	T254
Test name
Test status
Simulation time	215586497219 ps
CPU time	159.77 seconds
Started	Sep 11 01:49:02 AM UTC 24
Finished	Sep 11 01:51:44 AM UTC 24
Peak memory	199524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292436936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.292436936
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1339323619
Short name	T436
Test name
Test status
Simulation time	1155149030971 ps
CPU time	392.27 seconds
Started	Sep 11 01:49:10 AM UTC 24
Finished	Sep 11 01:55:47 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339323619 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1339323619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/46.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.3198744514
Short name	T246
Test name
Test status
Simulation time	23578064710 ps
CPU time	72.63 seconds
Started	Sep 11 01:49:14 AM UTC 24
Finished	Sep 11 01:50:28 AM UTC 24
Peak memory	199776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198744514 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3198744514
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.3969629537
Short name	T432
Test name
Test status
Simulation time	45363786596 ps
CPU time	137.78 seconds
Started	Sep 11 01:49:14 AM UTC 24
Finished	Sep 11 01:51:34 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969629537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3969629537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3351226991
Short name	T204
Test name
Test status
Simulation time	500932233687 ps
CPU time	293.06 seconds
Started	Sep 11 01:49:10 AM UTC 24
Finished	Sep 11 01:54:07 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351226991 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3351226991
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.3382192336
Short name	T424
Test name
Test status
Simulation time	95791596 ps
CPU time	1 seconds
Started	Sep 11 01:49:31 AM UTC 24
Finished	Sep 11 01:49:33 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382192336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3382192336
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/47.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.2878155217
Short name	T287
Test name
Test status
Simulation time	5847778639 ps
CPU time	6.49 seconds
Started	Sep 11 01:50:00 AM UTC 24
Finished	Sep 11 01:50:08 AM UTC 24
Peak memory	199608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878155217 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.2878155217
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.2453283709
Short name	T433
Test name
Test status
Simulation time	167192268971 ps
CPU time	109.64 seconds
Started	Sep 11 01:49:54 AM UTC 24
Finished	Sep 11 01:51:46 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453283709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2453283709
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.1678949347
Short name	T446
Test name
Test status
Simulation time	139188865864 ps
CPU time	2261.01 seconds
Started	Sep 11 01:49:39 AM UTC 24
Finished	Sep 11 02:27:46 AM UTC 24
Peak memory	202420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678949347 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1678949347
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.609474638
Short name	T365
Test name
Test status
Simulation time	147219051308 ps
CPU time	1281.03 seconds
Started	Sep 11 01:50:10 AM UTC 24
Finished	Sep 11 02:11:44 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609474638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.609474638
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.1217419456
Short name	T187
Test name
Test status
Simulation time	659460074301 ps
CPU time	1276.19 seconds
Started	Sep 11 01:50:29 AM UTC 24
Finished	Sep 11 02:11:58 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217419456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.1217419456
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/48.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.887015453
Short name	T210
Test name
Test status
Simulation time	321807164120 ps
CPU time	174.5 seconds
Started	Sep 11 01:50:42 AM UTC 24
Finished	Sep 11 01:53:39 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887015453 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.887015453
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.1363293580
Short name	T428
Test name
Test status
Simulation time	62216786863 ps
CPU time	38.8 seconds
Started	Sep 11 01:50:36 AM UTC 24
Finished	Sep 11 01:51:16 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363293580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1363293580
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2796295817
Short name	T220
Test name
Test status
Simulation time	213737485058 ps
CPU time	371.99 seconds
Started	Sep 11 01:50:33 AM UTC 24
Finished	Sep 11 01:56:50 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796295817 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2796295817
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.3581140194
Short name	T430
Test name
Test status
Simulation time	7825714273 ps
CPU time	32.21 seconds
Started	Sep 11 01:50:54 AM UTC 24
Finished	Sep 11 01:51:28 AM UTC 24
Peak memory	199704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581140194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3581140194
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1876093513
Short name	T218
Test name
Test status
Simulation time	492949962441 ps
CPU time	383.06 seconds
Started	Sep 11 01:51:09 AM UTC 24
Finished	Sep 11 01:57:37 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876093513 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1876093513
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all_with_rand_reset.58358252
Short name	T431
Test name
Test status
Simulation time	1649213161 ps
CPU time	30.87 seconds
Started	Sep 11 01:50:59 AM UTC 24
Finished	Sep 11 01:51:31 AM UTC 24
Peak memory	203932 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=58358252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.58358252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/49.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.2963199609
Short name	T113
Test name
Test status
Simulation time	1486482505526 ps
CPU time	802.36 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:41:48 AM UTC 24
Peak memory	202588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963199609 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.2963199609
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.1719075757
Short name	T379
Test name
Test status
Simulation time	131162414660 ps
CPU time	113.36 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:30:13 AM UTC 24
Peak memory	199804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719075757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1719075757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/5.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.3186992508
Short name	T311
Test name
Test status
Simulation time	45778017355 ps
CPU time	102.46 seconds
Started	Sep 11 01:51:17 AM UTC 24
Finished	Sep 11 01:53:02 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186992508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3186992508
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/50.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.1536841665
Short name	T301
Test name
Test status
Simulation time	219164048850 ps
CPU time	922.41 seconds
Started	Sep 11 01:51:26 AM UTC 24
Finished	Sep 11 02:06:59 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536841665 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1536841665
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/51.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.1990591945
Short name	T275
Test name
Test status
Simulation time	101282630782 ps
CPU time	218.56 seconds
Started	Sep 11 01:51:28 AM UTC 24
Finished	Sep 11 01:55:10 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990591945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1990591945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/52.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3578835723
Short name	T219
Test name
Test status
Simulation time	232472434599 ps
CPU time	665.38 seconds
Started	Sep 11 01:51:33 AM UTC 24
Finished	Sep 11 02:02:46 AM UTC 24
Peak memory	199692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578835723 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3578835723
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/53.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.671475787
Short name	T158
Test name
Test status
Simulation time	129365425382 ps
CPU time	120.49 seconds
Started	Sep 11 01:51:35 AM UTC 24
Finished	Sep 11 01:53:38 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671475787 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.671475787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/54.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.4091024437
Short name	T310
Test name
Test status
Simulation time	53865705261 ps
CPU time	93.14 seconds
Started	Sep 11 01:51:45 AM UTC 24
Finished	Sep 11 01:53:20 AM UTC 24
Peak memory	199600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091024437 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4091024437
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/55.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.2429437355
Short name	T334
Test name
Test status
Simulation time	159205088933 ps
CPU time	337.78 seconds
Started	Sep 11 01:51:48 AM UTC 24
Finished	Sep 11 01:57:30 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429437355 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2429437355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/56.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2236956893
Short name	T292
Test name
Test status
Simulation time	294855335949 ps
CPU time	179.06 seconds
Started	Sep 11 01:51:58 AM UTC 24
Finished	Sep 11 01:55:00 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236956893 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2236956893
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/57.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3411853919
Short name	T277
Test name
Test status
Simulation time	69218204011 ps
CPU time	228.06 seconds
Started	Sep 11 01:52:17 AM UTC 24
Finished	Sep 11 01:56:08 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411853919 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3411853919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/58.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.2587931903
Short name	T227
Test name
Test status
Simulation time	79570333656 ps
CPU time	204.61 seconds
Started	Sep 11 01:53:02 AM UTC 24
Finished	Sep 11 01:56:30 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587931903 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2587931903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/59.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.409254639
Short name	T89
Test name
Test status
Simulation time	743284074315 ps
CPU time	318.31 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:33:40 AM UTC 24
Peak memory	199780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409254639 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.409254639
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.3433068827
Short name	T386
Test name
Test status
Simulation time	175844518051 ps
CPU time	254.87 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:32:35 AM UTC 24
Peak memory	199080 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433068827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3433068827
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3533618188
Short name	T96
Test name
Test status
Simulation time	72470906255 ps
CPU time	152.29 seconds
Started	Sep 11 01:28:17 AM UTC 24
Finished	Sep 11 01:30:52 AM UTC 24
Peak memory	199776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533618188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3533618188
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1806436041
Short name	T9
Test name
Test status
Simulation time	79346946 ps
CPU time	0.76 seconds
Started	Sep 11 01:28:18 AM UTC 24
Finished	Sep 11 01:28:20 AM UTC 24
Peak memory	198868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806436041 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1806436041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/6.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.3816806210
Short name	T229
Test name
Test status
Simulation time	148618931579 ps
CPU time	868.52 seconds
Started	Sep 11 01:53:03 AM UTC 24
Finished	Sep 11 02:07:40 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816806210 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3816806210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/60.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.4027683324
Short name	T197
Test name
Test status
Simulation time	17494996787 ps
CPU time	54.97 seconds
Started	Sep 11 01:53:14 AM UTC 24
Finished	Sep 11 01:54:10 AM UTC 24
Peak memory	199772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027683324 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4027683324
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/61.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2404942028
Short name	T223
Test name
Test status
Simulation time	1365293096483 ps
CPU time	484.84 seconds
Started	Sep 11 01:53:15 AM UTC 24
Finished	Sep 11 02:01:26 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404942028 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2404942028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/62.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.2094927421
Short name	T265
Test name
Test status
Simulation time	44220514599 ps
CPU time	107.51 seconds
Started	Sep 11 01:53:18 AM UTC 24
Finished	Sep 11 01:55:07 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094927421 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2094927421
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/63.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3211090892
Short name	T149
Test name
Test status
Simulation time	30087487692 ps
CPU time	235.84 seconds
Started	Sep 11 01:53:21 AM UTC 24
Finished	Sep 11 01:57:20 AM UTC 24
Peak memory	199668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211090892 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3211090892
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/64.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.343029644
Short name	T159
Test name
Test status
Simulation time	131769917146 ps
CPU time	248.19 seconds
Started	Sep 11 01:53:38 AM UTC 24
Finished	Sep 11 01:57:50 AM UTC 24
Peak memory	199676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343029644 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.343029644
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/65.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1578148715
Short name	T249
Test name
Test status
Simulation time	36197046125 ps
CPU time	144.97 seconds
Started	Sep 11 01:53:39 AM UTC 24
Finished	Sep 11 01:56:06 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578148715 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1578148715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/66.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1955820918
Short name	T166
Test name
Test status
Simulation time	1656678450271 ps
CPU time	1305.21 seconds
Started	Sep 11 01:53:40 AM UTC 24
Finished	Sep 11 02:15:39 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955820918 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1955820918
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/67.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.86473361
Short name	T212
Test name
Test status
Simulation time	144308227058 ps
CPU time	348.41 seconds
Started	Sep 11 01:54:07 AM UTC 24
Finished	Sep 11 02:00:00 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86473361 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.86473361
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/68.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.4182199447
Short name	T117
Test name
Test status
Simulation time	836645638960 ps
CPU time	454.33 seconds
Started	Sep 11 01:28:19 AM UTC 24
Finished	Sep 11 01:35:58 AM UTC 24
Peak memory	199720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182199447 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.4182199447
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.958778886
Short name	T44
Test name
Test status
Simulation time	257077831047 ps
CPU time	194.94 seconds
Started	Sep 11 01:28:18 AM UTC 24
Finished	Sep 11 01:31:36 AM UTC 24
Peak memory	199808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958778886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.958778886
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1091177857
Short name	T137
Test name
Test status
Simulation time	148125240994 ps
CPU time	126.02 seconds
Started	Sep 11 01:28:18 AM UTC 24
Finished	Sep 11 01:30:27 AM UTC 24
Peak memory	199836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091177857 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1091177857
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.1692429960
Short name	T14
Test name
Test status
Simulation time	21603737652 ps
CPU time	34.28 seconds
Started	Sep 11 01:28:19 AM UTC 24
Finished	Sep 11 01:28:54 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692429960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1692429960
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.395715395
Short name	T121
Test name
Test status
Simulation time	1500538624331 ps
CPU time	682.67 seconds
Started	Sep 11 01:28:19 AM UTC 24
Finished	Sep 11 01:39:49 AM UTC 24
Peak memory	202348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395715395 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.395715395
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/7.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.1699917435
Short name	T184
Test name
Test status
Simulation time	15451255336 ps
CPU time	12.85 seconds
Started	Sep 11 01:54:12 AM UTC 24
Finished	Sep 11 01:54:26 AM UTC 24
Peak memory	199456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699917435 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1699917435
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/70.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.4023196451
Short name	T257
Test name
Test status
Simulation time	73338231139 ps
CPU time	154.91 seconds
Started	Sep 11 01:54:22 AM UTC 24
Finished	Sep 11 01:57:00 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023196451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.4023196451
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/71.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2759428936
Short name	T282
Test name
Test status
Simulation time	1079855720453 ps
CPU time	799.65 seconds
Started	Sep 11 01:54:27 AM UTC 24
Finished	Sep 11 02:07:57 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759428936 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2759428936
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/72.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3306808869
Short name	T280
Test name
Test status
Simulation time	127749124078 ps
CPU time	475.93 seconds
Started	Sep 11 01:54:31 AM UTC 24
Finished	Sep 11 02:02:33 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306808869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3306808869
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/73.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.2087247118
Short name	T235
Test name
Test status
Simulation time	204639054917 ps
CPU time	1045.97 seconds
Started	Sep 11 01:54:34 AM UTC 24
Finished	Sep 11 02:12:11 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087247118 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2087247118
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/74.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1701380823
Short name	T286
Test name
Test status
Simulation time	274363619075 ps
CPU time	142.27 seconds
Started	Sep 11 01:54:47 AM UTC 24
Finished	Sep 11 01:57:11 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701380823 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1701380823
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/75.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.4025003657
Short name	T181
Test name
Test status
Simulation time	165556185733 ps
CPU time	525.32 seconds
Started	Sep 11 01:54:55 AM UTC 24
Finished	Sep 11 02:03:47 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025003657 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4025003657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/76.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.4209153140
Short name	T267
Test name
Test status
Simulation time	844896538275 ps
CPU time	438.77 seconds
Started	Sep 11 01:55:01 AM UTC 24
Finished	Sep 11 02:02:25 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209153140 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4209153140
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/77.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2367394882
Short name	T302
Test name
Test status
Simulation time	365154602225 ps
CPU time	799.12 seconds
Started	Sep 11 01:55:08 AM UTC 24
Finished	Sep 11 02:08:37 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367394882 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2367394882
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/78.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.3040386766
Short name	T239
Test name
Test status
Simulation time	161446975550 ps
CPU time	448.38 seconds
Started	Sep 11 01:55:11 AM UTC 24
Finished	Sep 11 02:02:45 AM UTC 24
Peak memory	199768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040386766 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3040386766
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/79.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.2237540323
Short name	T313
Test name
Test status
Simulation time	1467592115859 ps
CPU time	954.5 seconds
Started	Sep 11 01:28:20 AM UTC 24
Finished	Sep 11 01:44:25 AM UTC 24
Peak memory	202332 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237540323 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.2237540323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.2888014489
Short name	T380
Test name
Test status
Simulation time	981937498915 ps
CPU time	114.45 seconds
Started	Sep 11 01:28:19 AM UTC 24
Finished	Sep 11 01:30:15 AM UTC 24
Peak memory	199840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888014489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2888014489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.3590043784
Short name	T120
Test name
Test status
Simulation time	636686296953 ps
CPU time	1096.11 seconds
Started	Sep 11 01:28:19 AM UTC 24
Finished	Sep 11 01:46:48 AM UTC 24
Peak memory	202488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590043784 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3590043784
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3275214015
Short name	T15
Test name
Test status
Simulation time	48646552616 ps
CPU time	72.41 seconds
Started	Sep 11 01:28:20 AM UTC 24
Finished	Sep 11 01:29:34 AM UTC 24
Peak memory	199840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275214015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3275214015
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/8.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.3861907650
Short name	T169
Test name
Test status
Simulation time	194355716106 ps
CPU time	62.08 seconds
Started	Sep 11 01:55:29 AM UTC 24
Finished	Sep 11 01:56:33 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861907650 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3861907650
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/80.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.2758920078
Short name	T164
Test name
Test status
Simulation time	111747304403 ps
CPU time	830.76 seconds
Started	Sep 11 01:55:56 AM UTC 24
Finished	Sep 11 02:09:57 AM UTC 24
Peak memory	202612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758920078 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2758920078
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/82.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.1650344553
Short name	T156
Test name
Test status
Simulation time	5334083034 ps
CPU time	2.98 seconds
Started	Sep 11 01:56:06 AM UTC 24
Finished	Sep 11 01:56:10 AM UTC 24
Peak memory	199444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650344553 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1650344553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/83.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.4174862989
Short name	T180
Test name
Test status
Simulation time	211768529740 ps
CPU time	188.23 seconds
Started	Sep 11 01:56:07 AM UTC 24
Finished	Sep 11 01:59:18 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174862989 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4174862989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/84.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.3654953443
Short name	T179
Test name
Test status
Simulation time	412371291672 ps
CPU time	384.07 seconds
Started	Sep 11 01:56:10 AM UTC 24
Finished	Sep 11 02:02:38 AM UTC 24
Peak memory	199700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654953443 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3654953443
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/86.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.2450802320
Short name	T190
Test name
Test status
Simulation time	412152878152 ps
CPU time	523.5 seconds
Started	Sep 11 01:56:11 AM UTC 24
Finished	Sep 11 02:05:01 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450802320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2450802320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/87.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.1655362755
Short name	T281
Test name
Test status
Simulation time	390425537285 ps
CPU time	1231.81 seconds
Started	Sep 11 01:56:18 AM UTC 24
Finished	Sep 11 02:17:04 AM UTC 24
Peak memory	202448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655362755 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1655362755
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/88.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.3240906618
Short name	T172
Test name
Test status
Simulation time	31996606632 ps
CPU time	356.91 seconds
Started	Sep 11 01:56:31 AM UTC 24
Finished	Sep 11 02:02:33 AM UTC 24
Peak memory	199736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240906618 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3240906618
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/89.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.1059464331
Short name	T85
Test name
Test status
Simulation time	192243194627 ps
CPU time	96.07 seconds
Started	Sep 11 01:28:21 AM UTC 24
Finished	Sep 11 01:29:59 AM UTC 24
Peak memory	199656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059464331 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1059464331
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.4154729359
Short name	T23
Test name
Test status
Simulation time	57289205320 ps
CPU time	47.4 seconds
Started	Sep 11 01:28:20 AM UTC 24
Finished	Sep 11 01:29:09 AM UTC 24
Peak memory	199720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154729359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4154729359
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3455587830
Short name	T383
Test name
Test status
Simulation time	82372378493 ps
CPU time	167.62 seconds
Started	Sep 11 01:28:21 AM UTC 24
Finished	Sep 11 01:31:12 AM UTC 24
Peak memory	199708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455587830 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3455587830
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/9.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.4030940958
Short name	T176
Test name
Test status
Simulation time	59733871889 ps
CPU time	134.12 seconds
Started	Sep 11 01:56:34 AM UTC 24
Finished	Sep 11 01:58:50 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030940958 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4030940958
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/90.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.4243917878
Short name	T316
Test name
Test status
Simulation time	519158890625 ps
CPU time	381.68 seconds
Started	Sep 11 01:56:51 AM UTC 24
Finished	Sep 11 02:03:18 AM UTC 24
Peak memory	199696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243917878 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4243917878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/91.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3681863074
Short name	T340
Test name
Test status
Simulation time	186403822198 ps
CPU time	362.12 seconds
Started	Sep 11 01:57:01 AM UTC 24
Finished	Sep 11 02:03:09 AM UTC 24
Peak memory	199600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681863074 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3681863074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/92.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.831720955
Short name	T357
Test name
Test status
Simulation time	122287870358 ps
CPU time	2679.15 seconds
Started	Sep 11 01:57:09 AM UTC 24
Finished	Sep 11 02:42:20 AM UTC 24
Peak memory	202408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831720955 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.831720955
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/93.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2430934171
Short name	T361
Test name
Test status
Simulation time	224186865900 ps
CPU time	447.09 seconds
Started	Sep 11 01:57:12 AM UTC 24
Finished	Sep 11 02:04:45 AM UTC 24
Peak memory	199660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430934171 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2430934171
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/94.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.2895086770
Short name	T165
Test name
Test status
Simulation time	638739643677 ps
CPU time	823.7 seconds
Started	Sep 11 01:57:21 AM UTC 24
Finished	Sep 11 02:11:14 AM UTC 24
Peak memory	199864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895086770 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2895086770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/95.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.3100454925
Short name	T217
Test name
Test status
Simulation time	460876773666 ps
CPU time	588.26 seconds
Started	Sep 11 01:57:26 AM UTC 24
Finished	Sep 11 02:07:21 AM UTC 24
Peak memory	199800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100454925 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3100454925
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/96.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.3462037888
Short name	T338
Test name
Test status
Simulation time	48437921738 ps
CPU time	112.8 seconds
Started	Sep 11 01:57:31 AM UTC 24
Finished	Sep 11 01:59:26 AM UTC 24
Peak memory	199664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462037888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3462037888
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/97.rv_timer_random/latest