| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.71 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.89 |
| T506 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.665746872 | Sep 18 05:30:33 AM UTC 24 | Sep 18 05:30:35 AM UTC 24 | 13141225 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1283894555 | Sep 18 05:30:33 AM UTC 24 | Sep 18 05:30:35 AM UTC 24 | 15877039 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1265489263 | Sep 18 05:30:33 AM UTC 24 | Sep 18 05:30:35 AM UTC 24 | 88775647 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3919907945 | Sep 18 05:30:34 AM UTC 24 | Sep 18 05:30:36 AM UTC 24 | 153760924 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2215707172 | Sep 18 05:30:34 AM UTC 24 | Sep 18 05:30:36 AM UTC 24 | 160396452 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.88578128 | Sep 18 05:30:33 AM UTC 24 | Sep 18 05:30:36 AM UTC 24 | 140534824 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.4146813183 | Sep 18 05:30:33 AM UTC 24 | Sep 18 05:30:37 AM UTC 24 | 53722127 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1379896748 | Sep 18 05:30:36 AM UTC 24 | Sep 18 05:30:37 AM UTC 24 | 27624798 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.3836342931 | Sep 18 05:30:36 AM UTC 24 | Sep 18 05:30:37 AM UTC 24 | 19496797 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.486909676 | Sep 18 05:30:36 AM UTC 24 | Sep 18 05:30:38 AM UTC 24 | 170383670 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.213984116 | Sep 18 05:30:35 AM UTC 24 | Sep 18 05:30:38 AM UTC 24 | 112417281 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3069093933 | Sep 18 05:30:37 AM UTC 24 | Sep 18 05:30:39 AM UTC 24 | 197429750 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.748975770 | Sep 18 05:30:37 AM UTC 24 | Sep 18 05:30:39 AM UTC 24 | 174981870 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3890915374 | Sep 18 05:30:37 AM UTC 24 | Sep 18 05:30:40 AM UTC 24 | 116106038 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1281384060 | Sep 18 05:30:36 AM UTC 24 | Sep 18 05:30:40 AM UTC 24 | 384137696 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2669227592 | Sep 18 05:30:38 AM UTC 24 | Sep 18 05:30:40 AM UTC 24 | 218826794 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1362066909 | Sep 18 05:30:39 AM UTC 24 | Sep 18 05:30:40 AM UTC 24 | 14134593 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3486475343 | Sep 18 05:30:39 AM UTC 24 | Sep 18 05:30:41 AM UTC 24 | 109280771 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3832475442 | Sep 18 05:30:39 AM UTC 24 | Sep 18 05:30:41 AM UTC 24 | 22228991 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2720649720 | Sep 18 05:30:40 AM UTC 24 | Sep 18 05:30:42 AM UTC 24 | 12261920 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2256169807 | Sep 18 05:30:37 AM UTC 24 | Sep 18 05:30:42 AM UTC 24 | 364487416 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3841411534 | Sep 18 05:30:40 AM UTC 24 | Sep 18 05:30:43 AM UTC 24 | 101511570 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.665354473 | Sep 18 05:30:41 AM UTC 24 | Sep 18 05:30:43 AM UTC 24 | 53750976 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.840102154 | Sep 18 05:30:41 AM UTC 24 | Sep 18 05:30:43 AM UTC 24 | 44298442 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.677602210 | Sep 18 05:30:39 AM UTC 24 | Sep 18 05:30:43 AM UTC 24 | 134416257 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.2545283823 | Sep 18 05:30:42 AM UTC 24 | Sep 18 05:30:43 AM UTC 24 | 15147418 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.3915747767 | Sep 18 05:30:42 AM UTC 24 | Sep 18 05:30:44 AM UTC 24 | 29946235 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4099558813 | Sep 18 05:30:42 AM UTC 24 | Sep 18 05:30:44 AM UTC 24 | 601743958 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1739514344 | Sep 18 05:30:41 AM UTC 24 | Sep 18 05:30:44 AM UTC 24 | 22298427 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.3092719047 | Sep 18 05:30:42 AM UTC 24 | Sep 18 05:30:44 AM UTC 24 | 95802617 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3429030260 | Sep 18 05:30:43 AM UTC 24 | Sep 18 05:30:45 AM UTC 24 | 18802814 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1313446247 | Sep 18 05:30:43 AM UTC 24 | Sep 18 05:30:45 AM UTC 24 | 28857592 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.2190092016 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:46 AM UTC 24 | 19897338 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.449356111 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:47 AM UTC 24 | 87630455 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1229995107 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:47 AM UTC 24 | 23038849 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2220631116 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:47 AM UTC 24 | 45622602 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1935741241 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:47 AM UTC 24 | 695797954 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1649396238 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:48 AM UTC 24 | 221919484 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1036314924 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:48 AM UTC 24 | 58463797 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1332911818 | Sep 18 05:30:46 AM UTC 24 | Sep 18 05:30:48 AM UTC 24 | 40654449 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.133973541 | Sep 18 05:30:46 AM UTC 24 | Sep 18 05:30:48 AM UTC 24 | 11001711 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.326350659 | Sep 18 05:30:46 AM UTC 24 | Sep 18 05:30:48 AM UTC 24 | 111139909 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.2806838356 | Sep 18 05:30:45 AM UTC 24 | Sep 18 05:30:49 AM UTC 24 | 265174696 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3054817851 | Sep 18 05:30:48 AM UTC 24 | Sep 18 05:30:49 AM UTC 24 | 49383953 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2050683549 | Sep 18 05:30:48 AM UTC 24 | Sep 18 05:30:50 AM UTC 24 | 34588480 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.235988855 | Sep 18 05:30:48 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 380625453 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2829696838 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 46672235 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.2717125959 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 13183844 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1358817514 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 14099893 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3957508815 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 14531678 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.660208962 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 25806265 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2792559875 | Sep 18 05:30:48 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 110517658 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3206788521 | Sep 18 05:30:49 AM UTC 24 | Sep 18 05:30:51 AM UTC 24 | 637620600 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3024880685 | Sep 18 05:30:51 AM UTC 24 | Sep 18 05:30:53 AM UTC 24 | 14189384 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.4266337735 | Sep 18 05:30:51 AM UTC 24 | Sep 18 05:30:53 AM UTC 24 | 32355427 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2463935173 | Sep 18 05:30:51 AM UTC 24 | Sep 18 05:30:53 AM UTC 24 | 24297945 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1075603366 | Sep 18 05:30:52 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 13742267 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2061929395 | Sep 18 05:30:52 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 14164013 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2129804606 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 18433540 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1574244844 | Sep 18 05:30:52 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 54090748 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1344324050 | Sep 18 05:30:52 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 17128009 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3799907159 | Sep 18 05:30:53 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 27353684 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.31408157 | Sep 18 05:30:53 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 12461346 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.4101739269 | Sep 18 05:30:53 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 13576918 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3449546044 | Sep 18 05:30:53 AM UTC 24 | Sep 18 05:30:54 AM UTC 24 | 37511646 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1636721888 | Sep 18 05:30:54 AM UTC 24 | Sep 18 05:30:56 AM UTC 24 | 11851720 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.984762293 | Sep 18 05:30:54 AM UTC 24 | Sep 18 05:30:56 AM UTC 24 | 30753345 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2861038418 | Sep 18 05:30:54 AM UTC 24 | Sep 18 05:30:56 AM UTC 24 | 20523876 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.651509554 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 43551507 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.4044474635 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 14169232 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.853623722 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 130887852 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.911489423 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 13366775 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3115935684 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 45241031 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1149189981 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 14339146 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1299789736 | Sep 18 05:30:56 AM UTC 24 | Sep 18 05:30:58 AM UTC 24 | 24641770 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1152180020 | Sep 18 05:30:57 AM UTC 24 | Sep 18 05:30:59 AM UTC 24 | 200731724 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2151684336 | Sep 18 05:30:57 AM UTC 24 | Sep 18 05:30:59 AM UTC 24 | 47489616 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1733437694 | Sep 18 05:30:57 AM UTC 24 | Sep 18 05:30:59 AM UTC 24 | 19141929 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.254812686 | Sep 18 05:30:59 AM UTC 24 | Sep 18 05:31:01 AM UTC 24 | 11954895 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.2698316020 | Sep 18 05:30:59 AM UTC 24 | Sep 18 05:31:01 AM UTC 24 | 15227860 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all_with_rand_reset.51237746 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3635179344 ps |
| CPU time | 45.29 seconds |
| Started | Sep 18 04:46:22 AM UTC 24 |
| Finished | Sep 18 04:47:09 AM UTC 24 |
| Peak memory | 205308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=51237746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.51237746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3973339073 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 456608221293 ps |
| CPU time | 201.02 seconds |
| Started | Sep 18 04:49:45 AM UTC 24 |
| Finished | Sep 18 04:53:09 AM UTC 24 |
| Peak memory | 200984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973339073 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3973339073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1424395431 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 418345785 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 05:29:40 AM UTC 24 |
| Finished | Sep 18 05:29:43 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424395431 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1424395431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.3026405421 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 599759987659 ps |
| CPU time | 1668.57 seconds |
| Started | Sep 18 04:46:26 AM UTC 24 |
| Finished | Sep 18 05:14:32 AM UTC 24 |
| Peak memory | 202772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026405421 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.3026405421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3330066244 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2183610020974 ps |
| CPU time | 6002.51 seconds |
| Started | Sep 18 04:47:42 AM UTC 24 |
| Finished | Sep 18 06:28:51 AM UTC 24 |
| Peak memory | 202780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330066244 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3330066244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.1223993273 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 761667629131 ps |
| CPU time | 1784.04 seconds |
| Started | Sep 18 04:47:35 AM UTC 24 |
| Finished | Sep 18 05:17:37 AM UTC 24 |
| Peak memory | 202716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223993273 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.1223993273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3184257465 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18368365 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 05:29:50 AM UTC 24 |
| Finished | Sep 18 05:29:51 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184257465 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.3184257465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2109998612 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 645600530059 ps |
| CPU time | 828.1 seconds |
| Started | Sep 18 04:52:52 AM UTC 24 |
| Finished | Sep 18 05:06:50 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109998612 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2109998612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3071623144 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 317899195293 ps |
| CPU time | 323.14 seconds |
| Started | Sep 18 04:47:42 AM UTC 24 |
| Finished | Sep 18 04:53:09 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071623144 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3071623144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.2296952373 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 547308071865 ps |
| CPU time | 604.51 seconds |
| Started | Sep 18 04:48:29 AM UTC 24 |
| Finished | Sep 18 04:58:40 AM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296952373 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.2296952373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.2337571958 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 349477247315 ps |
| CPU time | 557.02 seconds |
| Started | Sep 18 04:46:36 AM UTC 24 |
| Finished | Sep 18 04:55:59 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337571958 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.2337571958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.4050328381 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 990401766924 ps |
| CPU time | 1176.26 seconds |
| Started | Sep 18 04:50:58 AM UTC 24 |
| Finished | Sep 18 05:10:47 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050328381 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.4050328381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.3745035599 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 780747338307 ps |
| CPU time | 3684.48 seconds |
| Started | Sep 18 04:56:40 AM UTC 24 |
| Finished | Sep 18 05:58:42 AM UTC 24 |
| Peak memory | 202644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745035599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.3745035599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.4174371011 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 213627427118 ps |
| CPU time | 1074.32 seconds |
| Started | Sep 18 04:50:37 AM UTC 24 |
| Finished | Sep 18 05:08:43 AM UTC 24 |
| Peak memory | 201220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174371011 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.4174371011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2245133134 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 993741044619 ps |
| CPU time | 1675.01 seconds |
| Started | Sep 18 04:47:36 AM UTC 24 |
| Finished | Sep 18 05:15:49 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245133134 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2245133134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.1535536695 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 197826030 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 04:46:18 AM UTC 24 |
| Finished | Sep 18 04:46:20 AM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535536695 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1535536695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.3957223343 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 407530195977 ps |
| CPU time | 4780.41 seconds |
| Started | Sep 18 04:49:27 AM UTC 24 |
| Finished | Sep 18 06:09:57 AM UTC 24 |
| Peak memory | 202972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957223343 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.3957223343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.2397006960 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 162341840485 ps |
| CPU time | 362.31 seconds |
| Started | Sep 18 04:51:00 AM UTC 24 |
| Finished | Sep 18 04:57:06 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397006960 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2397006960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.862842464 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1093298462211 ps |
| CPU time | 684.12 seconds |
| Started | Sep 18 05:07:54 AM UTC 24 |
| Finished | Sep 18 05:19:26 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862842464 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.862842464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.2517590258 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 483376504303 ps |
| CPU time | 315.29 seconds |
| Started | Sep 18 05:18:22 AM UTC 24 |
| Finished | Sep 18 05:23:42 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517590258 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2517590258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.1498878887 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1296463137235 ps |
| CPU time | 844.15 seconds |
| Started | Sep 18 04:53:47 AM UTC 24 |
| Finished | Sep 18 05:08:01 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498878887 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.1498878887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.595555071 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 328063252966 ps |
| CPU time | 1850.68 seconds |
| Started | Sep 18 04:59:50 AM UTC 24 |
| Finished | Sep 18 05:31:00 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595555071 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.595555071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.3127350078 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 171402913080 ps |
| CPU time | 827.36 seconds |
| Started | Sep 18 05:00:14 AM UTC 24 |
| Finished | Sep 18 05:14:10 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127350078 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.3127350078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.2890993186 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1377755596534 ps |
| CPU time | 1170.01 seconds |
| Started | Sep 18 05:05:17 AM UTC 24 |
| Finished | Sep 18 05:24:59 AM UTC 24 |
| Peak memory | 202776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890993186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.2890993186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.1189046764 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 596864922648 ps |
| CPU time | 4606.93 seconds |
| Started | Sep 18 05:06:00 AM UTC 24 |
| Finished | Sep 18 06:23:40 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189046764 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.1189046764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.3720686508 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 803888329550 ps |
| CPU time | 1455.21 seconds |
| Started | Sep 18 04:54:50 AM UTC 24 |
| Finished | Sep 18 05:19:20 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720686508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.3720686508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2216919295 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3186604815597 ps |
| CPU time | 1267.96 seconds |
| Started | Sep 18 04:49:54 AM UTC 24 |
| Finished | Sep 18 05:11:15 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216919295 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.2216919295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.2513163318 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 127158495883 ps |
| CPU time | 219.65 seconds |
| Started | Sep 18 04:54:51 AM UTC 24 |
| Finished | Sep 18 04:58:34 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513163318 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2513163318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.2538095415 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 816302716401 ps |
| CPU time | 1215.89 seconds |
| Started | Sep 18 04:55:28 AM UTC 24 |
| Finished | Sep 18 05:15:57 AM UTC 24 |
| Peak memory | 202648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538095415 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.2538095415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.19388709 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 383191704314 ps |
| CPU time | 444.21 seconds |
| Started | Sep 18 04:57:26 AM UTC 24 |
| Finished | Sep 18 05:04:55 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19388709 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.19388709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.209871174 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2900964598255 ps |
| CPU time | 3231.05 seconds |
| Started | Sep 18 05:00:35 AM UTC 24 |
| Finished | Sep 18 05:55:00 AM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209871174 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.209871174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.3730904373 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2229394833406 ps |
| CPU time | 4006.53 seconds |
| Started | Sep 18 05:07:18 AM UTC 24 |
| Finished | Sep 18 06:14:49 AM UTC 24 |
| Peak memory | 203032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730904373 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.3730904373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.1448598650 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 186267668564 ps |
| CPU time | 757.74 seconds |
| Started | Sep 18 05:24:34 AM UTC 24 |
| Finished | Sep 18 05:37:21 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448598650 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1448598650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.1350419445 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 161681123257 ps |
| CPU time | 1044.1 seconds |
| Started | Sep 18 05:03:03 AM UTC 24 |
| Finished | Sep 18 05:20:39 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350419445 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1350419445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3852360213 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 268319416254 ps |
| CPU time | 344.03 seconds |
| Started | Sep 18 05:08:40 AM UTC 24 |
| Finished | Sep 18 05:14:28 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852360213 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3852360213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.770152361 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1317179992127 ps |
| CPU time | 1892.59 seconds |
| Started | Sep 18 04:46:18 AM UTC 24 |
| Finished | Sep 18 05:18:11 AM UTC 24 |
| Peak memory | 202772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770152361 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.770152361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1079113045 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 997047268141 ps |
| CPU time | 415.24 seconds |
| Started | Sep 18 05:17:38 AM UTC 24 |
| Finished | Sep 18 05:24:39 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079113045 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1079113045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.446426861 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 600376317310 ps |
| CPU time | 844.58 seconds |
| Started | Sep 18 04:49:18 AM UTC 24 |
| Finished | Sep 18 05:03:32 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446426861 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.446426861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.1781947322 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 118748456542 ps |
| CPU time | 193.46 seconds |
| Started | Sep 18 04:47:52 AM UTC 24 |
| Finished | Sep 18 04:51:08 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781947322 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1781947322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.4289590238 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 353962317045 ps |
| CPU time | 346.15 seconds |
| Started | Sep 18 04:48:01 AM UTC 24 |
| Finished | Sep 18 04:53:52 AM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289590238 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.4289590238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.59533018 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 196308236302 ps |
| CPU time | 719.61 seconds |
| Started | Sep 18 05:21:15 AM UTC 24 |
| Finished | Sep 18 05:33:23 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59533018 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.59533018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.851313525 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 105203761781 ps |
| CPU time | 232.74 seconds |
| Started | Sep 18 05:28:02 AM UTC 24 |
| Finished | Sep 18 05:31:58 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851313525 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.851313525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1498175713 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1745325132308 ps |
| CPU time | 1712.38 seconds |
| Started | Sep 18 04:51:23 AM UTC 24 |
| Finished | Sep 18 05:20:12 AM UTC 24 |
| Peak memory | 202944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498175713 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1498175713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.1565608771 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 211715097457 ps |
| CPU time | 480.07 seconds |
| Started | Sep 18 05:17:47 AM UTC 24 |
| Finished | Sep 18 05:25:53 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565608771 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1565608771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.3556147233 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 379382600041 ps |
| CPU time | 280.29 seconds |
| Started | Sep 18 05:17:57 AM UTC 24 |
| Finished | Sep 18 05:22:41 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556147233 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3556147233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.871579902 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 114529845971 ps |
| CPU time | 1286.1 seconds |
| Started | Sep 18 05:23:40 AM UTC 24 |
| Finished | Sep 18 05:45:20 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871579902 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.871579902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.4145922665 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 105332824210 ps |
| CPU time | 397.75 seconds |
| Started | Sep 18 05:26:45 AM UTC 24 |
| Finished | Sep 18 05:33:29 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145922665 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4145922665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.2083688149 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 51623543109 ps |
| CPU time | 224.1 seconds |
| Started | Sep 18 05:28:48 AM UTC 24 |
| Finished | Sep 18 05:32:35 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083688149 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2083688149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.793899748 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1861781851322 ps |
| CPU time | 1126.43 seconds |
| Started | Sep 18 04:54:13 AM UTC 24 |
| Finished | Sep 18 05:13:11 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793899748 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.793899748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.696299858 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 772136623109 ps |
| CPU time | 1282.53 seconds |
| Started | Sep 18 04:58:57 AM UTC 24 |
| Finished | Sep 18 05:20:34 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696299858 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.696299858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.411167701 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 168408743445 ps |
| CPU time | 1294.1 seconds |
| Started | Sep 18 05:02:12 AM UTC 24 |
| Finished | Sep 18 05:24:01 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411167701 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.411167701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.4099460180 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 545855394936 ps |
| CPU time | 656.48 seconds |
| Started | Sep 18 04:46:40 AM UTC 24 |
| Finished | Sep 18 04:57:43 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099460180 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.4099460180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.782251315 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 51828953015 ps |
| CPU time | 155.91 seconds |
| Started | Sep 18 05:08:44 AM UTC 24 |
| Finished | Sep 18 05:11:22 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782251315 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.782251315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.3050621400 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 391739578754 ps |
| CPU time | 553.49 seconds |
| Started | Sep 18 05:08:47 AM UTC 24 |
| Finished | Sep 18 05:18:07 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050621400 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3050621400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.61855454 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 871052422774 ps |
| CPU time | 2089.78 seconds |
| Started | Sep 18 05:11:11 AM UTC 24 |
| Finished | Sep 18 05:46:23 AM UTC 24 |
| Peak memory | 202768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61855454 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.61855454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.4098263230 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 497121474033 ps |
| CPU time | 528.29 seconds |
| Started | Sep 18 04:47:11 AM UTC 24 |
| Finished | Sep 18 04:56:06 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098263230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4098263230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.2811495182 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 173933909092 ps |
| CPU time | 199.73 seconds |
| Started | Sep 18 05:13:11 AM UTC 24 |
| Finished | Sep 18 05:16:34 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811495182 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2811495182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.2721790282 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 374024923200 ps |
| CPU time | 2643.05 seconds |
| Started | Sep 18 05:13:42 AM UTC 24 |
| Finished | Sep 18 05:58:15 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721790282 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2721790282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.1497557339 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 368436597391 ps |
| CPU time | 336.34 seconds |
| Started | Sep 18 05:14:29 AM UTC 24 |
| Finished | Sep 18 05:20:10 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497557339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1497557339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.309284683 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 241517846 ps |
| CPU time | 3.18 seconds |
| Started | Sep 18 05:29:48 AM UTC 24 |
| Finished | Sep 18 05:29:52 AM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309284683 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.309284683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4256035349 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 30366649 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 05:29:50 AM UTC 24 |
| Finished | Sep 18 05:29:52 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256035349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.4256035349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2446055584 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 171833504087 ps |
| CPU time | 633.43 seconds |
| Started | Sep 18 05:16:26 AM UTC 24 |
| Finished | Sep 18 05:27:07 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446055584 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2446055584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.2332140209 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 260484472574 ps |
| CPU time | 384.55 seconds |
| Started | Sep 18 05:17:37 AM UTC 24 |
| Finished | Sep 18 05:24:07 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332140209 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2332140209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.325581132 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 102391388451 ps |
| CPU time | 208.87 seconds |
| Started | Sep 18 05:18:18 AM UTC 24 |
| Finished | Sep 18 05:21:50 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325581132 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.325581132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.3910026960 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 434407366732 ps |
| CPU time | 538.74 seconds |
| Started | Sep 18 05:18:20 AM UTC 24 |
| Finished | Sep 18 05:27:26 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910026960 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3910026960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.570489240 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3291262896741 ps |
| CPU time | 947.42 seconds |
| Started | Sep 18 04:47:51 AM UTC 24 |
| Finished | Sep 18 05:03:49 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570489240 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.570489240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.44140002 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 478896780304 ps |
| CPU time | 355.15 seconds |
| Started | Sep 18 05:18:33 AM UTC 24 |
| Finished | Sep 18 05:24:33 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44140002 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.44140002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.2176320281 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 33862086202 ps |
| CPU time | 119.57 seconds |
| Started | Sep 18 05:20:40 AM UTC 24 |
| Finished | Sep 18 05:22:41 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176320281 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2176320281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1084261508 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 172199216983 ps |
| CPU time | 125.97 seconds |
| Started | Sep 18 05:21:30 AM UTC 24 |
| Finished | Sep 18 05:23:39 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084261508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1084261508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.2128605257 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1254898014988 ps |
| CPU time | 942.97 seconds |
| Started | Sep 18 05:24:01 AM UTC 24 |
| Finished | Sep 18 05:39:55 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128605257 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2128605257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.261056305 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2211481734932 ps |
| CPU time | 816.27 seconds |
| Started | Sep 18 04:49:10 AM UTC 24 |
| Finished | Sep 18 05:02:54 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261056305 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.261056305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.2195812330 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1406685740006 ps |
| CPU time | 1644.48 seconds |
| Started | Sep 18 05:24:22 AM UTC 24 |
| Finished | Sep 18 05:52:04 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195812330 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2195812330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.604522323 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 171018122473 ps |
| CPU time | 789.71 seconds |
| Started | Sep 18 05:27:13 AM UTC 24 |
| Finished | Sep 18 05:40:32 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604522323 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.604522323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.1305617525 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 84423381236 ps |
| CPU time | 177.68 seconds |
| Started | Sep 18 05:28:30 AM UTC 24 |
| Finished | Sep 18 05:31:30 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305617525 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1305617525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.2893883070 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 128873416771 ps |
| CPU time | 531 seconds |
| Started | Sep 18 05:03:50 AM UTC 24 |
| Finished | Sep 18 05:12:47 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893883070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2893883070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2759600887 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 301122929726 ps |
| CPU time | 594.38 seconds |
| Started | Sep 18 05:07:55 AM UTC 24 |
| Finished | Sep 18 05:17:56 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759600887 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2759600887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.781082579 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 151678371216 ps |
| CPU time | 518.69 seconds |
| Started | Sep 18 05:11:40 AM UTC 24 |
| Finished | Sep 18 05:20:25 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781082579 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.781082579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1905960697 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 15489067927 ps |
| CPU time | 57.73 seconds |
| Started | Sep 18 05:12:05 AM UTC 24 |
| Finished | Sep 18 05:13:04 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905960697 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1905960697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.4156041198 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 430125599650 ps |
| CPU time | 324.53 seconds |
| Started | Sep 18 05:15:57 AM UTC 24 |
| Finished | Sep 18 05:21:26 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156041198 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4156041198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.3872027549 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 333016971135 ps |
| CPU time | 298.91 seconds |
| Started | Sep 18 05:17:47 AM UTC 24 |
| Finished | Sep 18 05:22:50 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872027549 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3872027549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.699617401 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 152824684738 ps |
| CPU time | 367.93 seconds |
| Started | Sep 18 05:20:26 AM UTC 24 |
| Finished | Sep 18 05:26:39 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699617401 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.699617401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1690366639 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 90375371512 ps |
| CPU time | 262.51 seconds |
| Started | Sep 18 05:21:27 AM UTC 24 |
| Finished | Sep 18 05:25:53 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690366639 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1690366639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.4064116185 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 226128601172 ps |
| CPU time | 504.3 seconds |
| Started | Sep 18 05:22:10 AM UTC 24 |
| Finished | Sep 18 05:30:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064116185 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4064116185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1921755174 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 135048645988 ps |
| CPU time | 219.33 seconds |
| Started | Sep 18 05:22:35 AM UTC 24 |
| Finished | Sep 18 05:26:17 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921755174 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1921755174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.139345363 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 227539032565 ps |
| CPU time | 1850.32 seconds |
| Started | Sep 18 05:24:25 AM UTC 24 |
| Finished | Sep 18 05:55:36 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139345363 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.139345363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.2660673239 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 14409850434 ps |
| CPU time | 69.45 seconds |
| Started | Sep 18 05:25:00 AM UTC 24 |
| Finished | Sep 18 05:26:12 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660673239 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2660673239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.2440753699 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 438486376422 ps |
| CPU time | 284.21 seconds |
| Started | Sep 18 05:25:48 AM UTC 24 |
| Finished | Sep 18 05:30:36 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440753699 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2440753699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1115865636 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 383388358500 ps |
| CPU time | 359.57 seconds |
| Started | Sep 18 04:49:31 AM UTC 24 |
| Finished | Sep 18 04:55:35 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115865636 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1115865636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.2525088990 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 305105214206 ps |
| CPU time | 356.33 seconds |
| Started | Sep 18 05:28:48 AM UTC 24 |
| Finished | Sep 18 05:34:49 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525088990 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2525088990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.2661093649 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 101245594393 ps |
| CPU time | 181.19 seconds |
| Started | Sep 18 05:28:56 AM UTC 24 |
| Finished | Sep 18 05:32:00 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661093649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2661093649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2785334267 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 34340819164 ps |
| CPU time | 99.5 seconds |
| Started | Sep 18 04:51:44 AM UTC 24 |
| Finished | Sep 18 04:53:26 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785334267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2785334267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.3010285615 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 275329508494 ps |
| CPU time | 255.7 seconds |
| Started | Sep 18 04:53:25 AM UTC 24 |
| Finished | Sep 18 04:57:45 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010285615 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3010285615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3997895938 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1636744727072 ps |
| CPU time | 1155.59 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 05:05:57 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997895938 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.3997895938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.4099720244 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 119457731281 ps |
| CPU time | 242.52 seconds |
| Started | Sep 18 04:57:38 AM UTC 24 |
| Finished | Sep 18 05:01:44 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099720244 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.4099720244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2386390496 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1236517323808 ps |
| CPU time | 1101.28 seconds |
| Started | Sep 18 05:05:52 AM UTC 24 |
| Finished | Sep 18 05:24:24 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386390496 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2386390496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.2590421506 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 122326639165 ps |
| CPU time | 171.22 seconds |
| Started | Sep 18 05:05:35 AM UTC 24 |
| Finished | Sep 18 05:08:29 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590421506 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2590421506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.4028266809 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 54417982028 ps |
| CPU time | 124.51 seconds |
| Started | Sep 18 05:10:00 AM UTC 24 |
| Finished | Sep 18 05:12:07 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028266809 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4028266809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.1144200808 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 136714142460 ps |
| CPU time | 378.5 seconds |
| Started | Sep 18 05:11:23 AM UTC 24 |
| Finished | Sep 18 05:17:46 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144200808 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1144200808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.2034469199 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 204281932232 ps |
| CPU time | 381.78 seconds |
| Started | Sep 18 05:15:01 AM UTC 24 |
| Finished | Sep 18 05:21:28 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034469199 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2034469199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1117721042 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 57078590 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:29:45 AM UTC 24 |
| Finished | Sep 18 05:29:47 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117721042 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1117721042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3422389968 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 38016524 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 05:29:53 AM UTC 24 |
| Finished | Sep 18 05:29:55 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3422389968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.3422389968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.586256068 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 62477547 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:29:46 AM UTC 24 |
| Finished | Sep 18 05:29:48 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586256068 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.586256068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.2897180975 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 29855353 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:29:44 AM UTC 24 |
| Finished | Sep 18 05:29:46 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897180975 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2897180975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.1675492508 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 58503373 ps |
| CPU time | 4.08 seconds |
| Started | Sep 18 05:29:34 AM UTC 24 |
| Finished | Sep 18 05:29:39 AM UTC 24 |
| Peak memory | 202704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675492508 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1675492508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.540043720 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 38360690 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 05:29:58 AM UTC 24 |
| Finished | Sep 18 05:30:00 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540043720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.540043720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3116778808 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 197077528 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 05:29:58 AM UTC 24 |
| Finished | Sep 18 05:30:01 AM UTC 24 |
| Peak memory | 200884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116778808 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.3116778808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3711620089 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 17895053 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:29:56 AM UTC 24 |
| Finished | Sep 18 05:29:58 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711620089 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.3711620089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3182409343 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 81659130 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 05:30:01 AM UTC 24 |
| Finished | Sep 18 05:30:04 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3182409343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.3182409343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.3856255660 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 29962724 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 05:29:57 AM UTC 24 |
| Finished | Sep 18 05:29:59 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856255660 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3856255660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.747417236 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 89634750 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 05:29:56 AM UTC 24 |
| Finished | Sep 18 05:29:58 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747417236 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.747417236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1693923061 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 42389430 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:29:59 AM UTC 24 |
| Finished | Sep 18 05:30:01 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693923061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.1693923061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.4142460297 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 88286295 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 05:29:53 AM UTC 24 |
| Finished | Sep 18 05:29:56 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142460297 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4142460297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1407008131 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 46851618 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 05:29:53 AM UTC 24 |
| Finished | Sep 18 05:29:55 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407008131 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1407008131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.148946432 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 49548888 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 05:30:30 AM UTC 24 |
| Finished | Sep 18 05:30:32 AM UTC 24 |
| Peak memory | 198980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=148946432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_cs r_mem_rw_with_rand_reset.148946432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2362464603 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 41985531 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:30 AM UTC 24 |
| Finished | Sep 18 05:30:32 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362464603 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2362464603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2203364225 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 23431734 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:30 AM UTC 24 |
| Finished | Sep 18 05:30:31 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203364225 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2203364225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3415994572 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 117612922 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 05:30:30 AM UTC 24 |
| Finished | Sep 18 05:30:32 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415994572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.3415994572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.2256510052 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 54480735 ps |
| CPU time | 2.22 seconds |
| Started | Sep 18 05:30:27 AM UTC 24 |
| Finished | Sep 18 05:30:30 AM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256510052 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2256510052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1362474926 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 293639946 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 05:30:28 AM UTC 24 |
| Finished | Sep 18 05:30:31 AM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362474926 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.1362474926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.88578128 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 140534824 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:36 AM UTC 24 |
| Peak memory | 200664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=88578128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr _mem_rw_with_rand_reset.88578128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.3979455355 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 15107732 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:35 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979455355 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3979455355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.2560202595 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 50687268 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:31 AM UTC 24 |
| Finished | Sep 18 05:30:33 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560202595 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2560202595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1283894555 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 15877039 ps |
| CPU time | 1 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:35 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283894555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.1283894555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2815385864 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 45083210 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 05:30:31 AM UTC 24 |
| Finished | Sep 18 05:30:34 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815385864 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2815385864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1914354482 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 45682493 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 05:30:31 AM UTC 24 |
| Finished | Sep 18 05:30:33 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914354482 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.1914354482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.213984116 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 112417281 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 05:30:35 AM UTC 24 |
| Finished | Sep 18 05:30:38 AM UTC 24 |
| Peak memory | 198980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=213984116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_cs r_mem_rw_with_rand_reset.213984116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3919907945 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 153760924 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:34 AM UTC 24 |
| Finished | Sep 18 05:30:36 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919907945 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3919907945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.665746872 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 13141225 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:35 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665746872 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.665746872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2215707172 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 160396452 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 05:30:34 AM UTC 24 |
| Finished | Sep 18 05:30:36 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215707172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.2215707172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.4146813183 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 53722127 ps |
| CPU time | 3.14 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:37 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146813183 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4146813183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1265489263 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 88775647 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 05:30:33 AM UTC 24 |
| Finished | Sep 18 05:30:35 AM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265489263 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1265489263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3890915374 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 116106038 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 05:30:37 AM UTC 24 |
| Finished | Sep 18 05:30:40 AM UTC 24 |
| Peak memory | 200956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3890915374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.3890915374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.3836342931 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 19496797 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:36 AM UTC 24 |
| Finished | Sep 18 05:30:37 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836342931 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3836342931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1379896748 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 27624798 ps |
| CPU time | 0.7 seconds |
| Started | Sep 18 05:30:36 AM UTC 24 |
| Finished | Sep 18 05:30:37 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379896748 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1379896748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3069093933 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 197429750 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 05:30:37 AM UTC 24 |
| Finished | Sep 18 05:30:39 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069093933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.3069093933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1281384060 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 384137696 ps |
| CPU time | 3.19 seconds |
| Started | Sep 18 05:30:36 AM UTC 24 |
| Finished | Sep 18 05:30:40 AM UTC 24 |
| Peak memory | 202796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281384060 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1281384060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.486909676 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 170383670 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 05:30:36 AM UTC 24 |
| Finished | Sep 18 05:30:38 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486909676 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.486909676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3832475442 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 22228991 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 05:30:39 AM UTC 24 |
| Finished | Sep 18 05:30:41 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3832475442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.3832475442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1362066909 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 14134593 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 05:30:39 AM UTC 24 |
| Finished | Sep 18 05:30:40 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362066909 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1362066909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2669227592 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 218826794 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:38 AM UTC 24 |
| Finished | Sep 18 05:30:40 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669227592 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2669227592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3486475343 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 109280771 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 05:30:39 AM UTC 24 |
| Finished | Sep 18 05:30:41 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486475343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3486475343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2256169807 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 364487416 ps |
| CPU time | 4.01 seconds |
| Started | Sep 18 05:30:37 AM UTC 24 |
| Finished | Sep 18 05:30:42 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256169807 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2256169807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.748975770 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 174981870 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 05:30:37 AM UTC 24 |
| Finished | Sep 18 05:30:39 AM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748975770 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.748975770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1739514344 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 22298427 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 05:30:41 AM UTC 24 |
| Finished | Sep 18 05:30:44 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1739514344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1739514344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.665354473 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 53750976 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:41 AM UTC 24 |
| Finished | Sep 18 05:30:43 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665354473 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.665354473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2720649720 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 12261920 ps |
| CPU time | 0.72 seconds |
| Started | Sep 18 05:30:40 AM UTC 24 |
| Finished | Sep 18 05:30:42 AM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720649720 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2720649720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.840102154 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 44298442 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 05:30:41 AM UTC 24 |
| Finished | Sep 18 05:30:43 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840102154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.840102154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.677602210 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 134416257 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 05:30:39 AM UTC 24 |
| Finished | Sep 18 05:30:43 AM UTC 24 |
| Peak memory | 200592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677602210 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.677602210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3841411534 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 101511570 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 05:30:40 AM UTC 24 |
| Finished | Sep 18 05:30:43 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841411534 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3841411534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1313446247 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 28857592 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 05:30:43 AM UTC 24 |
| Finished | Sep 18 05:30:45 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1313446247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.1313446247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.3915747767 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 29946235 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:30:42 AM UTC 24 |
| Finished | Sep 18 05:30:44 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915747767 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3915747767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.2545283823 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 15147418 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:42 AM UTC 24 |
| Finished | Sep 18 05:30:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545283823 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2545283823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3429030260 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 18802814 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 05:30:43 AM UTC 24 |
| Finished | Sep 18 05:30:45 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429030260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.3429030260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.3092719047 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 95802617 ps |
| CPU time | 1.67 seconds |
| Started | Sep 18 05:30:42 AM UTC 24 |
| Finished | Sep 18 05:30:44 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092719047 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3092719047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4099558813 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 601743958 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 05:30:42 AM UTC 24 |
| Finished | Sep 18 05:30:44 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099558813 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.4099558813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2220631116 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 45622602 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:47 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2220631116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.2220631116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.449356111 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 87630455 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:47 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449356111 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.449356111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.2190092016 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 19897338 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:46 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190092016 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2190092016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1229995107 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 23038849 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:47 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229995107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.1229995107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1036314924 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 58463797 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:48 AM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036314924 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1036314924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1649396238 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 221919484 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:48 AM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649396238 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.1649396238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2050683549 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 34588480 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 05:30:48 AM UTC 24 |
| Finished | Sep 18 05:30:50 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2050683549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.2050683549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.133973541 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 11001711 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:46 AM UTC 24 |
| Finished | Sep 18 05:30:48 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133973541 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.133973541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1332911818 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 40654449 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:46 AM UTC 24 |
| Finished | Sep 18 05:30:48 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332911818 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1332911818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.326350659 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 111139909 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 05:30:46 AM UTC 24 |
| Finished | Sep 18 05:30:48 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326350659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.326350659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.2806838356 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 265174696 ps |
| CPU time | 3.47 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:49 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806838356 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2806838356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1935741241 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 695797954 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 05:30:45 AM UTC 24 |
| Finished | Sep 18 05:30:47 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935741241 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.1935741241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.660208962 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 25806265 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 198980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=660208962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_cs r_mem_rw_with_rand_reset.660208962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2829696838 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 46672235 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829696838 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2829696838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3054817851 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 49383953 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:48 AM UTC 24 |
| Finished | Sep 18 05:30:49 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054817851 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3054817851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3206788521 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 637620600 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206788521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.3206788521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2792559875 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 110517658 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 05:30:48 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792559875 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2792559875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.235988855 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 380625453 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 05:30:48 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 200936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235988855 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.235988855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1741124845 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 18466449 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 05:30:05 AM UTC 24 |
| Finished | Sep 18 05:30:07 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741124845 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.1741124845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2474130512 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 190889109 ps |
| CPU time | 3.13 seconds |
| Started | Sep 18 05:30:05 AM UTC 24 |
| Finished | Sep 18 05:30:09 AM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474130512 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2474130512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.868272757 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 23800704 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:03 AM UTC 24 |
| Finished | Sep 18 05:30:04 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868272757 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.868272757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1066837743 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 162973168 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 05:30:06 AM UTC 24 |
| Finished | Sep 18 05:30:08 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1066837743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.1066837743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1198121280 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 53060052 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:04 AM UTC 24 |
| Finished | Sep 18 05:30:05 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198121280 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1198121280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2513523463 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 12725962 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 05:30:01 AM UTC 24 |
| Finished | Sep 18 05:30:03 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513523463 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2513523463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.226549962 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 20509103 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 05:30:05 AM UTC 24 |
| Finished | Sep 18 05:30:07 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226549962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.226549962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2827411464 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 562291775 ps |
| CPU time | 4.21 seconds |
| Started | Sep 18 05:30:01 AM UTC 24 |
| Finished | Sep 18 05:30:07 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827411464 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2827411464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.480456684 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 81569751 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 05:30:01 AM UTC 24 |
| Finished | Sep 18 05:30:04 AM UTC 24 |
| Peak memory | 198764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480456684 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.480456684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.2717125959 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 13183844 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717125959 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2717125959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3957508815 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 14531678 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957508815 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3957508815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1358817514 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 14099893 ps |
| CPU time | 0.76 seconds |
| Started | Sep 18 05:30:49 AM UTC 24 |
| Finished | Sep 18 05:30:51 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358817514 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1358817514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2463935173 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 24297945 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:51 AM UTC 24 |
| Finished | Sep 18 05:30:53 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463935173 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2463935173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.3024880685 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 14189384 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:51 AM UTC 24 |
| Finished | Sep 18 05:30:53 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024880685 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3024880685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.4266337735 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 32355427 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 05:30:51 AM UTC 24 |
| Finished | Sep 18 05:30:53 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266337735 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4266337735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2061929395 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 14164013 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:52 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061929395 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2061929395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1075603366 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 13742267 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 05:30:52 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075603366 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1075603366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1574244844 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 54090748 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:52 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574244844 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1574244844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1344324050 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 17128009 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:52 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344324050 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1344324050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4288921799 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 36887090 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 05:30:11 AM UTC 24 |
| Finished | Sep 18 05:30:12 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288921799 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.4288921799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1282573302 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 84577529 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 05:30:09 AM UTC 24 |
| Finished | Sep 18 05:30:12 AM UTC 24 |
| Peak memory | 200816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282573302 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.1282573302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3627521595 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13426865 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:09 AM UTC 24 |
| Finished | Sep 18 05:30:11 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627521595 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.3627521595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2550736024 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 50940799 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 05:30:11 AM UTC 24 |
| Finished | Sep 18 05:30:14 AM UTC 24 |
| Peak memory | 200808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2550736024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2550736024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.1877671791 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 20771721 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:09 AM UTC 24 |
| Finished | Sep 18 05:30:11 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877671791 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1877671791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.852989932 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 49225222 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:08 AM UTC 24 |
| Finished | Sep 18 05:30:10 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852989932 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.852989932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3881539934 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 208536270 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 05:30:11 AM UTC 24 |
| Finished | Sep 18 05:30:12 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881539934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.3881539934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.1085779410 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 32965837 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 05:30:07 AM UTC 24 |
| Finished | Sep 18 05:30:09 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085779410 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1085779410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3475116116 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 116775362 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 05:30:07 AM UTC 24 |
| Finished | Sep 18 05:30:09 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475116116 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.3475116116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3799907159 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 27353684 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:53 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799907159 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3799907159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.31408157 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 12461346 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:53 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31408157 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.31408157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.4101739269 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 13576918 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:53 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101739269 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4101739269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3449546044 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 37511646 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 05:30:53 AM UTC 24 |
| Finished | Sep 18 05:30:54 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449546044 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3449546044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1636721888 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 11851720 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:30:54 AM UTC 24 |
| Finished | Sep 18 05:30:56 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636721888 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1636721888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2861038418 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 20523876 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:54 AM UTC 24 |
| Finished | Sep 18 05:30:56 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861038418 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2861038418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.984762293 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 30753345 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 05:30:54 AM UTC 24 |
| Finished | Sep 18 05:30:56 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984762293 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.984762293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.651509554 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 43551507 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651509554 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.651509554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.4044474635 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 14169232 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044474635 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4044474635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.853623722 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 130887852 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853623722 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.853623722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2519997000 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 39098689 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 05:30:14 AM UTC 24 |
| Finished | Sep 18 05:30:16 AM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519997000 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.2519997000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1314958793 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 66912322 ps |
| CPU time | 3.14 seconds |
| Started | Sep 18 05:30:13 AM UTC 24 |
| Finished | Sep 18 05:30:17 AM UTC 24 |
| Peak memory | 200756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314958793 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1314958793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2387375634 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 21074548 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 05:30:13 AM UTC 24 |
| Finished | Sep 18 05:30:15 AM UTC 24 |
| Peak memory | 198768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387375634 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.2387375634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2925071794 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 141401722 ps |
| CPU time | 2.56 seconds |
| Started | Sep 18 05:30:16 AM UTC 24 |
| Finished | Sep 18 05:30:19 AM UTC 24 |
| Peak memory | 200808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2925071794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.2925071794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.2023875902 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 49232659 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:13 AM UTC 24 |
| Finished | Sep 18 05:30:15 AM UTC 24 |
| Peak memory | 198784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023875902 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2023875902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.60739369 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 46110471 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:12 AM UTC 24 |
| Finished | Sep 18 05:30:14 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60739369 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.60739369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.618456810 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 60935029 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 05:30:14 AM UTC 24 |
| Finished | Sep 18 05:30:16 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618456810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.618456810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.619427930 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 118926203 ps |
| CPU time | 2.2 seconds |
| Started | Sep 18 05:30:12 AM UTC 24 |
| Finished | Sep 18 05:30:15 AM UTC 24 |
| Peak memory | 202800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619427930 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.619427930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2667716569 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 309280612 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 05:30:12 AM UTC 24 |
| Finished | Sep 18 05:30:14 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667716569 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.2667716569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3115935684 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 45241031 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115935684 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3115935684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.911489423 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13366775 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911489423 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.911489423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2129804606 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 18433540 ps |
| CPU time | 0.82 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129804606 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2129804606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1149189981 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 14339146 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149189981 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1149189981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1299789736 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 24641770 ps |
| CPU time | 0.83 seconds |
| Started | Sep 18 05:30:56 AM UTC 24 |
| Finished | Sep 18 05:30:58 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299789736 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1299789736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1152180020 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 200731724 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:57 AM UTC 24 |
| Finished | Sep 18 05:30:59 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152180020 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1152180020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1733437694 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 19141929 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 05:30:57 AM UTC 24 |
| Finished | Sep 18 05:30:59 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733437694 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1733437694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2151684336 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 47489616 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:30:57 AM UTC 24 |
| Finished | Sep 18 05:30:59 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151684336 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2151684336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.254812686 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 11954895 ps |
| CPU time | 0.77 seconds |
| Started | Sep 18 05:30:59 AM UTC 24 |
| Finished | Sep 18 05:31:01 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254812686 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.254812686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.2698316020 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 15227860 ps |
| CPU time | 0.78 seconds |
| Started | Sep 18 05:30:59 AM UTC 24 |
| Finished | Sep 18 05:31:01 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698316020 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2698316020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1949909061 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 593377268 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 05:30:17 AM UTC 24 |
| Finished | Sep 18 05:30:19 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1949909061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.1949909061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.1739197067 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 81189114 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:16 AM UTC 24 |
| Finished | Sep 18 05:30:17 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739197067 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1739197067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.1345545646 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 44189454 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 05:30:16 AM UTC 24 |
| Finished | Sep 18 05:30:18 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345545646 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1345545646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1074429948 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 123697904 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 05:30:17 AM UTC 24 |
| Finished | Sep 18 05:30:19 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074429948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.1074429948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.2855317917 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 187040577 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 05:30:16 AM UTC 24 |
| Finished | Sep 18 05:30:18 AM UTC 24 |
| Peak memory | 200952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855317917 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2855317917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3202224674 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 92415992 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 05:30:16 AM UTC 24 |
| Finished | Sep 18 05:30:18 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202224674 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.3202224674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.358907702 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 22230421 ps |
| CPU time | 1.07 seconds |
| Started | Sep 18 05:30:21 AM UTC 24 |
| Finished | Sep 18 05:30:23 AM UTC 24 |
| Peak memory | 198980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=358907702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.358907702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2662779777 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 33332901 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:30:19 AM UTC 24 |
| Finished | Sep 18 05:30:21 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662779777 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2662779777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2230477827 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 15497099 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 05:30:18 AM UTC 24 |
| Finished | Sep 18 05:30:20 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230477827 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2230477827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.601753857 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 45777896 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 05:30:19 AM UTC 24 |
| Finished | Sep 18 05:30:21 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601753857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.601753857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.1424482057 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 185139267 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 05:30:18 AM UTC 24 |
| Finished | Sep 18 05:30:22 AM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424482057 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1424482057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2204661222 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 322731765 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 05:30:18 AM UTC 24 |
| Finished | Sep 18 05:30:22 AM UTC 24 |
| Peak memory | 200760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204661222 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.2204661222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2162854382 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 89212500 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 05:30:23 AM UTC 24 |
| Finished | Sep 18 05:30:25 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2162854382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.2162854382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.1954482697 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 31287514 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 05:30:22 AM UTC 24 |
| Finished | Sep 18 05:30:24 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954482697 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1954482697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.3178681086 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 23695566 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:30:21 AM UTC 24 |
| Finished | Sep 18 05:30:22 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178681086 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3178681086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.449329770 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 179047869 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 05:30:22 AM UTC 24 |
| Finished | Sep 18 05:30:24 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449329770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.449329770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.2253634825 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 27831063 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 05:30:21 AM UTC 24 |
| Finished | Sep 18 05:30:23 AM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253634825 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2253634825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.229500257 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 450097231 ps |
| CPU time | 2.09 seconds |
| Started | Sep 18 05:30:21 AM UTC 24 |
| Finished | Sep 18 05:30:24 AM UTC 24 |
| Peak memory | 200744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229500257 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.229500257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1738030035 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 69338474 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 05:30:25 AM UTC 24 |
| Finished | Sep 18 05:30:26 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1738030035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.1738030035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.2346490979 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 26963501 ps |
| CPU time | 0.86 seconds |
| Started | Sep 18 05:30:24 AM UTC 24 |
| Finished | Sep 18 05:30:26 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346490979 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2346490979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.3565463510 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 43256037 ps |
| CPU time | 0.79 seconds |
| Started | Sep 18 05:30:23 AM UTC 24 |
| Finished | Sep 18 05:30:25 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565463510 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3565463510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3070324484 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 47596067 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 05:30:24 AM UTC 24 |
| Finished | Sep 18 05:30:27 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070324484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.3070324484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1441996140 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 285084082 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 05:30:23 AM UTC 24 |
| Finished | Sep 18 05:30:27 AM UTC 24 |
| Peak memory | 202896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441996140 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1441996140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.693964227 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 418079228 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 05:30:23 AM UTC 24 |
| Finished | Sep 18 05:30:26 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693964227 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.693964227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1419853951 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 36336067 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 05:30:27 AM UTC 24 |
| Finished | Sep 18 05:30:30 AM UTC 24 |
| Peak memory | 198868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1419853951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.1419853951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3906588436 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13621822 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 05:30:27 AM UTC 24 |
| Finished | Sep 18 05:30:29 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906588436 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3906588436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1254277303 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 42685560 ps |
| CPU time | 0.79 seconds |
| Started | Sep 18 05:30:27 AM UTC 24 |
| Finished | Sep 18 05:30:29 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254277303 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1254277303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1561662821 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 13670971 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 05:30:27 AM UTC 24 |
| Finished | Sep 18 05:30:29 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561662821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1561662821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.1670790459 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 167714227 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 05:30:25 AM UTC 24 |
| Finished | Sep 18 05:30:29 AM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670790459 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1670790459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1339109238 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 440394819 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 05:30:26 AM UTC 24 |
| Finished | Sep 18 05:30:29 AM UTC 24 |
| Peak memory | 200820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339109238 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.1339109238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.3257180578 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7393732020 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 04:46:17 AM UTC 24 |
| Finished | Sep 18 04:46:24 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257180578 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3257180578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.607541629 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 738238267722 ps |
| CPU time | 850.08 seconds |
| Started | Sep 18 04:46:17 AM UTC 24 |
| Finished | Sep 18 05:00:37 AM UTC 24 |
| Peak memory | 201056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607541629 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.607541629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.688945817 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 73729577759 ps |
| CPU time | 83.37 seconds |
| Started | Sep 18 04:46:17 AM UTC 24 |
| Finished | Sep 18 04:47:42 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688945817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.688945817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.3017241115 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 227018207126 ps |
| CPU time | 461.19 seconds |
| Started | Sep 18 04:46:21 AM UTC 24 |
| Finished | Sep 18 04:54:08 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017241115 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.3017241115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4272763561 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 612570744680 ps |
| CPU time | 327.47 seconds |
| Started | Sep 18 04:46:21 AM UTC 24 |
| Finished | Sep 18 04:51:53 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272763561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4272763561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.2099243764 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 124269361317 ps |
| CPU time | 486.54 seconds |
| Started | Sep 18 04:46:18 AM UTC 24 |
| Finished | Sep 18 04:54:31 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099243764 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2099243764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.2908307860 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 56926041449 ps |
| CPU time | 173.18 seconds |
| Started | Sep 18 04:46:21 AM UTC 24 |
| Finished | Sep 18 04:49:18 AM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908307860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2908307860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.689892285 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 55038646 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 04:46:22 AM UTC 24 |
| Finished | Sep 18 04:46:24 AM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689892285 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.689892285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.797000598 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 226326077717 ps |
| CPU time | 226.51 seconds |
| Started | Sep 18 04:46:22 AM UTC 24 |
| Finished | Sep 18 04:50:12 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797000598 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.797000598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.4219238875 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 416982142722 ps |
| CPU time | 564.23 seconds |
| Started | Sep 18 04:47:29 AM UTC 24 |
| Finished | Sep 18 04:57:00 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219238875 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.4219238875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.3463050769 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 810730692358 ps |
| CPU time | 268.75 seconds |
| Started | Sep 18 04:47:29 AM UTC 24 |
| Finished | Sep 18 04:52:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463050769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3463050769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.2875029082 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 20884789715 ps |
| CPU time | 12.44 seconds |
| Started | Sep 18 04:47:29 AM UTC 24 |
| Finished | Sep 18 04:47:43 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875029082 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2875029082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.797601865 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 16335082433 ps |
| CPU time | 20.53 seconds |
| Started | Sep 18 04:47:31 AM UTC 24 |
| Finished | Sep 18 04:47:53 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797601865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.797601865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1082631639 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 547361467407 ps |
| CPU time | 1762.15 seconds |
| Started | Sep 18 05:16:34 AM UTC 24 |
| Finished | Sep 18 05:46:15 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082631639 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1082631639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.1191598345 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 37554254212 ps |
| CPU time | 19.3 seconds |
| Started | Sep 18 05:16:37 AM UTC 24 |
| Finished | Sep 18 05:16:58 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191598345 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1191598345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.1884985100 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 261527411805 ps |
| CPU time | 183.15 seconds |
| Started | Sep 18 05:16:58 AM UTC 24 |
| Finished | Sep 18 05:20:04 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884985100 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1884985100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.1570080964 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 117342781284 ps |
| CPU time | 390.58 seconds |
| Started | Sep 18 05:17:41 AM UTC 24 |
| Finished | Sep 18 05:24:17 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570080964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1570080964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.2138275438 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 61595730720 ps |
| CPU time | 67.97 seconds |
| Started | Sep 18 04:47:41 AM UTC 24 |
| Finished | Sep 18 04:48:51 AM UTC 24 |
| Peak memory | 201216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138275438 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2138275438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.2753607415 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 258820891 ps |
| CPU time | 3.17 seconds |
| Started | Sep 18 04:47:41 AM UTC 24 |
| Finished | Sep 18 04:47:45 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753607415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2753607415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.2658715634 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 10570236204 ps |
| CPU time | 21.19 seconds |
| Started | Sep 18 05:17:59 AM UTC 24 |
| Finished | Sep 18 05:18:21 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658715634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2658715634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.2188964353 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 36424403463 ps |
| CPU time | 148.93 seconds |
| Started | Sep 18 05:18:01 AM UTC 24 |
| Finished | Sep 18 05:20:32 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188964353 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2188964353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.2502115261 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 21592770530 ps |
| CPU time | 16.21 seconds |
| Started | Sep 18 05:18:02 AM UTC 24 |
| Finished | Sep 18 05:18:19 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502115261 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2502115261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.778133877 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 276154963185 ps |
| CPU time | 1331.92 seconds |
| Started | Sep 18 05:18:08 AM UTC 24 |
| Finished | Sep 18 05:40:35 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778133877 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.778133877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.2933837502 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 54383515494 ps |
| CPU time | 140.17 seconds |
| Started | Sep 18 05:18:10 AM UTC 24 |
| Finished | Sep 18 05:20:33 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933837502 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2933837502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.1032193543 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 354116513075 ps |
| CPU time | 612.3 seconds |
| Started | Sep 18 05:18:11 AM UTC 24 |
| Finished | Sep 18 05:28:31 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032193543 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1032193543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.2940067686 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 380906881052 ps |
| CPU time | 548.21 seconds |
| Started | Sep 18 05:18:15 AM UTC 24 |
| Finished | Sep 18 05:27:30 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940067686 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2940067686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1039965089 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 95977199172 ps |
| CPU time | 78.82 seconds |
| Started | Sep 18 04:47:44 AM UTC 24 |
| Finished | Sep 18 04:49:04 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039965089 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1039965089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.54571282 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 419644751467 ps |
| CPU time | 189.67 seconds |
| Started | Sep 18 04:47:44 AM UTC 24 |
| Finished | Sep 18 04:50:56 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54571282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.54571282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.3505079896 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 517286738373 ps |
| CPU time | 445.8 seconds |
| Started | Sep 18 04:47:47 AM UTC 24 |
| Finished | Sep 18 04:55:18 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505079896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3505079896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.4265270455 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 607025363188 ps |
| CPU time | 461.72 seconds |
| Started | Sep 18 05:19:21 AM UTC 24 |
| Finished | Sep 18 05:27:08 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265270455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4265270455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1181269458 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 341809878825 ps |
| CPU time | 645.26 seconds |
| Started | Sep 18 05:19:22 AM UTC 24 |
| Finished | Sep 18 05:30:15 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181269458 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1181269458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.4145471366 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 43615543386 ps |
| CPU time | 495.36 seconds |
| Started | Sep 18 05:19:26 AM UTC 24 |
| Finished | Sep 18 05:27:48 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145471366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4145471366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.949791872 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 466301657828 ps |
| CPU time | 206.65 seconds |
| Started | Sep 18 05:19:30 AM UTC 24 |
| Finished | Sep 18 05:23:00 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949791872 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.949791872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3180098360 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 137102348858 ps |
| CPU time | 51.05 seconds |
| Started | Sep 18 05:20:05 AM UTC 24 |
| Finished | Sep 18 05:20:58 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180098360 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3180098360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.1232762383 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 260149470750 ps |
| CPU time | 612.48 seconds |
| Started | Sep 18 05:20:11 AM UTC 24 |
| Finished | Sep 18 05:30:32 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232762383 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1232762383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3978407419 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 97496335180 ps |
| CPU time | 126.06 seconds |
| Started | Sep 18 05:20:13 AM UTC 24 |
| Finished | Sep 18 05:22:22 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978407419 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3978407419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.2884437869 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 30410524593 ps |
| CPU time | 39.18 seconds |
| Started | Sep 18 05:20:33 AM UTC 24 |
| Finished | Sep 18 05:21:14 AM UTC 24 |
| Peak memory | 201248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884437869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2884437869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.617734097 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 129649672135 ps |
| CPU time | 71.27 seconds |
| Started | Sep 18 04:47:58 AM UTC 24 |
| Finished | Sep 18 04:49:11 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617734097 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.617734097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.4070458206 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 90053284669 ps |
| CPU time | 159.64 seconds |
| Started | Sep 18 04:47:54 AM UTC 24 |
| Finished | Sep 18 04:50:36 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070458206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4070458206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.267658094 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 13972234 ps |
| CPU time | 0.81 seconds |
| Started | Sep 18 04:47:59 AM UTC 24 |
| Finished | Sep 18 04:48:01 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267658094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.267658094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.984819149 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 295852220754 ps |
| CPU time | 274.64 seconds |
| Started | Sep 18 05:20:34 AM UTC 24 |
| Finished | Sep 18 05:25:12 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984819149 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.984819149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1662288380 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 109860199341 ps |
| CPU time | 2603.21 seconds |
| Started | Sep 18 05:20:35 AM UTC 24 |
| Finished | Sep 18 06:04:26 AM UTC 24 |
| Peak memory | 202688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662288380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1662288380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1123851128 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 43660207123 ps |
| CPU time | 108.89 seconds |
| Started | Sep 18 05:20:59 AM UTC 24 |
| Finished | Sep 18 05:22:50 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123851128 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1123851128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2252079486 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 58060272985 ps |
| CPU time | 76.95 seconds |
| Started | Sep 18 05:21:09 AM UTC 24 |
| Finished | Sep 18 05:22:28 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252079486 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2252079486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1196253725 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 441889052172 ps |
| CPU time | 389.08 seconds |
| Started | Sep 18 05:21:24 AM UTC 24 |
| Finished | Sep 18 05:27:58 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196253725 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1196253725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.3494970223 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 82775885215 ps |
| CPU time | 63.83 seconds |
| Started | Sep 18 05:21:28 AM UTC 24 |
| Finished | Sep 18 05:22:34 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494970223 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3494970223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.1382422977 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 122229959977 ps |
| CPU time | 263.15 seconds |
| Started | Sep 18 04:48:13 AM UTC 24 |
| Finished | Sep 18 04:52:39 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382422977 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.1382422977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.4256092451 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 101046229331 ps |
| CPU time | 102.08 seconds |
| Started | Sep 18 04:48:07 AM UTC 24 |
| Finished | Sep 18 04:49:50 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256092451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4256092451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.2673770815 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 15348039749 ps |
| CPU time | 12.87 seconds |
| Started | Sep 18 04:48:02 AM UTC 24 |
| Finished | Sep 18 04:48:16 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673770815 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2673770815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.1600855292 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 419716303 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 04:48:18 AM UTC 24 |
| Finished | Sep 18 04:48:20 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600855292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1600855292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.3541271186 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 653596311477 ps |
| CPU time | 831.4 seconds |
| Started | Sep 18 05:21:39 AM UTC 24 |
| Finished | Sep 18 05:35:41 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541271186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3541271186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.1831971261 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 554056865028 ps |
| CPU time | 848.82 seconds |
| Started | Sep 18 05:21:50 AM UTC 24 |
| Finished | Sep 18 05:36:10 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831971261 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1831971261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.3766881629 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 119065379289 ps |
| CPU time | 329.36 seconds |
| Started | Sep 18 05:22:23 AM UTC 24 |
| Finished | Sep 18 05:27:56 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766881629 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3766881629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.972225688 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 214600890225 ps |
| CPU time | 252.37 seconds |
| Started | Sep 18 05:22:29 AM UTC 24 |
| Finished | Sep 18 05:26:44 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972225688 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.972225688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.1062099571 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 11343181471 ps |
| CPU time | 45.89 seconds |
| Started | Sep 18 05:22:41 AM UTC 24 |
| Finished | Sep 18 05:23:28 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062099571 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1062099571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.3520440448 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 328303759097 ps |
| CPU time | 360.39 seconds |
| Started | Sep 18 05:22:42 AM UTC 24 |
| Finished | Sep 18 05:28:47 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520440448 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3520440448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2576693469 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 184483185625 ps |
| CPU time | 586.76 seconds |
| Started | Sep 18 05:22:50 AM UTC 24 |
| Finished | Sep 18 05:32:44 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576693469 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2576693469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.2283595492 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 591816203873 ps |
| CPU time | 1530.36 seconds |
| Started | Sep 18 05:22:51 AM UTC 24 |
| Finished | Sep 18 05:48:39 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283595492 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2283595492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.2872172520 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1022748066943 ps |
| CPU time | 1104.33 seconds |
| Started | Sep 18 04:48:51 AM UTC 24 |
| Finished | Sep 18 05:07:27 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872172520 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.2872172520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.3483573746 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 108110777911 ps |
| CPU time | 275.81 seconds |
| Started | Sep 18 04:48:31 AM UTC 24 |
| Finished | Sep 18 04:53:11 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483573746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3483573746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.2053784821 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 365025182543 ps |
| CPU time | 174.44 seconds |
| Started | Sep 18 04:48:30 AM UTC 24 |
| Finished | Sep 18 04:51:27 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053784821 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2053784821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.595116015 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 203263052 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 04:48:51 AM UTC 24 |
| Finished | Sep 18 04:48:53 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595116015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.595116015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.521331927 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1907570085230 ps |
| CPU time | 1073.18 seconds |
| Started | Sep 18 04:49:02 AM UTC 24 |
| Finished | Sep 18 05:07:07 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521331927 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.521331927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.718867003 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 100985190668 ps |
| CPU time | 349.97 seconds |
| Started | Sep 18 05:23:00 AM UTC 24 |
| Finished | Sep 18 05:28:55 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718867003 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.718867003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.3241477100 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 22157530161 ps |
| CPU time | 48.69 seconds |
| Started | Sep 18 05:23:11 AM UTC 24 |
| Finished | Sep 18 05:24:01 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241477100 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3241477100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1364762076 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 297092471538 ps |
| CPU time | 200.67 seconds |
| Started | Sep 18 05:23:12 AM UTC 24 |
| Finished | Sep 18 05:26:36 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364762076 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1364762076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.779390677 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 321357172861 ps |
| CPU time | 288.87 seconds |
| Started | Sep 18 05:23:29 AM UTC 24 |
| Finished | Sep 18 05:28:23 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779390677 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.779390677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.2569889471 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 58584734364 ps |
| CPU time | 111.33 seconds |
| Started | Sep 18 05:23:43 AM UTC 24 |
| Finished | Sep 18 05:25:36 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569889471 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2569889471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.3521001821 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 107660359303 ps |
| CPU time | 246.99 seconds |
| Started | Sep 18 05:24:02 AM UTC 24 |
| Finished | Sep 18 05:28:12 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521001821 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3521001821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.452635494 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 14064210761 ps |
| CPU time | 18.85 seconds |
| Started | Sep 18 05:24:02 AM UTC 24 |
| Finished | Sep 18 05:24:22 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452635494 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.452635494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3899350137 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 252822789028 ps |
| CPU time | 322.04 seconds |
| Started | Sep 18 05:24:07 AM UTC 24 |
| Finished | Sep 18 05:29:33 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899350137 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3899350137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2748874156 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 176419316712 ps |
| CPU time | 151.3 seconds |
| Started | Sep 18 04:49:04 AM UTC 24 |
| Finished | Sep 18 04:51:38 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748874156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2748874156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.42323655 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 153097718442 ps |
| CPU time | 2568.34 seconds |
| Started | Sep 18 04:49:02 AM UTC 24 |
| Finished | Sep 18 05:32:17 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42323655 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.42323655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.309962094 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 196296718028 ps |
| CPU time | 79.84 seconds |
| Started | Sep 18 04:49:10 AM UTC 24 |
| Finished | Sep 18 04:50:31 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309962094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.309962094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.2773890204 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1040219113609 ps |
| CPU time | 662.83 seconds |
| Started | Sep 18 04:49:13 AM UTC 24 |
| Finished | Sep 18 05:00:23 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773890204 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.2773890204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.1764745404 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 667452004091 ps |
| CPU time | 428.84 seconds |
| Started | Sep 18 05:24:18 AM UTC 24 |
| Finished | Sep 18 05:31:33 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764745404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1764745404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.1137207706 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 85950483812 ps |
| CPU time | 552.22 seconds |
| Started | Sep 18 05:24:39 AM UTC 24 |
| Finished | Sep 18 05:33:59 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137207706 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1137207706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2696229198 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 62717347367 ps |
| CPU time | 26.98 seconds |
| Started | Sep 18 05:25:13 AM UTC 24 |
| Finished | Sep 18 05:25:41 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696229198 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2696229198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2645202307 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 97010275533 ps |
| CPU time | 93.19 seconds |
| Started | Sep 18 05:25:37 AM UTC 24 |
| Finished | Sep 18 05:27:12 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645202307 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2645202307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.4066331320 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 956994423895 ps |
| CPU time | 238.5 seconds |
| Started | Sep 18 05:25:42 AM UTC 24 |
| Finished | Sep 18 05:29:44 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066331320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4066331320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.1992308529 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 94674523793 ps |
| CPU time | 72.61 seconds |
| Started | Sep 18 04:49:20 AM UTC 24 |
| Finished | Sep 18 04:50:34 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992308529 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1992308529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3016684301 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 401877975153 ps |
| CPU time | 285.95 seconds |
| Started | Sep 18 04:49:19 AM UTC 24 |
| Finished | Sep 18 04:54:09 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016684301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3016684301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3232981595 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 318165854019 ps |
| CPU time | 632.31 seconds |
| Started | Sep 18 04:49:22 AM UTC 24 |
| Finished | Sep 18 05:00:02 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232981595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3232981595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1912056570 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 228274878119 ps |
| CPU time | 918.34 seconds |
| Started | Sep 18 05:25:54 AM UTC 24 |
| Finished | Sep 18 05:41:24 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912056570 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1912056570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.4253390794 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5573600279 ps |
| CPU time | 145.87 seconds |
| Started | Sep 18 05:25:54 AM UTC 24 |
| Finished | Sep 18 05:28:23 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253390794 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4253390794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.232668828 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 77904122756 ps |
| CPU time | 135.12 seconds |
| Started | Sep 18 05:26:12 AM UTC 24 |
| Finished | Sep 18 05:28:29 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232668828 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.232668828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2419814743 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 101250846139 ps |
| CPU time | 219.58 seconds |
| Started | Sep 18 05:26:18 AM UTC 24 |
| Finished | Sep 18 05:30:01 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419814743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2419814743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.2890767872 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 121812754650 ps |
| CPU time | 461.07 seconds |
| Started | Sep 18 05:26:37 AM UTC 24 |
| Finished | Sep 18 05:34:24 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890767872 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2890767872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.2980733998 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 127623229553 ps |
| CPU time | 101.08 seconds |
| Started | Sep 18 05:26:40 AM UTC 24 |
| Finished | Sep 18 05:28:23 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980733998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2980733998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3135187314 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 61945050984 ps |
| CPU time | 68.61 seconds |
| Started | Sep 18 05:26:51 AM UTC 24 |
| Finished | Sep 18 05:28:02 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135187314 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3135187314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.2331477943 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 434673499441 ps |
| CPU time | 1738.11 seconds |
| Started | Sep 18 05:27:08 AM UTC 24 |
| Finished | Sep 18 05:56:26 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331477943 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2331477943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.508661754 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 119029987823 ps |
| CPU time | 292.72 seconds |
| Started | Sep 18 05:27:09 AM UTC 24 |
| Finished | Sep 18 05:32:05 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508661754 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.508661754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.1573359910 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5889839983 ps |
| CPU time | 16.99 seconds |
| Started | Sep 18 04:49:38 AM UTC 24 |
| Finished | Sep 18 04:49:56 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573359910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1573359910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.131714349 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 111385664679 ps |
| CPU time | 832.11 seconds |
| Started | Sep 18 04:49:46 AM UTC 24 |
| Finished | Sep 18 05:03:48 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131714349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.131714349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2481124595 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 330942772226 ps |
| CPU time | 349.81 seconds |
| Started | Sep 18 05:27:21 AM UTC 24 |
| Finished | Sep 18 05:33:15 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481124595 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2481124595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.44657508 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 495860652434 ps |
| CPU time | 689.16 seconds |
| Started | Sep 18 05:27:27 AM UTC 24 |
| Finished | Sep 18 05:39:05 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44657508 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.44657508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1996824708 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 59935694696 ps |
| CPU time | 108.77 seconds |
| Started | Sep 18 05:27:31 AM UTC 24 |
| Finished | Sep 18 05:29:22 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996824708 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1996824708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.4116484653 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 444647177863 ps |
| CPU time | 452.81 seconds |
| Started | Sep 18 05:27:36 AM UTC 24 |
| Finished | Sep 18 05:35:15 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116484653 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4116484653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.4202892715 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 543389987739 ps |
| CPU time | 766.84 seconds |
| Started | Sep 18 05:27:49 AM UTC 24 |
| Finished | Sep 18 05:40:45 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202892715 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4202892715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.315880066 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 171650396421 ps |
| CPU time | 360.19 seconds |
| Started | Sep 18 05:27:57 AM UTC 24 |
| Finished | Sep 18 05:34:02 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315880066 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.315880066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.2539180298 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 141968225577 ps |
| CPU time | 119.33 seconds |
| Started | Sep 18 05:27:59 AM UTC 24 |
| Finished | Sep 18 05:30:01 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539180298 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2539180298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.2452761769 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 443845855545 ps |
| CPU time | 304.84 seconds |
| Started | Sep 18 05:28:13 AM UTC 24 |
| Finished | Sep 18 05:33:22 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452761769 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2452761769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.330528259 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 97153739621 ps |
| CPU time | 62.47 seconds |
| Started | Sep 18 04:50:29 AM UTC 24 |
| Finished | Sep 18 04:51:33 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330528259 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.330528259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.3626607389 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 205778711267 ps |
| CPU time | 128.98 seconds |
| Started | Sep 18 04:50:13 AM UTC 24 |
| Finished | Sep 18 04:52:24 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626607389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3626607389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1325525990 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 140721057300 ps |
| CPU time | 324.59 seconds |
| Started | Sep 18 04:49:58 AM UTC 24 |
| Finished | Sep 18 04:55:27 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325525990 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1325525990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.1283530394 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29208153479 ps |
| CPU time | 69.95 seconds |
| Started | Sep 18 04:50:32 AM UTC 24 |
| Finished | Sep 18 04:51:44 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283530394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1283530394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all_with_rand_reset.1587678384 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6423336204 ps |
| CPU time | 86.4 seconds |
| Started | Sep 18 04:50:35 AM UTC 24 |
| Finished | Sep 18 04:52:03 AM UTC 24 |
| Peak memory | 205360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1587678384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.rv_timer_stress_all_with_rand_reset.1587678384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1187102200 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 7498077219 ps |
| CPU time | 22.25 seconds |
| Started | Sep 18 05:28:23 AM UTC 24 |
| Finished | Sep 18 05:28:47 AM UTC 24 |
| Peak memory | 200104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187102200 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1187102200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.3192742815 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 22916692995 ps |
| CPU time | 83.61 seconds |
| Started | Sep 18 05:28:23 AM UTC 24 |
| Finished | Sep 18 05:29:49 AM UTC 24 |
| Peak memory | 200132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192742815 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3192742815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.1650414925 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 122579185938 ps |
| CPU time | 103.8 seconds |
| Started | Sep 18 05:28:25 AM UTC 24 |
| Finished | Sep 18 05:30:10 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650414925 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1650414925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.1503686320 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 130602391618 ps |
| CPU time | 436.54 seconds |
| Started | Sep 18 05:28:32 AM UTC 24 |
| Finished | Sep 18 05:35:54 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503686320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1503686320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.2583370543 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 744984859672 ps |
| CPU time | 1209.94 seconds |
| Started | Sep 18 05:29:23 AM UTC 24 |
| Finished | Sep 18 05:49:46 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583370543 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2583370543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.1770289996 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 119653820088 ps |
| CPU time | 587.1 seconds |
| Started | Sep 18 05:29:32 AM UTC 24 |
| Finished | Sep 18 05:39:27 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770289996 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1770289996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3689249784 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 189178352580 ps |
| CPU time | 165.04 seconds |
| Started | Sep 18 04:46:25 AM UTC 24 |
| Finished | Sep 18 04:49:12 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689249784 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3689249784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.3894217552 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 342215962913 ps |
| CPU time | 262.78 seconds |
| Started | Sep 18 04:46:25 AM UTC 24 |
| Finished | Sep 18 04:50:51 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894217552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3894217552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1529501935 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 167235986966 ps |
| CPU time | 451.41 seconds |
| Started | Sep 18 04:46:24 AM UTC 24 |
| Finished | Sep 18 04:54:01 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529501935 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1529501935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3756847501 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 149664300418 ps |
| CPU time | 38.4 seconds |
| Started | Sep 18 04:46:25 AM UTC 24 |
| Finished | Sep 18 04:47:05 AM UTC 24 |
| Peak memory | 200924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756847501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3756847501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.2325229757 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 73248875 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 04:46:27 AM UTC 24 |
| Finished | Sep 18 04:46:29 AM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325229757 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2325229757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2307442524 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2062517190670 ps |
| CPU time | 746.58 seconds |
| Started | Sep 18 04:50:52 AM UTC 24 |
| Finished | Sep 18 05:03:27 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307442524 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2307442524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3366380858 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 93973281799 ps |
| CPU time | 134.92 seconds |
| Started | Sep 18 04:50:45 AM UTC 24 |
| Finished | Sep 18 04:53:02 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366380858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3366380858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.1982453235 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 382443449298 ps |
| CPU time | 358.02 seconds |
| Started | Sep 18 04:50:37 AM UTC 24 |
| Finished | Sep 18 04:56:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982453235 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1982453235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.3750784129 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1127890272 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 04:50:55 AM UTC 24 |
| Finished | Sep 18 04:50:58 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750784129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3750784129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.126091855 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 257364484664 ps |
| CPU time | 217.12 seconds |
| Started | Sep 18 04:51:09 AM UTC 24 |
| Finished | Sep 18 04:54:49 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126091855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.126091855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.210265608 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 77349505557 ps |
| CPU time | 584.82 seconds |
| Started | Sep 18 04:51:27 AM UTC 24 |
| Finished | Sep 18 05:01:18 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210265608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.210265608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.581383069 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1098262065928 ps |
| CPU time | 519.1 seconds |
| Started | Sep 18 04:51:28 AM UTC 24 |
| Finished | Sep 18 05:00:13 AM UTC 24 |
| Peak memory | 201216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581383069 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.581383069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.3732446680 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 21158770671 ps |
| CPU time | 70.12 seconds |
| Started | Sep 18 04:51:39 AM UTC 24 |
| Finished | Sep 18 04:52:51 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732446680 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.3732446680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.2534845833 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 414761597032 ps |
| CPU time | 495.48 seconds |
| Started | Sep 18 04:51:31 AM UTC 24 |
| Finished | Sep 18 04:59:52 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534845833 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2534845833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.961904045 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 961659859921 ps |
| CPU time | 2920.56 seconds |
| Started | Sep 18 04:51:54 AM UTC 24 |
| Finished | Sep 18 05:41:04 AM UTC 24 |
| Peak memory | 202900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961904045 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.961904045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all_with_rand_reset.281412552 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7020345973 ps |
| CPU time | 92.17 seconds |
| Started | Sep 18 04:51:51 AM UTC 24 |
| Finished | Sep 18 04:53:25 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=281412552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.281412552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.524120816 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 72537670250 ps |
| CPU time | 124.03 seconds |
| Started | Sep 18 04:52:25 AM UTC 24 |
| Finished | Sep 18 04:54:31 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524120816 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.524120816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.2889418333 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 168763751433 ps |
| CPU time | 136.43 seconds |
| Started | Sep 18 04:52:04 AM UTC 24 |
| Finished | Sep 18 04:54:22 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889418333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2889418333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.288533237 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 93585257850 ps |
| CPU time | 153.16 seconds |
| Started | Sep 18 04:52:02 AM UTC 24 |
| Finished | Sep 18 04:54:38 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288533237 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.288533237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.519572240 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 85739137846 ps |
| CPU time | 938.59 seconds |
| Started | Sep 18 04:52:30 AM UTC 24 |
| Finished | Sep 18 05:08:19 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519572240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.519572240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.3209525723 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 294431561380 ps |
| CPU time | 585.34 seconds |
| Started | Sep 18 04:53:10 AM UTC 24 |
| Finished | Sep 18 05:03:02 AM UTC 24 |
| Peak memory | 201028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209525723 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3209525723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.3766253729 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 167890851167 ps |
| CPU time | 147.19 seconds |
| Started | Sep 18 04:53:03 AM UTC 24 |
| Finished | Sep 18 04:55:33 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766253729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3766253729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.1516691336 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 384227246236 ps |
| CPU time | 1133.88 seconds |
| Started | Sep 18 04:52:58 AM UTC 24 |
| Finished | Sep 18 05:12:05 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516691336 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1516691336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.1214615895 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8397441585 ps |
| CPU time | 14.66 seconds |
| Started | Sep 18 04:53:10 AM UTC 24 |
| Finished | Sep 18 04:53:26 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214615895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1214615895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2959492842 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 970198777499 ps |
| CPU time | 594.63 seconds |
| Started | Sep 18 04:53:19 AM UTC 24 |
| Finished | Sep 18 05:03:21 AM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959492842 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.2959492842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.3343647637 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 73015627304 ps |
| CPU time | 189.67 seconds |
| Started | Sep 18 04:53:27 AM UTC 24 |
| Finished | Sep 18 04:56:39 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343647637 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3343647637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.4086947910 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 144520401861 ps |
| CPU time | 50.17 seconds |
| Started | Sep 18 04:53:27 AM UTC 24 |
| Finished | Sep 18 04:54:18 AM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086947910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4086947910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2068600908 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8618393833 ps |
| CPU time | 18.2 seconds |
| Started | Sep 18 04:53:27 AM UTC 24 |
| Finished | Sep 18 04:53:46 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068600908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2068600908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.4209797853 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6182616106 ps |
| CPU time | 20.33 seconds |
| Started | Sep 18 04:53:38 AM UTC 24 |
| Finished | Sep 18 04:53:59 AM UTC 24 |
| Peak memory | 205288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4209797853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.rv_timer_stress_all_with_rand_reset.4209797853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.168537939 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 50035006729 ps |
| CPU time | 81.63 seconds |
| Started | Sep 18 04:54:02 AM UTC 24 |
| Finished | Sep 18 04:55:25 AM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168537939 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.168537939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1731111328 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 612332599878 ps |
| CPU time | 365.54 seconds |
| Started | Sep 18 04:54:00 AM UTC 24 |
| Finished | Sep 18 05:00:10 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731111328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1731111328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.630856383 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 236215838057 ps |
| CPU time | 352.47 seconds |
| Started | Sep 18 04:53:53 AM UTC 24 |
| Finished | Sep 18 04:59:50 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630856383 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.630856383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1673926312 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 81130830979 ps |
| CPU time | 102.13 seconds |
| Started | Sep 18 04:54:09 AM UTC 24 |
| Finished | Sep 18 04:55:53 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673926312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1673926312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.1152588510 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 566535393670 ps |
| CPU time | 336.17 seconds |
| Started | Sep 18 04:54:31 AM UTC 24 |
| Finished | Sep 18 05:00:12 AM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152588510 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1152588510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.908277624 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 588204656587 ps |
| CPU time | 273.95 seconds |
| Started | Sep 18 04:54:23 AM UTC 24 |
| Finished | Sep 18 04:59:01 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908277624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.908277624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1753328677 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 195440111480 ps |
| CPU time | 327.85 seconds |
| Started | Sep 18 04:54:19 AM UTC 24 |
| Finished | Sep 18 04:59:52 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753328677 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1753328677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.1793116314 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 126258344464 ps |
| CPU time | 157.22 seconds |
| Started | Sep 18 04:54:32 AM UTC 24 |
| Finished | Sep 18 04:57:11 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793116314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1793116314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.4188167842 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 904321410518 ps |
| CPU time | 471.18 seconds |
| Started | Sep 18 04:55:19 AM UTC 24 |
| Finished | Sep 18 05:03:16 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188167842 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.4188167842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.1682849343 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 204430478431 ps |
| CPU time | 272.39 seconds |
| Started | Sep 18 04:55:01 AM UTC 24 |
| Finished | Sep 18 04:59:37 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682849343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1682849343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.944299420 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 103958617855 ps |
| CPU time | 67.28 seconds |
| Started | Sep 18 04:55:20 AM UTC 24 |
| Finished | Sep 18 04:56:29 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944299420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.944299420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.4193674275 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 119141569757 ps |
| CPU time | 107.02 seconds |
| Started | Sep 18 04:55:47 AM UTC 24 |
| Finished | Sep 18 04:57:37 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193674275 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.4193674275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.275979371 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 98824237621 ps |
| CPU time | 52.53 seconds |
| Started | Sep 18 04:55:36 AM UTC 24 |
| Finished | Sep 18 04:56:30 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275979371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.275979371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.3510448594 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1000167149525 ps |
| CPU time | 473.48 seconds |
| Started | Sep 18 04:55:33 AM UTC 24 |
| Finished | Sep 18 05:03:32 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510448594 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3510448594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.3296953540 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 49608560222 ps |
| CPU time | 90.5 seconds |
| Started | Sep 18 04:55:53 AM UTC 24 |
| Finished | Sep 18 04:57:25 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296953540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3296953540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.2821324540 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 158850420205 ps |
| CPU time | 860.68 seconds |
| Started | Sep 18 04:56:00 AM UTC 24 |
| Finished | Sep 18 05:10:30 AM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821324540 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.2821324540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.404124250 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3532639901 ps |
| CPU time | 35.46 seconds |
| Started | Sep 18 04:55:54 AM UTC 24 |
| Finished | Sep 18 04:56:30 AM UTC 24 |
| Peak memory | 205508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=404124250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.404124250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.2123654300 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 261908622915 ps |
| CPU time | 150.77 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:49:01 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123654300 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.2123654300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3755334715 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 74415898556 ps |
| CPU time | 140.67 seconds |
| Started | Sep 18 04:46:27 AM UTC 24 |
| Finished | Sep 18 04:48:50 AM UTC 24 |
| Peak memory | 201052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755334715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3755334715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.833691438 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 207716841081 ps |
| CPU time | 180.79 seconds |
| Started | Sep 18 04:46:27 AM UTC 24 |
| Finished | Sep 18 04:49:31 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833691438 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.833691438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.708043127 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 68709239826 ps |
| CPU time | 556.21 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:55:51 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708043127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.708043127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.3349850023 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 81393700 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:46:30 AM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349850023 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3349850023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.2579882205 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 231896280070 ps |
| CPU time | 607.73 seconds |
| Started | Sep 18 04:56:31 AM UTC 24 |
| Finished | Sep 18 05:06:46 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579882205 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2579882205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2825887447 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 66628398086 ps |
| CPU time | 143.38 seconds |
| Started | Sep 18 04:56:30 AM UTC 24 |
| Finished | Sep 18 04:58:56 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825887447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2825887447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3386428726 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 169299633645 ps |
| CPU time | 117.29 seconds |
| Started | Sep 18 04:56:07 AM UTC 24 |
| Finished | Sep 18 04:58:06 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386428726 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3386428726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.2585783290 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 9468585497 ps |
| CPU time | 8.02 seconds |
| Started | Sep 18 04:56:31 AM UTC 24 |
| Finished | Sep 18 04:56:40 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585783290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2585783290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.1141330427 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 28427658887 ps |
| CPU time | 35.32 seconds |
| Started | Sep 18 04:57:04 AM UTC 24 |
| Finished | Sep 18 04:57:41 AM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141330427 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1141330427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.2120237152 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 27679056146 ps |
| CPU time | 52.37 seconds |
| Started | Sep 18 04:57:01 AM UTC 24 |
| Finished | Sep 18 04:57:55 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120237152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2120237152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.3541007864 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 138464230804 ps |
| CPU time | 526.37 seconds |
| Started | Sep 18 04:56:41 AM UTC 24 |
| Finished | Sep 18 05:05:34 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541007864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3541007864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.3663794210 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 199056080676 ps |
| CPU time | 263.14 seconds |
| Started | Sep 18 04:57:07 AM UTC 24 |
| Finished | Sep 18 05:01:34 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663794210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3663794210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3925392456 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 289706168233 ps |
| CPU time | 855.72 seconds |
| Started | Sep 18 04:57:20 AM UTC 24 |
| Finished | Sep 18 05:11:45 AM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925392456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.3925392456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all_with_rand_reset.1649793808 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2233617919 ps |
| CPU time | 14.34 seconds |
| Started | Sep 18 04:57:13 AM UTC 24 |
| Finished | Sep 18 04:57:28 AM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1649793808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.rv_timer_stress_all_with_rand_reset.1649793808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.2712423142 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 145051573828 ps |
| CPU time | 299 seconds |
| Started | Sep 18 04:57:29 AM UTC 24 |
| Finished | Sep 18 05:02:32 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712423142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2712423142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.1478174848 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 182676386048 ps |
| CPU time | 167.97 seconds |
| Started | Sep 18 04:57:42 AM UTC 24 |
| Finished | Sep 18 05:00:33 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478174848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1478174848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.2652482632 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 584242927807 ps |
| CPU time | 1558.77 seconds |
| Started | Sep 18 04:57:45 AM UTC 24 |
| Finished | Sep 18 05:24:00 AM UTC 24 |
| Peak memory | 202968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652482632 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.2652482632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.2892825657 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 160729745291 ps |
| CPU time | 264.73 seconds |
| Started | Sep 18 04:58:23 AM UTC 24 |
| Finished | Sep 18 05:02:51 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892825657 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.2892825657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.3297429977 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 111416167341 ps |
| CPU time | 83.7 seconds |
| Started | Sep 18 04:58:07 AM UTC 24 |
| Finished | Sep 18 04:59:33 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297429977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3297429977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.3425771790 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 87426735705 ps |
| CPU time | 143.37 seconds |
| Started | Sep 18 04:57:56 AM UTC 24 |
| Finished | Sep 18 05:00:22 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425771790 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3425771790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.2300907645 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 114784880776 ps |
| CPU time | 571.99 seconds |
| Started | Sep 18 04:58:35 AM UTC 24 |
| Finished | Sep 18 05:08:14 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300907645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2300907645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2413318602 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 894067997488 ps |
| CPU time | 1047.46 seconds |
| Started | Sep 18 04:58:57 AM UTC 24 |
| Finished | Sep 18 05:16:36 AM UTC 24 |
| Peak memory | 200940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413318602 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.2413318602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1554335174 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 585407754083 ps |
| CPU time | 397.88 seconds |
| Started | Sep 18 04:59:03 AM UTC 24 |
| Finished | Sep 18 05:05:46 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554335174 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1554335174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.2250691079 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 429629585774 ps |
| CPU time | 296.31 seconds |
| Started | Sep 18 04:59:02 AM UTC 24 |
| Finished | Sep 18 05:04:02 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250691079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2250691079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.3770650846 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10912363309 ps |
| CPU time | 100.39 seconds |
| Started | Sep 18 04:59:33 AM UTC 24 |
| Finished | Sep 18 05:01:16 AM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770650846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3770650846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.2595329975 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3566331125 ps |
| CPU time | 47.31 seconds |
| Started | Sep 18 04:59:37 AM UTC 24 |
| Finished | Sep 18 05:00:26 AM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2595329975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.rv_timer_stress_all_with_rand_reset.2595329975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.2867292712 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1857623376847 ps |
| CPU time | 968.75 seconds |
| Started | Sep 18 05:00:06 AM UTC 24 |
| Finished | Sep 18 05:16:25 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867292712 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2867292712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.3444301814 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 477932768614 ps |
| CPU time | 220.63 seconds |
| Started | Sep 18 04:59:54 AM UTC 24 |
| Finished | Sep 18 05:03:37 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444301814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3444301814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.878379096 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 345417111626 ps |
| CPU time | 1277.75 seconds |
| Started | Sep 18 04:59:52 AM UTC 24 |
| Finished | Sep 18 05:21:24 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878379096 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.878379096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.873364731 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 244153652 ps |
| CPU time | 0.87 seconds |
| Started | Sep 18 05:00:11 AM UTC 24 |
| Finished | Sep 18 05:00:13 AM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873364731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.873364731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.82130296 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 99320983432 ps |
| CPU time | 105.24 seconds |
| Started | Sep 18 05:00:24 AM UTC 24 |
| Finished | Sep 18 05:02:11 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82130296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.82130296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2614371884 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 216558663342 ps |
| CPU time | 270.65 seconds |
| Started | Sep 18 05:00:23 AM UTC 24 |
| Finished | Sep 18 05:04:57 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614371884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2614371884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3301424422 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 128228040772 ps |
| CPU time | 481.44 seconds |
| Started | Sep 18 05:00:14 AM UTC 24 |
| Finished | Sep 18 05:08:21 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301424422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3301424422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.269358507 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 34550664849 ps |
| CPU time | 93.78 seconds |
| Started | Sep 18 05:00:27 AM UTC 24 |
| Finished | Sep 18 05:02:03 AM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269358507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.269358507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all_with_rand_reset.1647439375 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2507560185 ps |
| CPU time | 34.09 seconds |
| Started | Sep 18 05:00:33 AM UTC 24 |
| Finished | Sep 18 05:01:09 AM UTC 24 |
| Peak memory | 205228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1647439375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.rv_timer_stress_all_with_rand_reset.1647439375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.780769249 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 26689484442 ps |
| CPU time | 43.28 seconds |
| Started | Sep 18 05:01:10 AM UTC 24 |
| Finished | Sep 18 05:01:54 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780769249 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.780769249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.481213312 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 68558450541 ps |
| CPU time | 105.62 seconds |
| Started | Sep 18 05:00:38 AM UTC 24 |
| Finished | Sep 18 05:02:26 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481213312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.481213312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.2086044435 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 331787629613 ps |
| CPU time | 260.92 seconds |
| Started | Sep 18 05:00:37 AM UTC 24 |
| Finished | Sep 18 05:05:02 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086044435 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2086044435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2779125843 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 117324279374 ps |
| CPU time | 203.22 seconds |
| Started | Sep 18 05:01:17 AM UTC 24 |
| Finished | Sep 18 05:04:43 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779125843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2779125843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1009549627 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 251822438716 ps |
| CPU time | 205.8 seconds |
| Started | Sep 18 05:01:35 AM UTC 24 |
| Finished | Sep 18 05:05:03 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009549627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1009549627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.3644762008 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 6527177707 ps |
| CPU time | 21.2 seconds |
| Started | Sep 18 05:01:55 AM UTC 24 |
| Finished | Sep 18 05:02:17 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644762008 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.3644762008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.1584214467 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29147747083 ps |
| CPU time | 23.88 seconds |
| Started | Sep 18 05:01:45 AM UTC 24 |
| Finished | Sep 18 05:02:10 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584214467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1584214467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.1646602208 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 56445670573 ps |
| CPU time | 178.65 seconds |
| Started | Sep 18 05:01:42 AM UTC 24 |
| Finished | Sep 18 05:04:43 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646602208 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1646602208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.1470142628 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 726680129110 ps |
| CPU time | 175.24 seconds |
| Started | Sep 18 05:02:04 AM UTC 24 |
| Finished | Sep 18 05:05:02 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470142628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1470142628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.3504094744 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 152115825069 ps |
| CPU time | 322.38 seconds |
| Started | Sep 18 05:02:26 AM UTC 24 |
| Finished | Sep 18 05:07:53 AM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504094744 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3504094744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.265137077 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 128768419797 ps |
| CPU time | 216.95 seconds |
| Started | Sep 18 05:02:18 AM UTC 24 |
| Finished | Sep 18 05:05:58 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265137077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.265137077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.2151531288 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 32089035047 ps |
| CPU time | 110.39 seconds |
| Started | Sep 18 05:02:15 AM UTC 24 |
| Finished | Sep 18 05:04:08 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151531288 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2151531288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.643602513 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 53481920441 ps |
| CPU time | 132.39 seconds |
| Started | Sep 18 05:02:33 AM UTC 24 |
| Finished | Sep 18 05:04:47 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643602513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.643602513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.339439994 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 390205341929 ps |
| CPU time | 911.74 seconds |
| Started | Sep 18 05:02:55 AM UTC 24 |
| Finished | Sep 18 05:18:17 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339439994 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.339439994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.177768093 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 245837556450 ps |
| CPU time | 262.65 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:50:55 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177768093 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.177768093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.1132519086 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 102052495882 ps |
| CPU time | 174.07 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:49:25 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132519086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1132519086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.3679465686 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 40476374307 ps |
| CPU time | 78.71 seconds |
| Started | Sep 18 04:46:28 AM UTC 24 |
| Finished | Sep 18 04:47:49 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679465686 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3679465686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.1250342067 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 95983703721 ps |
| CPU time | 184.88 seconds |
| Started | Sep 18 04:46:29 AM UTC 24 |
| Finished | Sep 18 04:49:37 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250342067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1250342067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.1298006808 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 70113780 ps |
| CPU time | 1 seconds |
| Started | Sep 18 04:46:36 AM UTC 24 |
| Finished | Sep 18 04:46:38 AM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298006808 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1298006808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3931120965 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1011234440592 ps |
| CPU time | 492.7 seconds |
| Started | Sep 18 05:03:18 AM UTC 24 |
| Finished | Sep 18 05:11:37 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931120965 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3931120965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.748300089 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 124707532302 ps |
| CPU time | 237.43 seconds |
| Started | Sep 18 05:03:17 AM UTC 24 |
| Finished | Sep 18 05:07:18 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748300089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.748300089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1811855509 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 45485948396 ps |
| CPU time | 396.35 seconds |
| Started | Sep 18 05:03:22 AM UTC 24 |
| Finished | Sep 18 05:10:04 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811855509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1811855509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.1468596713 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 533464023472 ps |
| CPU time | 554.4 seconds |
| Started | Sep 18 05:03:33 AM UTC 24 |
| Finished | Sep 18 05:12:54 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468596713 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.1468596713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.823175862 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3410837207 ps |
| CPU time | 36.29 seconds |
| Started | Sep 18 05:03:28 AM UTC 24 |
| Finished | Sep 18 05:04:06 AM UTC 24 |
| Peak memory | 205560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=823175862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.823175862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3283598347 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 7691334077 ps |
| CPU time | 19.92 seconds |
| Started | Sep 18 05:03:48 AM UTC 24 |
| Finished | Sep 18 05:04:10 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283598347 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3283598347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.2146326535 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 296049277068 ps |
| CPU time | 66.76 seconds |
| Started | Sep 18 05:03:38 AM UTC 24 |
| Finished | Sep 18 05:04:47 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146326535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2146326535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.588952087 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 145916559170 ps |
| CPU time | 58.14 seconds |
| Started | Sep 18 05:03:33 AM UTC 24 |
| Finished | Sep 18 05:04:33 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588952087 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.588952087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2179881421 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 174853331327 ps |
| CPU time | 1378.55 seconds |
| Started | Sep 18 05:04:07 AM UTC 24 |
| Finished | Sep 18 05:27:20 AM UTC 24 |
| Peak memory | 203032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179881421 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2179881421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.2148464166 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 85292106609 ps |
| CPU time | 132.72 seconds |
| Started | Sep 18 05:04:23 AM UTC 24 |
| Finished | Sep 18 05:06:38 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148464166 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2148464166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3959711398 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 204663021459 ps |
| CPU time | 317.88 seconds |
| Started | Sep 18 05:04:11 AM UTC 24 |
| Finished | Sep 18 05:09:32 AM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959711398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3959711398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.2574768409 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 23797413400 ps |
| CPU time | 65.93 seconds |
| Started | Sep 18 05:04:09 AM UTC 24 |
| Finished | Sep 18 05:05:16 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574768409 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2574768409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.4113629553 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 46653699315 ps |
| CPU time | 83.82 seconds |
| Started | Sep 18 05:04:34 AM UTC 24 |
| Finished | Sep 18 05:05:59 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113629553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4113629553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.1187567392 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 493921222579 ps |
| CPU time | 2307.28 seconds |
| Started | Sep 18 05:04:44 AM UTC 24 |
| Finished | Sep 18 05:43:34 AM UTC 24 |
| Peak memory | 202908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187567392 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.1187567392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all_with_rand_reset.4256002934 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1556190038 ps |
| CPU time | 21.21 seconds |
| Started | Sep 18 05:04:43 AM UTC 24 |
| Finished | Sep 18 05:05:06 AM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4256002934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.rv_timer_stress_all_with_rand_reset.4256002934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.4025324109 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 145336402652 ps |
| CPU time | 184.12 seconds |
| Started | Sep 18 05:04:48 AM UTC 24 |
| Finished | Sep 18 05:07:55 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025324109 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.4025324109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.1288852156 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 108523810377 ps |
| CPU time | 62.62 seconds |
| Started | Sep 18 05:04:47 AM UTC 24 |
| Finished | Sep 18 05:05:52 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288852156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1288852156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.1733344173 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 210421598502 ps |
| CPU time | 102.01 seconds |
| Started | Sep 18 05:04:44 AM UTC 24 |
| Finished | Sep 18 05:06:28 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733344173 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1733344173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.1443335124 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 560832911 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 05:04:56 AM UTC 24 |
| Finished | Sep 18 05:05:00 AM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443335124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1443335124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2065780964 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2312673535401 ps |
| CPU time | 355.75 seconds |
| Started | Sep 18 05:05:01 AM UTC 24 |
| Finished | Sep 18 05:11:01 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065780964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.2065780964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.163249842 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 90064874117 ps |
| CPU time | 170.91 seconds |
| Started | Sep 18 05:05:04 AM UTC 24 |
| Finished | Sep 18 05:07:57 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163249842 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.163249842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3095398993 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 142076719073 ps |
| CPU time | 74.87 seconds |
| Started | Sep 18 05:05:03 AM UTC 24 |
| Finished | Sep 18 05:06:19 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095398993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3095398993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.2670305049 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 68135634646 ps |
| CPU time | 99.01 seconds |
| Started | Sep 18 05:05:03 AM UTC 24 |
| Finished | Sep 18 05:06:43 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670305049 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2670305049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.1375904169 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 259518258993 ps |
| CPU time | 142.58 seconds |
| Started | Sep 18 05:05:07 AM UTC 24 |
| Finished | Sep 18 05:07:32 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375904169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1375904169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.3700575336 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4143235400 ps |
| CPU time | 80.38 seconds |
| Started | Sep 18 05:05:07 AM UTC 24 |
| Finished | Sep 18 05:06:29 AM UTC 24 |
| Peak memory | 205288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3700575336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.rv_timer_stress_all_with_rand_reset.3700575336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1146530186 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 420434671902 ps |
| CPU time | 169.46 seconds |
| Started | Sep 18 05:05:47 AM UTC 24 |
| Finished | Sep 18 05:08:39 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146530186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1146530186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1145859515 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 28848451533 ps |
| CPU time | 89.58 seconds |
| Started | Sep 18 05:05:57 AM UTC 24 |
| Finished | Sep 18 05:07:29 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145859515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1145859515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2243458339 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 793378922831 ps |
| CPU time | 522.08 seconds |
| Started | Sep 18 05:06:30 AM UTC 24 |
| Finished | Sep 18 05:15:18 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243458339 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2243458339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.3947226260 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 265983541854 ps |
| CPU time | 156.98 seconds |
| Started | Sep 18 05:06:30 AM UTC 24 |
| Finished | Sep 18 05:09:09 AM UTC 24 |
| Peak memory | 201040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947226260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3947226260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.1736995973 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 379310160875 ps |
| CPU time | 567.27 seconds |
| Started | Sep 18 05:06:20 AM UTC 24 |
| Finished | Sep 18 05:15:54 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736995973 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1736995973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.2777804486 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 62695402269 ps |
| CPU time | 557.74 seconds |
| Started | Sep 18 05:06:39 AM UTC 24 |
| Finished | Sep 18 05:16:04 AM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777804486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2777804486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1527660181 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 68946216638 ps |
| CPU time | 32.38 seconds |
| Started | Sep 18 05:06:47 AM UTC 24 |
| Finished | Sep 18 05:07:21 AM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527660181 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1527660181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all_with_rand_reset.2237835712 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 672107443 ps |
| CPU time | 8.55 seconds |
| Started | Sep 18 05:06:44 AM UTC 24 |
| Finished | Sep 18 05:06:54 AM UTC 24 |
| Peak memory | 203176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2237835712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.rv_timer_stress_all_with_rand_reset.2237835712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.4226646185 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 394127771537 ps |
| CPU time | 626.96 seconds |
| Started | Sep 18 05:07:08 AM UTC 24 |
| Finished | Sep 18 05:17:41 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226646185 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.4226646185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2955526211 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 358579277780 ps |
| CPU time | 266.83 seconds |
| Started | Sep 18 05:06:55 AM UTC 24 |
| Finished | Sep 18 05:11:25 AM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955526211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2955526211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.4021585534 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 71463097590 ps |
| CPU time | 113.25 seconds |
| Started | Sep 18 05:06:51 AM UTC 24 |
| Finished | Sep 18 05:08:47 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021585534 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4021585534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.3029295209 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 302462149 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 05:07:11 AM UTC 24 |
| Finished | Sep 18 05:07:15 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029295209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3029295209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.841208310 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 448623320910 ps |
| CPU time | 507.63 seconds |
| Started | Sep 18 05:07:28 AM UTC 24 |
| Finished | Sep 18 05:16:01 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841208310 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.841208310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.3771203329 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 572556325432 ps |
| CPU time | 195.76 seconds |
| Started | Sep 18 05:07:25 AM UTC 24 |
| Finished | Sep 18 05:10:43 AM UTC 24 |
| Peak memory | 201212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771203329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3771203329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2036784060 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 990590200626 ps |
| CPU time | 278.3 seconds |
| Started | Sep 18 05:07:21 AM UTC 24 |
| Finished | Sep 18 05:12:03 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036784060 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2036784060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.2109817514 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 8236052686 ps |
| CPU time | 33.05 seconds |
| Started | Sep 18 05:07:30 AM UTC 24 |
| Finished | Sep 18 05:08:04 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109817514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2109817514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all_with_rand_reset.2989081689 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1226513076 ps |
| CPU time | 20.55 seconds |
| Started | Sep 18 05:07:33 AM UTC 24 |
| Finished | Sep 18 05:07:54 AM UTC 24 |
| Peak memory | 205552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2989081689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.rv_timer_stress_all_with_rand_reset.2989081689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3310224506 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1688813425716 ps |
| CPU time | 1163.95 seconds |
| Started | Sep 18 05:07:58 AM UTC 24 |
| Finished | Sep 18 05:27:35 AM UTC 24 |
| Peak memory | 202616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310224506 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3310224506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.1628117619 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 260900634798 ps |
| CPU time | 341.55 seconds |
| Started | Sep 18 05:07:56 AM UTC 24 |
| Finished | Sep 18 05:13:42 AM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628117619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1628117619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.3007098712 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 70998622352 ps |
| CPU time | 185.91 seconds |
| Started | Sep 18 05:08:01 AM UTC 24 |
| Finished | Sep 18 05:11:10 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007098712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3007098712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.3077140634 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 438718199458 ps |
| CPU time | 589.71 seconds |
| Started | Sep 18 05:08:14 AM UTC 24 |
| Finished | Sep 18 05:18:09 AM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077140634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.3077140634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.2177422150 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 73045606305 ps |
| CPU time | 165.21 seconds |
| Started | Sep 18 04:46:39 AM UTC 24 |
| Finished | Sep 18 04:49:27 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177422150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2177422150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.2639838792 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 346129082652 ps |
| CPU time | 237.54 seconds |
| Started | Sep 18 04:46:36 AM UTC 24 |
| Finished | Sep 18 04:50:37 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639838792 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2639838792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.1451648669 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 227466716989 ps |
| CPU time | 240.56 seconds |
| Started | Sep 18 04:46:40 AM UTC 24 |
| Finished | Sep 18 04:50:44 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451648669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1451648669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.831395332 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1077547804055 ps |
| CPU time | 333.87 seconds |
| Started | Sep 18 04:46:51 AM UTC 24 |
| Finished | Sep 18 04:52:29 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831395332 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.831395332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.575874762 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 516978574301 ps |
| CPU time | 98.19 seconds |
| Started | Sep 18 05:08:19 AM UTC 24 |
| Finished | Sep 18 05:10:00 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575874762 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.575874762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2254647951 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 296111129950 ps |
| CPU time | 355.09 seconds |
| Started | Sep 18 05:08:20 AM UTC 24 |
| Finished | Sep 18 05:14:21 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254647951 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2254647951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2955588026 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1786738002658 ps |
| CPU time | 786.85 seconds |
| Started | Sep 18 05:08:22 AM UTC 24 |
| Finished | Sep 18 05:21:39 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955588026 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2955588026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.1656396563 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 708803750602 ps |
| CPU time | 282.5 seconds |
| Started | Sep 18 05:08:30 AM UTC 24 |
| Finished | Sep 18 05:13:16 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656396563 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1656396563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3514544193 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 169599980831 ps |
| CPU time | 175.35 seconds |
| Started | Sep 18 05:08:42 AM UTC 24 |
| Finished | Sep 18 05:11:40 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514544193 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3514544193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.434723862 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 65286651121 ps |
| CPU time | 161.64 seconds |
| Started | Sep 18 05:09:10 AM UTC 24 |
| Finished | Sep 18 05:11:54 AM UTC 24 |
| Peak memory | 201204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434723862 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.434723862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.3721924330 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 133361774747 ps |
| CPU time | 1548.07 seconds |
| Started | Sep 18 05:09:33 AM UTC 24 |
| Finished | Sep 18 05:35:38 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721924330 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3721924330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.3416595459 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 39043810353 ps |
| CPU time | 23.21 seconds |
| Started | Sep 18 04:46:59 AM UTC 24 |
| Finished | Sep 18 04:47:24 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416595459 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3416595459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1013683372 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 178360776151 ps |
| CPU time | 30.09 seconds |
| Started | Sep 18 04:46:57 AM UTC 24 |
| Finished | Sep 18 04:47:29 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013683372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1013683372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.2085061874 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 74933239813 ps |
| CPU time | 133.78 seconds |
| Started | Sep 18 04:46:53 AM UTC 24 |
| Finished | Sep 18 04:49:09 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085061874 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2085061874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3312708408 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 55146262121 ps |
| CPU time | 595.28 seconds |
| Started | Sep 18 04:47:00 AM UTC 24 |
| Finished | Sep 18 04:57:04 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312708408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3312708408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1368193043 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 500984668297 ps |
| CPU time | 488.54 seconds |
| Started | Sep 18 04:47:05 AM UTC 24 |
| Finished | Sep 18 04:55:19 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368193043 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1368193043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.3430758734 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 91739502835 ps |
| CPU time | 217.22 seconds |
| Started | Sep 18 05:10:04 AM UTC 24 |
| Finished | Sep 18 05:13:45 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430758734 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3430758734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.3203697581 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 105143611813 ps |
| CPU time | 1127.25 seconds |
| Started | Sep 18 05:10:31 AM UTC 24 |
| Finished | Sep 18 05:29:31 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203697581 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3203697581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.40866242 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 110480766785 ps |
| CPU time | 408.38 seconds |
| Started | Sep 18 05:10:44 AM UTC 24 |
| Finished | Sep 18 05:17:37 AM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40866242 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.40866242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3967806179 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 35539947405 ps |
| CPU time | 44.88 seconds |
| Started | Sep 18 05:10:48 AM UTC 24 |
| Finished | Sep 18 05:11:34 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967806179 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3967806179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2197851562 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 496969782862 ps |
| CPU time | 413.11 seconds |
| Started | Sep 18 05:11:02 AM UTC 24 |
| Finished | Sep 18 05:18:00 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197851562 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2197851562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1872771429 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 760852792028 ps |
| CPU time | 2001.58 seconds |
| Started | Sep 18 05:11:16 AM UTC 24 |
| Finished | Sep 18 05:44:59 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872771429 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1872771429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.3141544609 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 441645694425 ps |
| CPU time | 477.15 seconds |
| Started | Sep 18 05:11:26 AM UTC 24 |
| Finished | Sep 18 05:19:30 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141544609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3141544609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.3130989029 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 70934271035 ps |
| CPU time | 127.76 seconds |
| Started | Sep 18 04:47:09 AM UTC 24 |
| Finished | Sep 18 04:49:19 AM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130989029 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3130989029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.228152794 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 211203732281 ps |
| CPU time | 131.3 seconds |
| Started | Sep 18 04:47:08 AM UTC 24 |
| Finished | Sep 18 04:49:21 AM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228152794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.228152794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.3472670638 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 848911920384 ps |
| CPU time | 252.58 seconds |
| Started | Sep 18 04:47:06 AM UTC 24 |
| Finished | Sep 18 04:51:22 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472670638 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3472670638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.692048620 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 43317276915 ps |
| CPU time | 76.76 seconds |
| Started | Sep 18 04:47:10 AM UTC 24 |
| Finished | Sep 18 04:48:28 AM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692048620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.692048620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2692614571 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 444439626969 ps |
| CPU time | 370.57 seconds |
| Started | Sep 18 04:47:10 AM UTC 24 |
| Finished | Sep 18 04:53:25 AM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692614571 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2692614571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.2455101910 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 648228258427 ps |
| CPU time | 1101.74 seconds |
| Started | Sep 18 05:11:34 AM UTC 24 |
| Finished | Sep 18 05:30:08 AM UTC 24 |
| Peak memory | 202764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455101910 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2455101910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.2872645599 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 681562966327 ps |
| CPU time | 363.97 seconds |
| Started | Sep 18 05:11:37 AM UTC 24 |
| Finished | Sep 18 05:17:46 AM UTC 24 |
| Peak memory | 201204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872645599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2872645599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3310394952 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 232905318368 ps |
| CPU time | 678.44 seconds |
| Started | Sep 18 05:11:45 AM UTC 24 |
| Finished | Sep 18 05:23:11 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310394952 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3310394952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.2568445098 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 143885077739 ps |
| CPU time | 439.93 seconds |
| Started | Sep 18 05:11:55 AM UTC 24 |
| Finished | Sep 18 05:19:20 AM UTC 24 |
| Peak memory | 201332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568445098 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2568445098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.873875690 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 41545170798 ps |
| CPU time | 63.35 seconds |
| Started | Sep 18 05:12:06 AM UTC 24 |
| Finished | Sep 18 05:13:10 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873875690 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.873875690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.2240001890 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 99043987731 ps |
| CPU time | 239.17 seconds |
| Started | Sep 18 05:12:08 AM UTC 24 |
| Finished | Sep 18 05:16:10 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240001890 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2240001890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.409663601 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 156524288800 ps |
| CPU time | 119.48 seconds |
| Started | Sep 18 05:12:48 AM UTC 24 |
| Finished | Sep 18 05:14:50 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409663601 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.409663601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1367422848 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 114826579579 ps |
| CPU time | 825.5 seconds |
| Started | Sep 18 05:12:55 AM UTC 24 |
| Finished | Sep 18 05:26:50 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367422848 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1367422848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.4155862090 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 52172034745 ps |
| CPU time | 154.75 seconds |
| Started | Sep 18 04:47:15 AM UTC 24 |
| Finished | Sep 18 04:49:53 AM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155862090 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.4155862090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.1521342467 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 384753726962 ps |
| CPU time | 147.46 seconds |
| Started | Sep 18 04:47:14 AM UTC 24 |
| Finished | Sep 18 04:49:44 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521342467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1521342467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.1342759286 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 65308580418 ps |
| CPU time | 39.59 seconds |
| Started | Sep 18 04:47:16 AM UTC 24 |
| Finished | Sep 18 04:47:58 AM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342759286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1342759286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.3705511569 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 584465598363 ps |
| CPU time | 786.94 seconds |
| Started | Sep 18 04:47:19 AM UTC 24 |
| Finished | Sep 18 05:00:34 AM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705511569 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.3705511569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.3376326339 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 377774284861 ps |
| CPU time | 536.48 seconds |
| Started | Sep 18 05:13:05 AM UTC 24 |
| Finished | Sep 18 05:22:08 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376326339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3376326339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3439094507 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 80745209646 ps |
| CPU time | 469.96 seconds |
| Started | Sep 18 05:13:12 AM UTC 24 |
| Finished | Sep 18 05:21:08 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439094507 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3439094507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.1211118791 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 291635720669 ps |
| CPU time | 486.8 seconds |
| Started | Sep 18 05:13:17 AM UTC 24 |
| Finished | Sep 18 05:21:30 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211118791 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1211118791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.3400387679 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6020392860 ps |
| CPU time | 17.35 seconds |
| Started | Sep 18 05:13:45 AM UTC 24 |
| Finished | Sep 18 05:14:04 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400387679 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3400387679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.336092303 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 139346884590 ps |
| CPU time | 1881.38 seconds |
| Started | Sep 18 05:14:05 AM UTC 24 |
| Finished | Sep 18 05:45:47 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336092303 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.336092303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.2999876071 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 208846672627 ps |
| CPU time | 1491.82 seconds |
| Started | Sep 18 05:14:12 AM UTC 24 |
| Finished | Sep 18 05:39:20 AM UTC 24 |
| Peak memory | 202692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999876071 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2999876071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.2317083646 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 59640784523 ps |
| CPU time | 36.94 seconds |
| Started | Sep 18 05:14:22 AM UTC 24 |
| Finished | Sep 18 05:15:00 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317083646 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2317083646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.3408836001 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 257557526734 ps |
| CPU time | 242.16 seconds |
| Started | Sep 18 04:47:21 AM UTC 24 |
| Finished | Sep 18 04:51:26 AM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408836001 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.3408836001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.4195397168 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 495490839145 ps |
| CPU time | 352.88 seconds |
| Started | Sep 18 04:47:21 AM UTC 24 |
| Finished | Sep 18 04:53:18 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195397168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4195397168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2394692783 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 343566328107 ps |
| CPU time | 1031.88 seconds |
| Started | Sep 18 04:47:20 AM UTC 24 |
| Finished | Sep 18 05:04:43 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394692783 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2394692783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.3096266409 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 658345857 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 04:47:25 AM UTC 24 |
| Finished | Sep 18 04:47:28 AM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096266409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3096266409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.4003126994 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 580706576138 ps |
| CPU time | 1242.45 seconds |
| Started | Sep 18 04:47:25 AM UTC 24 |
| Finished | Sep 18 05:08:20 AM UTC 24 |
| Peak memory | 202900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003126994 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.4003126994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.3389684243 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 85910277880 ps |
| CPU time | 201.72 seconds |
| Started | Sep 18 05:14:33 AM UTC 24 |
| Finished | Sep 18 05:17:58 AM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389684243 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3389684243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2323510259 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 87981623869 ps |
| CPU time | 492.99 seconds |
| Started | Sep 18 05:14:51 AM UTC 24 |
| Finished | Sep 18 05:23:10 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323510259 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2323510259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2507937355 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 224705389477 ps |
| CPU time | 1144.88 seconds |
| Started | Sep 18 05:15:19 AM UTC 24 |
| Finished | Sep 18 05:34:36 AM UTC 24 |
| Peak memory | 202700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507937355 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2507937355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.105182393 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 171530332976 ps |
| CPU time | 142.4 seconds |
| Started | Sep 18 05:15:49 AM UTC 24 |
| Finished | Sep 18 05:18:14 AM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105182393 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.105182393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.766728554 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 92292298175 ps |
| CPU time | 125.08 seconds |
| Started | Sep 18 05:15:54 AM UTC 24 |
| Finished | Sep 18 05:18:01 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766728554 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.766728554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.410795498 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 138448682515 ps |
| CPU time | 578.96 seconds |
| Started | Sep 18 05:16:02 AM UTC 24 |
| Finished | Sep 18 05:25:47 AM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410795498 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.410795498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.529986795 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 33166702904 ps |
| CPU time | 145.77 seconds |
| Started | Sep 18 05:16:05 AM UTC 24 |
| Finished | Sep 18 05:18:33 AM UTC 24 |
| Peak memory | 201140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529986795 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.529986795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.1404870518 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 475927922184 ps |
| CPU time | 1315.17 seconds |
| Started | Sep 18 05:16:11 AM UTC 24 |
| Finished | Sep 18 05:38:20 AM UTC 24 |
| Peak memory | 202956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404870518 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1404870518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/rv_timer-sim-vcs/99.rv_timer_random/latest |
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