| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.63 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.43 |
| T505 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3827808424 | Oct 09 10:41:26 PM UTC 24 | Oct 09 10:41:29 PM UTC 24 | 51219551 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3855002506 | Oct 09 10:41:27 PM UTC 24 | Oct 09 10:41:29 PM UTC 24 | 73135918 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2476384940 | Oct 09 10:41:25 PM UTC 24 | Oct 09 10:41:29 PM UTC 24 | 326007160 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1355339752 | Oct 09 10:41:28 PM UTC 24 | Oct 09 10:41:30 PM UTC 24 | 18357706 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.4115013635 | Oct 09 10:41:29 PM UTC 24 | Oct 09 10:41:31 PM UTC 24 | 97691413 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2719212353 | Oct 09 10:41:28 PM UTC 24 | Oct 09 10:41:31 PM UTC 24 | 269678066 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2746189454 | Oct 09 10:41:29 PM UTC 24 | Oct 09 10:41:31 PM UTC 24 | 18321009 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.2310220438 | Oct 09 10:41:27 PM UTC 24 | Oct 09 10:41:32 PM UTC 24 | 694810859 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1929820770 | Oct 09 10:41:30 PM UTC 24 | Oct 09 10:41:33 PM UTC 24 | 42914757 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3739331987 | Oct 09 10:41:30 PM UTC 24 | Oct 09 10:41:33 PM UTC 24 | 75483997 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1734795618 | Oct 09 10:41:32 PM UTC 24 | Oct 09 10:41:33 PM UTC 24 | 36716438 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.518842732 | Oct 09 10:41:32 PM UTC 24 | Oct 09 10:41:34 PM UTC 24 | 46549291 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3746351713 | Oct 09 10:41:32 PM UTC 24 | Oct 09 10:41:34 PM UTC 24 | 30471851 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1582770029 | Oct 09 10:41:30 PM UTC 24 | Oct 09 10:41:34 PM UTC 24 | 31628526 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4244597789 | Oct 09 10:41:33 PM UTC 24 | Oct 09 10:41:35 PM UTC 24 | 19076505 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3997379550 | Oct 09 10:41:34 PM UTC 24 | Oct 09 10:41:36 PM UTC 24 | 16224889 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3354536998 | Oct 09 10:41:34 PM UTC 24 | Oct 09 10:41:36 PM UTC 24 | 14901292 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.521350774 | Oct 09 10:41:34 PM UTC 24 | Oct 09 10:41:36 PM UTC 24 | 24170320 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2499675220 | Oct 09 10:41:34 PM UTC 24 | Oct 09 10:41:37 PM UTC 24 | 151266612 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3447313610 | Oct 09 10:41:34 PM UTC 24 | Oct 09 10:41:37 PM UTC 24 | 369157941 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2494546135 | Oct 09 10:41:36 PM UTC 24 | Oct 09 10:41:38 PM UTC 24 | 94763292 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4092258543 | Oct 09 10:41:37 PM UTC 24 | Oct 09 10:41:39 PM UTC 24 | 10590618 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1146370010 | Oct 09 10:41:37 PM UTC 24 | Oct 09 10:41:39 PM UTC 24 | 228432512 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2339327954 | Oct 09 10:41:36 PM UTC 24 | Oct 09 10:41:40 PM UTC 24 | 182558318 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3680883235 | Oct 09 10:41:58 PM UTC 24 | Oct 09 10:42:00 PM UTC 24 | 29016506 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3258249473 | Oct 09 10:41:37 PM UTC 24 | Oct 09 10:41:40 PM UTC 24 | 528637015 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1025855146 | Oct 09 10:41:38 PM UTC 24 | Oct 09 10:41:40 PM UTC 24 | 20801407 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.555671075 | Oct 09 10:41:38 PM UTC 24 | Oct 09 10:41:41 PM UTC 24 | 78510910 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1246325361 | Oct 09 10:41:40 PM UTC 24 | Oct 09 10:41:42 PM UTC 24 | 13254963 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1737376689 | Oct 09 10:41:38 PM UTC 24 | Oct 09 10:41:42 PM UTC 24 | 31996589 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2934218145 | Oct 09 10:41:40 PM UTC 24 | Oct 09 10:41:42 PM UTC 24 | 84864700 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4238862695 | Oct 09 10:41:41 PM UTC 24 | Oct 09 10:41:43 PM UTC 24 | 36826248 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1070664800 | Oct 09 10:41:41 PM UTC 24 | Oct 09 10:41:43 PM UTC 24 | 40098683 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.834857329 | Oct 09 10:41:41 PM UTC 24 | Oct 09 10:41:44 PM UTC 24 | 93709401 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3866839437 | Oct 09 10:41:42 PM UTC 24 | Oct 09 10:41:44 PM UTC 24 | 17211529 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.666063672 | Oct 09 10:41:42 PM UTC 24 | Oct 09 10:41:45 PM UTC 24 | 554363110 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.4273823728 | Oct 09 10:41:44 PM UTC 24 | Oct 09 10:41:45 PM UTC 24 | 39937144 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.270942246 | Oct 09 10:41:44 PM UTC 24 | Oct 09 10:41:46 PM UTC 24 | 33770034 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1524777635 | Oct 09 10:41:42 PM UTC 24 | Oct 09 10:41:46 PM UTC 24 | 355207892 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.430394528 | Oct 09 10:41:45 PM UTC 24 | Oct 09 10:41:47 PM UTC 24 | 86379185 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4192324781 | Oct 09 10:41:45 PM UTC 24 | Oct 09 10:41:47 PM UTC 24 | 37090516 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.3361460724 | Oct 09 10:41:45 PM UTC 24 | Oct 09 10:41:48 PM UTC 24 | 53435008 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2941416831 | Oct 09 10:41:46 PM UTC 24 | Oct 09 10:41:48 PM UTC 24 | 188023957 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1413467718 | Oct 09 10:41:46 PM UTC 24 | Oct 09 10:41:48 PM UTC 24 | 58012590 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.178874471 | Oct 09 10:41:47 PM UTC 24 | Oct 09 10:41:49 PM UTC 24 | 38145630 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.760377620 | Oct 09 10:41:47 PM UTC 24 | Oct 09 10:41:50 PM UTC 24 | 87543980 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3336254589 | Oct 09 10:41:49 PM UTC 24 | Oct 09 10:41:51 PM UTC 24 | 30414708 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.263912916 | Oct 09 10:41:49 PM UTC 24 | Oct 09 10:41:51 PM UTC 24 | 26231981 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2850401254 | Oct 09 10:41:49 PM UTC 24 | Oct 09 10:41:51 PM UTC 24 | 26104959 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1203758131 | Oct 09 10:41:49 PM UTC 24 | Oct 09 10:41:51 PM UTC 24 | 220703350 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.114604264 | Oct 09 10:41:50 PM UTC 24 | Oct 09 10:41:52 PM UTC 24 | 40461505 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1061089537 | Oct 09 10:41:50 PM UTC 24 | Oct 09 10:41:52 PM UTC 24 | 13890099 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2746570648 | Oct 09 10:41:50 PM UTC 24 | Oct 09 10:41:52 PM UTC 24 | 15535236 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3327793290 | Oct 09 10:41:50 PM UTC 24 | Oct 09 10:41:53 PM UTC 24 | 79789369 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1321595645 | Oct 09 10:41:49 PM UTC 24 | Oct 09 10:41:53 PM UTC 24 | 187141907 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2307572205 | Oct 09 10:41:52 PM UTC 24 | Oct 09 10:41:54 PM UTC 24 | 16192195 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3973996260 | Oct 09 10:41:52 PM UTC 24 | Oct 09 10:41:54 PM UTC 24 | 68688336 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1230776751 | Oct 09 10:41:52 PM UTC 24 | Oct 09 10:41:54 PM UTC 24 | 16406054 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1804689831 | Oct 09 10:41:53 PM UTC 24 | Oct 09 10:41:55 PM UTC 24 | 25276219 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.3716575415 | Oct 09 10:41:53 PM UTC 24 | Oct 09 10:41:55 PM UTC 24 | 26406053 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.825746025 | Oct 09 10:41:53 PM UTC 24 | Oct 09 10:41:55 PM UTC 24 | 12166415 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1552053010 | Oct 09 10:41:53 PM UTC 24 | Oct 09 10:41:55 PM UTC 24 | 44367235 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.4062855253 | Oct 09 10:41:54 PM UTC 24 | Oct 09 10:41:57 PM UTC 24 | 14151531 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2069859479 | Oct 09 10:41:55 PM UTC 24 | Oct 09 10:41:57 PM UTC 24 | 32962752 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2286069810 | Oct 09 10:41:55 PM UTC 24 | Oct 09 10:41:57 PM UTC 24 | 28258708 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3076504920 | Oct 09 10:41:55 PM UTC 24 | Oct 09 10:41:57 PM UTC 24 | 152763142 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3059440419 | Oct 09 10:41:55 PM UTC 24 | Oct 09 10:41:57 PM UTC 24 | 19058002 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3175470660 | Oct 09 10:41:56 PM UTC 24 | Oct 09 10:41:58 PM UTC 24 | 55445595 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.4118899049 | Oct 09 10:41:56 PM UTC 24 | Oct 09 10:41:58 PM UTC 24 | 12461205 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4209963634 | Oct 09 10:41:56 PM UTC 24 | Oct 09 10:41:58 PM UTC 24 | 39618855 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.931836786 | Oct 09 10:41:56 PM UTC 24 | Oct 09 10:41:59 PM UTC 24 | 109940492 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.1913505370 | Oct 09 10:41:58 PM UTC 24 | Oct 09 10:42:00 PM UTC 24 | 31054515 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.1137800175 | Oct 09 10:41:58 PM UTC 24 | Oct 09 10:42:00 PM UTC 24 | 14299448 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1671465165 | Oct 09 10:41:58 PM UTC 24 | Oct 09 10:42:00 PM UTC 24 | 10839722 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2830302127 | Oct 09 10:41:58 PM UTC 24 | Oct 09 10:42:00 PM UTC 24 | 14357543 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2647697517 | Oct 09 10:41:59 PM UTC 24 | Oct 09 10:42:01 PM UTC 24 | 26829600 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.643911887 | Oct 09 10:41:59 PM UTC 24 | Oct 09 10:42:01 PM UTC 24 | 197590144 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.545758656 | Oct 09 10:41:59 PM UTC 24 | Oct 09 10:42:01 PM UTC 24 | 15702428 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.93747298 | Oct 09 10:41:59 PM UTC 24 | Oct 09 10:42:01 PM UTC 24 | 131316167 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3843420150 | Oct 09 10:42:01 PM UTC 24 | Oct 09 10:42:03 PM UTC 24 | 34532373 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.505101469 | Oct 09 10:42:01 PM UTC 24 | Oct 09 10:42:03 PM UTC 24 | 25874587 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.1834903638 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 53622468983 ps |
| CPU time | 52.31 seconds |
| Started | Oct 09 09:55:24 PM UTC 24 |
| Finished | Oct 09 09:56:20 PM UTC 24 |
| Peak memory | 201320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834903638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1834903638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all_with_rand_reset.778209589 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4836056956 ps |
| CPU time | 19.52 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:10 PM UTC 24 |
| Peak memory | 205240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=778209589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.778209589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.819658876 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 151540249370 ps |
| CPU time | 153.87 seconds |
| Started | Oct 09 09:58:51 PM UTC 24 |
| Finished | Oct 09 10:01:28 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819658876 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.819658876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1573754042 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 40169126 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:40:17 PM UTC 24 |
| Finished | Oct 09 10:40:19 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573754042 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.1573754042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.3297325700 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2056142050887 ps |
| CPU time | 1164.67 seconds |
| Started | Oct 09 09:59:11 PM UTC 24 |
| Finished | Oct 09 10:18:48 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297325700 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.3297325700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.1603470916 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1267491213221 ps |
| CPU time | 3724.91 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:59:36 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603470916 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.1603470916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.285118585 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14650850 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:40:21 PM UTC 24 |
| Finished | Oct 09 10:40:23 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285118585 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.285118585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.776104102 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 594753617208 ps |
| CPU time | 2225.52 seconds |
| Started | Oct 09 09:58:23 PM UTC 24 |
| Finished | Oct 09 10:35:53 PM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776104102 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.776104102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.3060334605 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 354920697449 ps |
| CPU time | 1191.99 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:16:53 PM UTC 24 |
| Peak memory | 201220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060334605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.3060334605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.1088846056 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 132730725847 ps |
| CPU time | 384.19 seconds |
| Started | Oct 09 09:57:03 PM UTC 24 |
| Finished | Oct 09 10:03:33 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088846056 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1088846056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.1506202462 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1456872431545 ps |
| CPU time | 2658.94 seconds |
| Started | Oct 09 10:07:57 PM UTC 24 |
| Finished | Oct 09 10:52:44 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506202462 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.1506202462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.2317595535 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 329595040322 ps |
| CPU time | 1576.46 seconds |
| Started | Oct 09 09:58:38 PM UTC 24 |
| Finished | Oct 09 10:25:12 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317595535 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.2317595535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.304658145 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2286733309958 ps |
| CPU time | 1107.65 seconds |
| Started | Oct 09 10:11:43 PM UTC 24 |
| Finished | Oct 09 10:30:23 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304658145 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.304658145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.2127357485 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 200186917 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 09:56:46 PM UTC 24 |
| Finished | Oct 09 09:56:48 PM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127357485 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2127357485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.298133019 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2758671838167 ps |
| CPU time | 2365.97 seconds |
| Started | Oct 09 10:15:36 PM UTC 24 |
| Finished | Oct 09 10:55:27 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298133019 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.298133019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1792365709 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 330772466460 ps |
| CPU time | 1120.21 seconds |
| Started | Oct 09 09:57:48 PM UTC 24 |
| Finished | Oct 09 10:16:40 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792365709 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1792365709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.3723878117 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4049414782123 ps |
| CPU time | 1825.85 seconds |
| Started | Oct 09 10:16:08 PM UTC 24 |
| Finished | Oct 09 10:46:55 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723878117 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.3723878117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.1093229807 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 672611790791 ps |
| CPU time | 428.54 seconds |
| Started | Oct 09 10:06:41 PM UTC 24 |
| Finished | Oct 09 10:13:56 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093229807 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1093229807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.437253246 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 879526639666 ps |
| CPU time | 1069.85 seconds |
| Started | Oct 09 10:09:22 PM UTC 24 |
| Finished | Oct 09 10:27:24 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437253246 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.437253246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.4290707850 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 869462415349 ps |
| CPU time | 1359.53 seconds |
| Started | Oct 09 10:12:43 PM UTC 24 |
| Finished | Oct 09 10:35:37 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290707850 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.4290707850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.3817541703 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 368466347701 ps |
| CPU time | 1779.49 seconds |
| Started | Oct 09 10:05:55 PM UTC 24 |
| Finished | Oct 09 10:35:55 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817541703 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.3817541703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2709901287 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 80659769674 ps |
| CPU time | 1134.28 seconds |
| Started | Oct 09 10:03:02 PM UTC 24 |
| Finished | Oct 09 10:22:10 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709901287 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2709901287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2543876060 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 508313722761 ps |
| CPU time | 2543.97 seconds |
| Started | Oct 09 10:02:20 PM UTC 24 |
| Finished | Oct 09 10:45:13 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543876060 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.2543876060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.4265134712 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 274910583415 ps |
| CPU time | 627.97 seconds |
| Started | Oct 09 10:36:21 PM UTC 24 |
| Finished | Oct 09 10:46:58 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265134712 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4265134712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.3995141940 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 628172983949 ps |
| CPU time | 2190.77 seconds |
| Started | Oct 09 10:01:53 PM UTC 24 |
| Finished | Oct 09 10:38:48 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995141940 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.3995141940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.2909904970 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 64090295743 ps |
| CPU time | 457.18 seconds |
| Started | Oct 09 10:09:21 PM UTC 24 |
| Finished | Oct 09 10:17:04 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909904970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2909904970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.820710046 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 41640756 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:41:11 PM UTC 24 |
| Finished | Oct 09 10:41:13 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820710046 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.820710046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.4096411244 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 755282067564 ps |
| CPU time | 394.41 seconds |
| Started | Oct 09 09:57:34 PM UTC 24 |
| Finished | Oct 09 10:04:14 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096411244 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.4096411244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.698691446 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 458890780966 ps |
| CPU time | 267.62 seconds |
| Started | Oct 09 10:21:29 PM UTC 24 |
| Finished | Oct 09 10:26:01 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698691446 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.698691446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.2515655838 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1362802304676 ps |
| CPU time | 2115.23 seconds |
| Started | Oct 09 09:56:50 PM UTC 24 |
| Finished | Oct 09 10:32:27 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515655838 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.2515655838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.1684801397 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 200026335636 ps |
| CPU time | 1504.82 seconds |
| Started | Oct 09 10:25:28 PM UTC 24 |
| Finished | Oct 09 10:50:49 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684801397 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1684801397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.4032165703 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 97754285307 ps |
| CPU time | 282.4 seconds |
| Started | Oct 09 09:57:05 PM UTC 24 |
| Finished | Oct 09 10:01:52 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032165703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4032165703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.2626946543 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 636461091661 ps |
| CPU time | 3574.97 seconds |
| Started | Oct 09 09:57:09 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626946543 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.2626946543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.2765348577 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 101266058756 ps |
| CPU time | 402.95 seconds |
| Started | Oct 09 10:30:44 PM UTC 24 |
| Finished | Oct 09 10:37:33 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765348577 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2765348577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.1711532178 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 828273674192 ps |
| CPU time | 386.7 seconds |
| Started | Oct 09 09:57:22 PM UTC 24 |
| Finished | Oct 09 10:03:54 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711532178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.1711532178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.3981601984 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 612168440500 ps |
| CPU time | 971.95 seconds |
| Started | Oct 09 10:32:57 PM UTC 24 |
| Finished | Oct 09 10:49:21 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981601984 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3981601984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.500479383 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 150782162883 ps |
| CPU time | 833.25 seconds |
| Started | Oct 09 10:33:43 PM UTC 24 |
| Finished | Oct 09 10:47:47 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500479383 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.500479383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.2644276939 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 486818094656 ps |
| CPU time | 454.48 seconds |
| Started | Oct 09 10:00:12 PM UTC 24 |
| Finished | Oct 09 10:07:53 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644276939 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2644276939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.4099210462 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 542177773873 ps |
| CPU time | 1727.74 seconds |
| Started | Oct 09 10:07:13 PM UTC 24 |
| Finished | Oct 09 10:36:20 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099210462 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.4099210462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.3719738947 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 954054242909 ps |
| CPU time | 470.07 seconds |
| Started | Oct 09 10:39:01 PM UTC 24 |
| Finished | Oct 09 10:46:57 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719738947 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3719738947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3577468487 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 406239341809 ps |
| CPU time | 1399.5 seconds |
| Started | Oct 09 10:39:20 PM UTC 24 |
| Finished | Oct 09 11:02:57 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577468487 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3577468487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.886822584 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1430613054722 ps |
| CPU time | 563.92 seconds |
| Started | Oct 09 10:11:22 PM UTC 24 |
| Finished | Oct 09 10:20:52 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886822584 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.886822584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.3118297365 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2115959391346 ps |
| CPU time | 650.86 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:07:48 PM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118297365 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.3118297365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.2808607786 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 673962296946 ps |
| CPU time | 498.92 seconds |
| Started | Oct 09 10:19:54 PM UTC 24 |
| Finished | Oct 09 10:28:19 PM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808607786 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2808607786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.3520131520 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 894155904170 ps |
| CPU time | 272.66 seconds |
| Started | Oct 09 10:23:19 PM UTC 24 |
| Finished | Oct 09 10:27:56 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520131520 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3520131520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3988023690 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1252725084128 ps |
| CPU time | 634.91 seconds |
| Started | Oct 09 09:56:46 PM UTC 24 |
| Finished | Oct 09 10:07:29 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988023690 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3988023690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.1646478051 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 668589568848 ps |
| CPU time | 731.34 seconds |
| Started | Oct 09 10:23:43 PM UTC 24 |
| Finished | Oct 09 10:36:03 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646478051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1646478051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.2359149684 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 530708211142 ps |
| CPU time | 1216.97 seconds |
| Started | Oct 09 10:23:56 PM UTC 24 |
| Finished | Oct 09 10:44:27 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359149684 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2359149684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.412699235 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 160243976219 ps |
| CPU time | 733.46 seconds |
| Started | Oct 09 10:30:11 PM UTC 24 |
| Finished | Oct 09 10:42:33 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412699235 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.412699235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.333872427 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 545380758696 ps |
| CPU time | 1018.42 seconds |
| Started | Oct 09 09:57:54 PM UTC 24 |
| Finished | Oct 09 10:15:05 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333872427 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.333872427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.548706192 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 135763539033 ps |
| CPU time | 488.99 seconds |
| Started | Oct 09 10:36:23 PM UTC 24 |
| Finished | Oct 09 10:44:39 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548706192 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.548706192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.2439454130 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 226969455793 ps |
| CPU time | 176.56 seconds |
| Started | Oct 09 10:04:18 PM UTC 24 |
| Finished | Oct 09 10:07:18 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439454130 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.2439454130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.1100771752 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 492760390467 ps |
| CPU time | 2116.38 seconds |
| Started | Oct 09 10:07:34 PM UTC 24 |
| Finished | Oct 09 10:43:14 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100771752 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.1100771752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1955890573 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 99894372182 ps |
| CPU time | 595.38 seconds |
| Started | Oct 09 10:23:28 PM UTC 24 |
| Finished | Oct 09 10:33:30 PM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955890573 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1955890573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3081825773 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 225992547588 ps |
| CPU time | 939.45 seconds |
| Started | Oct 09 10:23:29 PM UTC 24 |
| Finished | Oct 09 10:39:20 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081825773 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3081825773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/99.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.296770241 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 783885733281 ps |
| CPU time | 1409.15 seconds |
| Started | Oct 09 10:25:49 PM UTC 24 |
| Finished | Oct 09 10:49:35 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296770241 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.296770241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2543309135 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 612394718530 ps |
| CPU time | 728.07 seconds |
| Started | Oct 09 10:27:20 PM UTC 24 |
| Finished | Oct 09 10:39:37 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543309135 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2543309135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.505578124 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 241822866456 ps |
| CPU time | 248.06 seconds |
| Started | Oct 09 09:57:12 PM UTC 24 |
| Finished | Oct 09 10:01:24 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505578124 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.505578124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.3712087910 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 643507405646 ps |
| CPU time | 479.17 seconds |
| Started | Oct 09 09:57:54 PM UTC 24 |
| Finished | Oct 09 10:05:59 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712087910 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3712087910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2882447776 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 135979438125 ps |
| CPU time | 1662.67 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:24:51 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882447776 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2882447776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3798448481 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 92176581867 ps |
| CPU time | 332.39 seconds |
| Started | Oct 09 10:22:44 PM UTC 24 |
| Finished | Oct 09 10:28:21 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798448481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3798448481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.1629569860 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 681193172249 ps |
| CPU time | 572.39 seconds |
| Started | Oct 09 10:24:03 PM UTC 24 |
| Finished | Oct 09 10:33:42 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629569860 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1629569860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.2484888291 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 398162024711 ps |
| CPU time | 359.72 seconds |
| Started | Oct 09 10:26:19 PM UTC 24 |
| Finished | Oct 09 10:32:23 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484888291 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2484888291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.2134303186 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 168806766285 ps |
| CPU time | 131.06 seconds |
| Started | Oct 09 10:27:29 PM UTC 24 |
| Finished | Oct 09 10:29:43 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134303186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2134303186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.3083694741 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 357236460210 ps |
| CPU time | 433.75 seconds |
| Started | Oct 09 10:32:28 PM UTC 24 |
| Finished | Oct 09 10:39:48 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083694741 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3083694741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.1448086095 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 107213490267 ps |
| CPU time | 176.74 seconds |
| Started | Oct 09 10:38:49 PM UTC 24 |
| Finished | Oct 09 10:41:49 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448086095 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1448086095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.800260193 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 301007989765 ps |
| CPU time | 1144.1 seconds |
| Started | Oct 09 10:39:24 PM UTC 24 |
| Finished | Oct 09 10:58:41 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800260193 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.800260193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.426392254 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 574039634531 ps |
| CPU time | 1130.77 seconds |
| Started | Oct 09 10:02:11 PM UTC 24 |
| Finished | Oct 09 10:21:14 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426392254 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.426392254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.622550340 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 413193984588 ps |
| CPU time | 1244.56 seconds |
| Started | Oct 09 10:09:12 PM UTC 24 |
| Finished | Oct 09 10:30:10 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622550340 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.622550340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.853688288 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 139295219344 ps |
| CPU time | 520.89 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:05:37 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853688288 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.853688288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3739331987 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 75483997 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 10:41:30 PM UTC 24 |
| Finished | Oct 09 10:41:33 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739331987 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.3739331987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.1881817475 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1329031055263 ps |
| CPU time | 944.19 seconds |
| Started | Oct 09 09:55:24 PM UTC 24 |
| Finished | Oct 09 10:11:21 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881817475 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1881817475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.3520635733 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 99549789518 ps |
| CPU time | 171.23 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 09:59:41 PM UTC 24 |
| Peak memory | 200804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520635733 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.3520635733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.2808196378 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 23847321738 ps |
| CPU time | 23.64 seconds |
| Started | Oct 09 09:56:50 PM UTC 24 |
| Finished | Oct 09 09:57:15 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808196378 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2808196378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.676372873 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 68335412903 ps |
| CPU time | 183.63 seconds |
| Started | Oct 09 09:56:50 PM UTC 24 |
| Finished | Oct 09 09:59:57 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676372873 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.676372873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.3651745022 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 132086364789 ps |
| CPU time | 440.11 seconds |
| Started | Oct 09 09:56:52 PM UTC 24 |
| Finished | Oct 09 10:04:18 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651745022 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3651745022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.1332232960 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 271144394954 ps |
| CPU time | 940.15 seconds |
| Started | Oct 09 10:24:24 PM UTC 24 |
| Finished | Oct 09 10:40:15 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332232960 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1332232960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.3971495056 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 52004892113 ps |
| CPU time | 436.76 seconds |
| Started | Oct 09 10:25:55 PM UTC 24 |
| Finished | Oct 09 10:33:18 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971495056 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3971495056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3350938412 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 441406804007 ps |
| CPU time | 239.69 seconds |
| Started | Oct 09 10:27:24 PM UTC 24 |
| Finished | Oct 09 10:31:27 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350938412 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3350938412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.857394570 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 415144128785 ps |
| CPU time | 616.84 seconds |
| Started | Oct 09 10:27:25 PM UTC 24 |
| Finished | Oct 09 10:37:50 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857394570 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.857394570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.2521395489 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1408675179217 ps |
| CPU time | 452.38 seconds |
| Started | Oct 09 10:28:09 PM UTC 24 |
| Finished | Oct 09 10:35:47 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521395489 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2521395489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.1324994504 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 13830119863 ps |
| CPU time | 49.5 seconds |
| Started | Oct 09 09:57:16 PM UTC 24 |
| Finished | Oct 09 09:58:07 PM UTC 24 |
| Peak memory | 201288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324994504 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1324994504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.458888014 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 44112685277 ps |
| CPU time | 102.93 seconds |
| Started | Oct 09 10:29:45 PM UTC 24 |
| Finished | Oct 09 10:31:30 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458888014 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.458888014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.3558445788 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 154601324172 ps |
| CPU time | 74.24 seconds |
| Started | Oct 09 09:57:34 PM UTC 24 |
| Finished | Oct 09 09:58:51 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558445788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3558445788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.1675999939 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 316154101627 ps |
| CPU time | 433.15 seconds |
| Started | Oct 09 10:32:01 PM UTC 24 |
| Finished | Oct 09 10:39:20 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675999939 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1675999939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.2357020158 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 113578480380 ps |
| CPU time | 489.85 seconds |
| Started | Oct 09 09:57:48 PM UTC 24 |
| Finished | Oct 09 10:06:04 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357020158 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2357020158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.2121889742 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 130610328119 ps |
| CPU time | 822.54 seconds |
| Started | Oct 09 10:33:20 PM UTC 24 |
| Finished | Oct 09 10:47:12 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121889742 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2121889742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.450503171 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 719620031827 ps |
| CPU time | 929.39 seconds |
| Started | Oct 09 10:34:33 PM UTC 24 |
| Finished | Oct 09 10:50:14 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450503171 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.450503171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.2441758605 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 138314381642 ps |
| CPU time | 913.63 seconds |
| Started | Oct 09 10:35:48 PM UTC 24 |
| Finished | Oct 09 10:51:12 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441758605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2441758605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2203937339 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 797060481834 ps |
| CPU time | 454.25 seconds |
| Started | Oct 09 10:36:57 PM UTC 24 |
| Finished | Oct 09 10:44:37 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203937339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2203937339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.107915857 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 640544573035 ps |
| CPU time | 277.37 seconds |
| Started | Oct 09 10:37:34 PM UTC 24 |
| Finished | Oct 09 10:42:16 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107915857 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.107915857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.929198448 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 92931229498 ps |
| CPU time | 178.7 seconds |
| Started | Oct 09 10:38:48 PM UTC 24 |
| Finished | Oct 09 10:41:50 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929198448 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.929198448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.1086917402 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 109867940412 ps |
| CPU time | 315.77 seconds |
| Started | Oct 09 09:59:31 PM UTC 24 |
| Finished | Oct 09 10:04:51 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086917402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1086917402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.1788408640 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 98414239097 ps |
| CPU time | 340.78 seconds |
| Started | Oct 09 10:39:25 PM UTC 24 |
| Finished | Oct 09 10:45:10 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788408640 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1788408640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3147293360 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 611454526126 ps |
| CPU time | 439.5 seconds |
| Started | Oct 09 10:39:49 PM UTC 24 |
| Finished | Oct 09 10:47:14 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147293360 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3147293360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.2154636118 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 336135268620 ps |
| CPU time | 643.19 seconds |
| Started | Oct 09 10:39:55 PM UTC 24 |
| Finished | Oct 09 10:50:48 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154636118 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2154636118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.1664546649 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 78702804711 ps |
| CPU time | 100.49 seconds |
| Started | Oct 09 10:02:11 PM UTC 24 |
| Finished | Oct 09 10:03:54 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664546649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1664546649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.933233493 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 97463965854 ps |
| CPU time | 82.01 seconds |
| Started | Oct 09 10:02:54 PM UTC 24 |
| Finished | Oct 09 10:04:18 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933233493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.933233493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.3808764069 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 196990649301 ps |
| CPU time | 452.39 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:04:26 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808764069 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.3808764069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.2920511534 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 54089920823 ps |
| CPU time | 274.93 seconds |
| Started | Oct 09 10:05:38 PM UTC 24 |
| Finished | Oct 09 10:10:17 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920511534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2920511534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.3039075398 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2242383427777 ps |
| CPU time | 1293.71 seconds |
| Started | Oct 09 10:06:01 PM UTC 24 |
| Finished | Oct 09 10:27:49 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039075398 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.3039075398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.566566931 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1109850847392 ps |
| CPU time | 996.15 seconds |
| Started | Oct 09 10:06:40 PM UTC 24 |
| Finished | Oct 09 10:23:28 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566566931 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.566566931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.3708195705 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 910655239554 ps |
| CPU time | 669.65 seconds |
| Started | Oct 09 10:08:58 PM UTC 24 |
| Finished | Oct 09 10:20:15 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708195705 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.3708195705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.632519833 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 263595417496 ps |
| CPU time | 172.46 seconds |
| Started | Oct 09 10:11:15 PM UTC 24 |
| Finished | Oct 09 10:14:10 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632519833 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.632519833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.53730645 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 305757767365 ps |
| CPU time | 446.6 seconds |
| Started | Oct 09 10:15:27 PM UTC 24 |
| Finished | Oct 09 10:23:00 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53730645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.53730645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1791059757 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 380143471523 ps |
| CPU time | 317.26 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:02:10 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791059757 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1791059757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.1711048579 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 82995559554 ps |
| CPU time | 448.51 seconds |
| Started | Oct 09 10:17:52 PM UTC 24 |
| Finished | Oct 09 10:25:27 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711048579 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1711048579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.2724682594 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 754347223206 ps |
| CPU time | 543.28 seconds |
| Started | Oct 09 10:19:59 PM UTC 24 |
| Finished | Oct 09 10:29:09 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724682594 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2724682594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.4090351869 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 53080531500 ps |
| CPU time | 119.85 seconds |
| Started | Oct 09 10:20:07 PM UTC 24 |
| Finished | Oct 09 10:22:09 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090351869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4090351869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1286406163 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 15656540 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:40:24 PM UTC 24 |
| Finished | Oct 09 10:40:26 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286406163 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.1286406163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2623441460 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1005038619 ps |
| CPU time | 4.94 seconds |
| Started | Oct 09 10:40:23 PM UTC 24 |
| Finished | Oct 09 10:40:29 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623441460 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.2623441460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2086102352 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15568383 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:40:20 PM UTC 24 |
| Finished | Oct 09 10:40:22 PM UTC 24 |
| Peak memory | 199184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086102352 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.2086102352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4145067046 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 118145586 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 10:40:29 PM UTC 24 |
| Finished | Oct 09 10:40:33 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4145067046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.4145067046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.2821884984 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 36556069 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 10:40:18 PM UTC 24 |
| Finished | Oct 09 10:40:20 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821884984 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2821884984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3723210088 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 114828328 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:40:27 PM UTC 24 |
| Finished | Oct 09 10:40:29 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723210088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.3723210088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.4272953409 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 318846847 ps |
| CPU time | 2.54 seconds |
| Started | Oct 09 10:40:14 PM UTC 24 |
| Finished | Oct 09 10:40:17 PM UTC 24 |
| Peak memory | 202748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272953409 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4272953409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2120688918 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 38881410 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:40:38 PM UTC 24 |
| Finished | Oct 09 10:40:40 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120688918 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.2120688918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2076125187 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 132370675 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 10:40:37 PM UTC 24 |
| Finished | Oct 09 10:40:40 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076125187 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.2076125187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3305114977 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 21206761 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:40:35 PM UTC 24 |
| Finished | Oct 09 10:40:36 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305114977 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.3305114977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2980427696 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 32602290 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:40:39 PM UTC 24 |
| Finished | Oct 09 10:40:41 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2980427696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.2980427696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.2222429810 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 29962560 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:40:36 PM UTC 24 |
| Finished | Oct 09 10:40:38 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222429810 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2222429810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.667778574 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 44844326 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:40:33 PM UTC 24 |
| Finished | Oct 09 10:40:35 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667778574 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.667778574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4119453616 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 39598197 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 10:40:38 PM UTC 24 |
| Finished | Oct 09 10:40:40 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119453616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.4119453616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.1898961533 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 48917693 ps |
| CPU time | 3.27 seconds |
| Started | Oct 09 10:40:30 PM UTC 24 |
| Finished | Oct 09 10:40:35 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898961533 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1898961533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1619188040 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1228371766 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 10:40:30 PM UTC 24 |
| Finished | Oct 09 10:40:34 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619188040 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1619188040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.659831756 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 26965175 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 10:41:24 PM UTC 24 |
| Finished | Oct 09 10:41:26 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=659831756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_cs r_mem_rw_with_rand_reset.659831756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.2740515737 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 89226378 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:23 PM UTC 24 |
| Finished | Oct 09 10:41:24 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740515737 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2740515737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.3572063192 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 39362513 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:21 PM UTC 24 |
| Finished | Oct 09 10:41:23 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572063192 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3572063192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2469064181 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 49292863 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:41:23 PM UTC 24 |
| Finished | Oct 09 10:41:25 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469064181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.2469064181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.2441879522 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 71400602 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 10:41:21 PM UTC 24 |
| Finished | Oct 09 10:41:24 PM UTC 24 |
| Peak memory | 199200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441879522 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2441879522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3452933061 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 127239940 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 10:41:21 PM UTC 24 |
| Finished | Oct 09 10:41:24 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452933061 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.3452933061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3855002506 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 73135918 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:41:27 PM UTC 24 |
| Finished | Oct 09 10:41:29 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3855002506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.3855002506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.2342586677 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 16033858 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 10:41:25 PM UTC 24 |
| Finished | Oct 09 10:41:27 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342586677 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2342586677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.1189808911 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 201171255 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:25 PM UTC 24 |
| Finished | Oct 09 10:41:27 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189808911 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1189808911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3827808424 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 51219551 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:41:26 PM UTC 24 |
| Finished | Oct 09 10:41:29 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827808424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.3827808424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2476384940 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 326007160 ps |
| CPU time | 2.87 seconds |
| Started | Oct 09 10:41:25 PM UTC 24 |
| Finished | Oct 09 10:41:29 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476384940 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2476384940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2611741311 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 168666806 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:41:25 PM UTC 24 |
| Finished | Oct 09 10:41:27 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611741311 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.2611741311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1929820770 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 42914757 ps |
| CPU time | 1.45 seconds |
| Started | Oct 09 10:41:30 PM UTC 24 |
| Finished | Oct 09 10:41:33 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1929820770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.1929820770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.4115013635 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 97691413 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:41:29 PM UTC 24 |
| Finished | Oct 09 10:41:31 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115013635 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4115013635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1355339752 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 18357706 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:28 PM UTC 24 |
| Finished | Oct 09 10:41:30 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355339752 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1355339752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2746189454 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 18321009 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 10:41:29 PM UTC 24 |
| Finished | Oct 09 10:41:31 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746189454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.2746189454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.2310220438 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 694810859 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 10:41:27 PM UTC 24 |
| Finished | Oct 09 10:41:32 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310220438 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2310220438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2719212353 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 269678066 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 10:41:28 PM UTC 24 |
| Finished | Oct 09 10:41:31 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719212353 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.2719212353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4244597789 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 19076505 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 10:41:33 PM UTC 24 |
| Finished | Oct 09 10:41:35 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4244597789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.4244597789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1734795618 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 36716438 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 10:41:32 PM UTC 24 |
| Finished | Oct 09 10:41:33 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734795618 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1734795618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.518842732 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 46549291 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:32 PM UTC 24 |
| Finished | Oct 09 10:41:34 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518842732 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.518842732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3746351713 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 30471851 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:41:32 PM UTC 24 |
| Finished | Oct 09 10:41:34 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746351713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.3746351713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.1582770029 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 31628526 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 10:41:30 PM UTC 24 |
| Finished | Oct 09 10:41:34 PM UTC 24 |
| Peak memory | 200580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582770029 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1582770029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2494546135 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 94763292 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:41:36 PM UTC 24 |
| Finished | Oct 09 10:41:38 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2494546135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.2494546135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3354536998 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 14901292 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:41:34 PM UTC 24 |
| Finished | Oct 09 10:41:36 PM UTC 24 |
| Peak memory | 199068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354536998 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3354536998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3997379550 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 16224889 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:34 PM UTC 24 |
| Finished | Oct 09 10:41:36 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997379550 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3997379550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.521350774 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 24170320 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:41:34 PM UTC 24 |
| Finished | Oct 09 10:41:36 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521350774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.521350774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.3447313610 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 369157941 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 10:41:34 PM UTC 24 |
| Finished | Oct 09 10:41:37 PM UTC 24 |
| Peak memory | 201168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447313610 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3447313610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2499675220 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 151266612 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 10:41:34 PM UTC 24 |
| Finished | Oct 09 10:41:37 PM UTC 24 |
| Peak memory | 199068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499675220 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.2499675220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1737376689 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 31996589 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:41:38 PM UTC 24 |
| Finished | Oct 09 10:41:42 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1737376689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1737376689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1146370010 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 228432512 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:41:37 PM UTC 24 |
| Finished | Oct 09 10:41:39 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146370010 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1146370010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4092258543 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 10590618 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 10:41:37 PM UTC 24 |
| Finished | Oct 09 10:41:39 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092258543 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4092258543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1025855146 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 20801407 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:41:38 PM UTC 24 |
| Finished | Oct 09 10:41:40 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025855146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.1025855146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2339327954 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 182558318 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 10:41:36 PM UTC 24 |
| Finished | Oct 09 10:41:40 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339327954 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2339327954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3258249473 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 528637015 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 10:41:37 PM UTC 24 |
| Finished | Oct 09 10:41:40 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258249473 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3258249473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.834857329 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 93709401 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 10:41:41 PM UTC 24 |
| Finished | Oct 09 10:41:44 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=834857329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.834857329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4238862695 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 36826248 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:41 PM UTC 24 |
| Finished | Oct 09 10:41:43 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238862695 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4238862695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1246325361 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 13254963 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:40 PM UTC 24 |
| Finished | Oct 09 10:41:42 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246325361 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1246325361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1070664800 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 40098683 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:41:41 PM UTC 24 |
| Finished | Oct 09 10:41:43 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070664800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.1070664800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.555671075 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 78510910 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 10:41:38 PM UTC 24 |
| Finished | Oct 09 10:41:41 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555671075 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.555671075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2934218145 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 84864700 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 10:41:40 PM UTC 24 |
| Finished | Oct 09 10:41:42 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934218145 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.2934218145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4192324781 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 37090516 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:41:45 PM UTC 24 |
| Finished | Oct 09 10:41:47 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4192324781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.4192324781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.4273823728 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 39937144 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:44 PM UTC 24 |
| Finished | Oct 09 10:41:45 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273823728 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4273823728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3866839437 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 17211529 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:42 PM UTC 24 |
| Finished | Oct 09 10:41:44 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866839437 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3866839437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.270942246 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 33770034 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:41:44 PM UTC 24 |
| Finished | Oct 09 10:41:46 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270942246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.270942246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1524777635 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 355207892 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 10:41:42 PM UTC 24 |
| Finished | Oct 09 10:41:46 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524777635 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1524777635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.666063672 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 554363110 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 10:41:42 PM UTC 24 |
| Finished | Oct 09 10:41:45 PM UTC 24 |
| Peak memory | 200776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666063672 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.666063672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.760377620 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 87543980 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 10:41:47 PM UTC 24 |
| Finished | Oct 09 10:41:50 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=760377620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_cs r_mem_rw_with_rand_reset.760377620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1413467718 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 58012590 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:41:46 PM UTC 24 |
| Finished | Oct 09 10:41:48 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413467718 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1413467718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2941416831 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 188023957 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:46 PM UTC 24 |
| Finished | Oct 09 10:41:48 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941416831 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2941416831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.178874471 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 38145630 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 10:41:47 PM UTC 24 |
| Finished | Oct 09 10:41:49 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178874471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.178874471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.3361460724 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 53435008 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 10:41:45 PM UTC 24 |
| Finished | Oct 09 10:41:48 PM UTC 24 |
| Peak memory | 199248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361460724 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3361460724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.430394528 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 86379185 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:41:45 PM UTC 24 |
| Finished | Oct 09 10:41:47 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430394528 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.430394528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3327793290 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 79789369 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 10:41:50 PM UTC 24 |
| Finished | Oct 09 10:41:53 PM UTC 24 |
| Peak memory | 201236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3327793290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3327793290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3336254589 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 30414708 ps |
| CPU time | 0.74 seconds |
| Started | Oct 09 10:41:49 PM UTC 24 |
| Finished | Oct 09 10:41:51 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336254589 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3336254589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.263912916 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 26231981 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:41:49 PM UTC 24 |
| Finished | Oct 09 10:41:51 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263912916 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.263912916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2850401254 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 26104959 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:41:49 PM UTC 24 |
| Finished | Oct 09 10:41:51 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850401254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.2850401254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1321595645 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 187141907 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:41:49 PM UTC 24 |
| Finished | Oct 09 10:41:53 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321595645 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1321595645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1203758131 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 220703350 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 10:41:49 PM UTC 24 |
| Finished | Oct 09 10:41:51 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203758131 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.1203758131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4118241494 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 35814111 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:40:46 PM UTC 24 |
| Finished | Oct 09 10:40:48 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118241494 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.4118241494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2776099914 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1420624348 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 10:40:46 PM UTC 24 |
| Finished | Oct 09 10:40:51 PM UTC 24 |
| Peak memory | 200644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776099914 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2776099914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2218315512 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 18126544 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:40:42 PM UTC 24 |
| Finished | Oct 09 10:40:44 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218315512 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.2218315512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2180925436 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 48816587 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:40:47 PM UTC 24 |
| Finished | Oct 09 10:40:49 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2180925436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2180925436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.2671632300 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 11967737 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:40:44 PM UTC 24 |
| Finished | Oct 09 10:40:46 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671632300 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2671632300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2157618799 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 91526895 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:40:41 PM UTC 24 |
| Finished | Oct 09 10:40:43 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157618799 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2157618799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.725795614 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 86200828 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:40:47 PM UTC 24 |
| Finished | Oct 09 10:40:49 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725795614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.725795614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.828060964 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 188462677 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 10:40:41 PM UTC 24 |
| Finished | Oct 09 10:40:46 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828060964 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.828060964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1213187304 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 557383111 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 10:40:41 PM UTC 24 |
| Finished | Oct 09 10:40:44 PM UTC 24 |
| Peak memory | 200776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213187304 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.1213187304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.114604264 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 40461505 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:50 PM UTC 24 |
| Finished | Oct 09 10:41:52 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114604264 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.114604264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1061089537 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 13890099 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:50 PM UTC 24 |
| Finished | Oct 09 10:41:52 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061089537 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1061089537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.2746570648 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 15535236 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:50 PM UTC 24 |
| Finished | Oct 09 10:41:52 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746570648 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2746570648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3973996260 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 68688336 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:52 PM UTC 24 |
| Finished | Oct 09 10:41:54 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973996260 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3973996260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2307572205 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 16192195 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 10:41:52 PM UTC 24 |
| Finished | Oct 09 10:41:54 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307572205 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2307572205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1230776751 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 16406054 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:52 PM UTC 24 |
| Finished | Oct 09 10:41:54 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230776751 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1230776751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.3716575415 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 26406053 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:53 PM UTC 24 |
| Finished | Oct 09 10:41:55 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716575415 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3716575415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1804689831 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 25276219 ps |
| CPU time | 0.66 seconds |
| Started | Oct 09 10:41:53 PM UTC 24 |
| Finished | Oct 09 10:41:55 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804689831 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1804689831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.825746025 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 12166415 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:53 PM UTC 24 |
| Finished | Oct 09 10:41:55 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825746025 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.825746025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1552053010 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 44367235 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:53 PM UTC 24 |
| Finished | Oct 09 10:41:55 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552053010 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1552053010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1391954902 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 69060901 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:40:53 PM UTC 24 |
| Finished | Oct 09 10:40:56 PM UTC 24 |
| Peak memory | 199188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391954902 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.1391954902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2756098594 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 100839164 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 10:40:53 PM UTC 24 |
| Finished | Oct 09 10:40:57 PM UTC 24 |
| Peak memory | 200584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756098594 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.2756098594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.625618073 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 15384886 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:40:52 PM UTC 24 |
| Finished | Oct 09 10:40:54 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625618073 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.625618073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3525856212 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 77351770 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:40:57 PM UTC 24 |
| Finished | Oct 09 10:40:59 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3525856212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.3525856212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.1346646859 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 27746169 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 10:40:53 PM UTC 24 |
| Finished | Oct 09 10:40:55 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346646859 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1346646859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.1031785446 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 15818715 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:40:50 PM UTC 24 |
| Finished | Oct 09 10:40:52 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031785446 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1031785446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.637570961 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 37320168 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 10:40:55 PM UTC 24 |
| Finished | Oct 09 10:40:57 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637570961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.637570961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.4225881914 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 172855582 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 10:40:49 PM UTC 24 |
| Finished | Oct 09 10:40:52 PM UTC 24 |
| Peak memory | 202892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225881914 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4225881914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3552061169 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 44626291 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:40:50 PM UTC 24 |
| Finished | Oct 09 10:40:52 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552061169 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.3552061169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.4062855253 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14151531 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 10:41:54 PM UTC 24 |
| Finished | Oct 09 10:41:57 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062855253 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4062855253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.2286069810 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 28258708 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:55 PM UTC 24 |
| Finished | Oct 09 10:41:57 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286069810 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2286069810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2069859479 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 32962752 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 10:41:55 PM UTC 24 |
| Finished | Oct 09 10:41:57 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069859479 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2069859479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3076504920 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 152763142 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:55 PM UTC 24 |
| Finished | Oct 09 10:41:57 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076504920 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3076504920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3059440419 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 19058002 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 10:41:55 PM UTC 24 |
| Finished | Oct 09 10:41:57 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059440419 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3059440419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3175470660 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 55445595 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:56 PM UTC 24 |
| Finished | Oct 09 10:41:58 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175470660 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3175470660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.4118899049 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 12461205 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:56 PM UTC 24 |
| Finished | Oct 09 10:41:58 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118899049 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4118899049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4209963634 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 39618855 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:56 PM UTC 24 |
| Finished | Oct 09 10:41:58 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209963634 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4209963634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.931836786 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 109940492 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:56 PM UTC 24 |
| Finished | Oct 09 10:41:59 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931836786 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.931836786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.1137800175 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 14299448 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:58 PM UTC 24 |
| Finished | Oct 09 10:42:00 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137800175 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1137800175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.852637420 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 44733117 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:41:01 PM UTC 24 |
| Finished | Oct 09 10:41:04 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852637420 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.852637420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4185081876 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 739533739 ps |
| CPU time | 3.77 seconds |
| Started | Oct 09 10:41:00 PM UTC 24 |
| Finished | Oct 09 10:41:05 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185081876 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.4185081876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.971380014 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 79519070 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:00 PM UTC 24 |
| Finished | Oct 09 10:41:02 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971380014 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.971380014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1828501193 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 92563328 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:41:03 PM UTC 24 |
| Finished | Oct 09 10:41:05 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1828501193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.1828501193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.291337431 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 117815569 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:00 PM UTC 24 |
| Finished | Oct 09 10:41:02 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291337431 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.291337431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.2388893234 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 44455977 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:40:58 PM UTC 24 |
| Finished | Oct 09 10:41:00 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388893234 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2388893234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2090517293 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 77935436 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 10:41:01 PM UTC 24 |
| Finished | Oct 09 10:41:04 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090517293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.2090517293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1885200147 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 207930513 ps |
| CPU time | 3.05 seconds |
| Started | Oct 09 10:40:57 PM UTC 24 |
| Finished | Oct 09 10:41:01 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885200147 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1885200147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1770221199 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 70278411 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:40:58 PM UTC 24 |
| Finished | Oct 09 10:41:00 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770221199 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.1770221199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3680883235 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 29016506 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 10:41:58 PM UTC 24 |
| Finished | Oct 09 10:42:00 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680883235 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3680883235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.1913505370 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 31054515 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 10:41:58 PM UTC 24 |
| Finished | Oct 09 10:42:00 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913505370 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1913505370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2830302127 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 14357543 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:58 PM UTC 24 |
| Finished | Oct 09 10:42:00 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830302127 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2830302127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1671465165 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 10839722 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:58 PM UTC 24 |
| Finished | Oct 09 10:42:00 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671465165 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1671465165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2647697517 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 26829600 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 10:41:59 PM UTC 24 |
| Finished | Oct 09 10:42:01 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647697517 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2647697517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.643911887 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 197590144 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:59 PM UTC 24 |
| Finished | Oct 09 10:42:01 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643911887 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.643911887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.545758656 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 15702428 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:59 PM UTC 24 |
| Finished | Oct 09 10:42:01 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545758656 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.545758656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.93747298 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 131316167 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:59 PM UTC 24 |
| Finished | Oct 09 10:42:01 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93747298 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.93747298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3843420150 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 34532373 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 10:42:01 PM UTC 24 |
| Finished | Oct 09 10:42:03 PM UTC 24 |
| Peak memory | 199120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843420150 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3843420150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.505101469 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 25874587 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:42:01 PM UTC 24 |
| Finished | Oct 09 10:42:03 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505101469 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.505101469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2660663822 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 30276439 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 10:41:06 PM UTC 24 |
| Finished | Oct 09 10:41:09 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2660663822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2660663822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3494491784 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 17119138 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 10:41:06 PM UTC 24 |
| Finished | Oct 09 10:41:08 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494491784 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3494491784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.225831847 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 26186963 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 10:41:05 PM UTC 24 |
| Finished | Oct 09 10:41:07 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225831847 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.225831847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3896729977 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 37143123 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:41:06 PM UTC 24 |
| Finished | Oct 09 10:41:08 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896729977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.3896729977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.2280891010 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 943405449 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:41:03 PM UTC 24 |
| Finished | Oct 09 10:41:07 PM UTC 24 |
| Peak memory | 200968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280891010 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2280891010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1133461869 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 321253343 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 10:41:05 PM UTC 24 |
| Finished | Oct 09 10:41:08 PM UTC 24 |
| Peak memory | 199068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133461869 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1133461869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.614255240 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 53071293 ps |
| CPU time | 0.95 seconds |
| Started | Oct 09 10:41:10 PM UTC 24 |
| Finished | Oct 09 10:41:12 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=614255240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.614255240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2498416534 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 30565032 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 10:41:09 PM UTC 24 |
| Finished | Oct 09 10:41:11 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498416534 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2498416534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.4108078604 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 12598303 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:09 PM UTC 24 |
| Finished | Oct 09 10:41:10 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108078604 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4108078604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1389227430 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 183649627 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 10:41:10 PM UTC 24 |
| Finished | Oct 09 10:41:12 PM UTC 24 |
| Peak memory | 199068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389227430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.1389227430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.163190190 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 46188455 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 10:41:07 PM UTC 24 |
| Finished | Oct 09 10:41:10 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163190190 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.163190190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.540970486 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 213996104 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:41:07 PM UTC 24 |
| Finished | Oct 09 10:41:10 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540970486 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.540970486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.126702066 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 56227351 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:41:13 PM UTC 24 |
| Finished | Oct 09 10:41:15 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=126702066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr _mem_rw_with_rand_reset.126702066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.819928799 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 31927731 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:11 PM UTC 24 |
| Finished | Oct 09 10:41:13 PM UTC 24 |
| Peak memory | 199124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819928799 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.819928799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3018068095 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 49198493 ps |
| CPU time | 1.05 seconds |
| Started | Oct 09 10:41:13 PM UTC 24 |
| Finished | Oct 09 10:41:15 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018068095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.3018068095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.357856185 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 676473837 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 10:41:11 PM UTC 24 |
| Finished | Oct 09 10:41:16 PM UTC 24 |
| Peak memory | 202880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357856185 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.357856185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2321592809 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 47244950 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 10:41:11 PM UTC 24 |
| Finished | Oct 09 10:41:14 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321592809 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.2321592809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1495362776 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 26159733 ps |
| CPU time | 1.68 seconds |
| Started | Oct 09 10:41:17 PM UTC 24 |
| Finished | Oct 09 10:41:20 PM UTC 24 |
| Peak memory | 201176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1495362776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.1495362776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.3552201772 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 17425564 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 10:41:16 PM UTC 24 |
| Finished | Oct 09 10:41:18 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552201772 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3552201772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2928671828 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 29452791 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 10:41:15 PM UTC 24 |
| Finished | Oct 09 10:41:17 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928671828 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2928671828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.604625436 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 32530416 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:41:16 PM UTC 24 |
| Finished | Oct 09 10:41:18 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604625436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.604625436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1086039142 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 298186436 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 10:41:14 PM UTC 24 |
| Finished | Oct 09 10:41:19 PM UTC 24 |
| Peak memory | 200840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086039142 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1086039142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3353920698 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 309792109 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 10:41:14 PM UTC 24 |
| Finished | Oct 09 10:41:17 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353920698 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.3353920698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2914894117 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 85380400 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:41:21 PM UTC 24 |
| Finished | Oct 09 10:41:23 PM UTC 24 |
| Peak memory | 199052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2914894117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.2914894117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3536749949 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 18207303 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 10:41:19 PM UTC 24 |
| Finished | Oct 09 10:41:21 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536749949 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3536749949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.4029344541 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 18095023 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 10:41:19 PM UTC 24 |
| Finished | Oct 09 10:41:21 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029344541 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4029344541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3091899223 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 70109896 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:41:20 PM UTC 24 |
| Finished | Oct 09 10:41:22 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091899223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.3091899223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3221298808 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 204309140 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 10:41:18 PM UTC 24 |
| Finished | Oct 09 10:41:21 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221298808 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3221298808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3597980880 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 49523566 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:41:18 PM UTC 24 |
| Finished | Oct 09 10:41:20 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597980880 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.3597980880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2671880878 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1698214508653 ps |
| CPU time | 819.04 seconds |
| Started | Oct 09 09:55:24 PM UTC 24 |
| Finished | Oct 09 10:09:14 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671880878 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2671880878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.4068257087 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 212158313 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 09:56:46 PM UTC 24 |
| Finished | Oct 09 09:56:49 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068257087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4068257087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.367097362 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2858370877980 ps |
| CPU time | 781.09 seconds |
| Started | Oct 09 09:56:46 PM UTC 24 |
| Finished | Oct 09 10:09:56 PM UTC 24 |
| Peak memory | 200824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367097362 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.367097362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.2496921990 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 23474003275 ps |
| CPU time | 14.41 seconds |
| Started | Oct 09 09:56:46 PM UTC 24 |
| Finished | Oct 09 09:57:02 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496921990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2496921990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3156905396 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 109020697884 ps |
| CPU time | 168.71 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 09:59:39 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156905396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3156905396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.4074871046 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 172563457 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 09:56:49 PM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074871046 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4074871046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3851912103 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 216461941 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 09:56:49 PM UTC 24 |
| Peak memory | 199284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851912103 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3851912103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.38199568 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 60515611997 ps |
| CPU time | 95.05 seconds |
| Started | Oct 09 09:56:50 PM UTC 24 |
| Finished | Oct 09 09:58:27 PM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38199568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.38199568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.2939896856 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 51493378747 ps |
| CPU time | 56.78 seconds |
| Started | Oct 09 09:56:50 PM UTC 24 |
| Finished | Oct 09 09:57:49 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939896856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2939896856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.2817570825 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 120380933881 ps |
| CPU time | 251.81 seconds |
| Started | Oct 09 10:24:48 PM UTC 24 |
| Finished | Oct 09 10:29:04 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817570825 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2817570825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.549409085 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 358621429463 ps |
| CPU time | 884.18 seconds |
| Started | Oct 09 10:24:51 PM UTC 24 |
| Finished | Oct 09 10:39:45 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549409085 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.549409085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3374891269 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 30963662362 ps |
| CPU time | 51.29 seconds |
| Started | Oct 09 10:25:02 PM UTC 24 |
| Finished | Oct 09 10:25:54 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374891269 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3374891269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.2540496125 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 201303885261 ps |
| CPU time | 174 seconds |
| Started | Oct 09 10:25:04 PM UTC 24 |
| Finished | Oct 09 10:28:01 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540496125 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2540496125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.4280963575 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1057126609600 ps |
| CPU time | 946.14 seconds |
| Started | Oct 09 10:25:09 PM UTC 24 |
| Finished | Oct 09 10:41:05 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280963575 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4280963575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.1806813720 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 557959736466 ps |
| CPU time | 2376.07 seconds |
| Started | Oct 09 10:25:12 PM UTC 24 |
| Finished | Oct 09 11:05:15 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806813720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1806813720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.3138437722 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 16140536291 ps |
| CPU time | 34.41 seconds |
| Started | Oct 09 09:56:53 PM UTC 24 |
| Finished | Oct 09 09:57:29 PM UTC 24 |
| Peak memory | 201288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138437722 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.3138437722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.2725789965 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 84748225182 ps |
| CPU time | 213.18 seconds |
| Started | Oct 09 09:56:53 PM UTC 24 |
| Finished | Oct 09 10:00:29 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725789965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2725789965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.565167307 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 37816488137 ps |
| CPU time | 360.29 seconds |
| Started | Oct 09 09:56:53 PM UTC 24 |
| Finished | Oct 09 10:02:58 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565167307 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.565167307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3189046508 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 132372405783 ps |
| CPU time | 352.44 seconds |
| Started | Oct 09 09:56:55 PM UTC 24 |
| Finished | Oct 09 10:02:53 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189046508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3189046508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.1875972452 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 295493741993 ps |
| CPU time | 106.91 seconds |
| Started | Oct 09 09:57:01 PM UTC 24 |
| Finished | Oct 09 09:58:50 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875972452 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.1875972452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.3393838939 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 120289730822 ps |
| CPU time | 111.19 seconds |
| Started | Oct 09 10:25:13 PM UTC 24 |
| Finished | Oct 09 10:27:06 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393838939 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3393838939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.2157037616 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 118162103466 ps |
| CPU time | 705.38 seconds |
| Started | Oct 09 10:25:28 PM UTC 24 |
| Finished | Oct 09 10:37:23 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157037616 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2157037616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.3273407259 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 328153534417 ps |
| CPU time | 484.99 seconds |
| Started | Oct 09 10:26:01 PM UTC 24 |
| Finished | Oct 09 10:34:12 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273407259 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3273407259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.1505418869 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 305309953503 ps |
| CPU time | 661.59 seconds |
| Started | Oct 09 10:26:15 PM UTC 24 |
| Finished | Oct 09 10:37:25 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505418869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1505418869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.3975650467 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 170855187375 ps |
| CPU time | 587.5 seconds |
| Started | Oct 09 10:26:59 PM UTC 24 |
| Finished | Oct 09 10:36:54 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975650467 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3975650467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.3182044953 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 72373269379 ps |
| CPU time | 58.99 seconds |
| Started | Oct 09 10:27:07 PM UTC 24 |
| Finished | Oct 09 10:28:08 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182044953 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3182044953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.4099435726 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 301538462532 ps |
| CPU time | 585.04 seconds |
| Started | Oct 09 09:57:05 PM UTC 24 |
| Finished | Oct 09 10:06:57 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099435726 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.4099435726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.3451500705 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 76945881190 ps |
| CPU time | 183.61 seconds |
| Started | Oct 09 09:57:03 PM UTC 24 |
| Finished | Oct 09 10:00:10 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451500705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3451500705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.3941169633 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 156113230931 ps |
| CPU time | 202.53 seconds |
| Started | Oct 09 10:27:50 PM UTC 24 |
| Finished | Oct 09 10:31:16 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941169633 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3941169633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.963217856 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 158360834170 ps |
| CPU time | 296.1 seconds |
| Started | Oct 09 10:27:56 PM UTC 24 |
| Finished | Oct 09 10:32:57 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963217856 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.963217856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.395783513 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 506263060349 ps |
| CPU time | 1289.45 seconds |
| Started | Oct 09 10:28:02 PM UTC 24 |
| Finished | Oct 09 10:49:46 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395783513 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.395783513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.399456489 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 228792085209 ps |
| CPU time | 400.27 seconds |
| Started | Oct 09 10:28:20 PM UTC 24 |
| Finished | Oct 09 10:35:05 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399456489 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.399456489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.4070629104 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 163619540892 ps |
| CPU time | 507.79 seconds |
| Started | Oct 09 10:28:22 PM UTC 24 |
| Finished | Oct 09 10:36:56 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070629104 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4070629104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.280684554 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 214176707329 ps |
| CPU time | 109.9 seconds |
| Started | Oct 09 09:57:12 PM UTC 24 |
| Finished | Oct 09 09:59:04 PM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280684554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.280684554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.271793116 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 41382008662 ps |
| CPU time | 107.39 seconds |
| Started | Oct 09 09:57:20 PM UTC 24 |
| Finished | Oct 09 09:59:10 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271793116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.271793116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.2037397755 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 613295749487 ps |
| CPU time | 617.07 seconds |
| Started | Oct 09 10:28:22 PM UTC 24 |
| Finished | Oct 09 10:38:46 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037397755 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2037397755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1013599155 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 240468413444 ps |
| CPU time | 374.8 seconds |
| Started | Oct 09 10:29:04 PM UTC 24 |
| Finished | Oct 09 10:35:24 PM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013599155 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1013599155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.1641270605 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 210362781959 ps |
| CPU time | 625.84 seconds |
| Started | Oct 09 10:29:10 PM UTC 24 |
| Finished | Oct 09 10:39:43 PM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641270605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1641270605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.2681243767 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 97980122518 ps |
| CPU time | 298.89 seconds |
| Started | Oct 09 10:29:29 PM UTC 24 |
| Finished | Oct 09 10:34:33 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681243767 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2681243767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.759062775 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 144381742507 ps |
| CPU time | 573.86 seconds |
| Started | Oct 09 10:29:58 PM UTC 24 |
| Finished | Oct 09 10:39:39 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759062775 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.759062775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.2676494006 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 162720131020 ps |
| CPU time | 168.13 seconds |
| Started | Oct 09 10:30:13 PM UTC 24 |
| Finished | Oct 09 10:33:04 PM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676494006 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2676494006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.3730233813 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 67685361313 ps |
| CPU time | 2612.55 seconds |
| Started | Oct 09 10:30:24 PM UTC 24 |
| Finished | Oct 09 11:14:27 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730233813 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3730233813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.3391665856 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 149562049393 ps |
| CPU time | 349.24 seconds |
| Started | Oct 09 09:57:32 PM UTC 24 |
| Finished | Oct 09 10:03:27 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391665856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3391665856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.413724462 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 259394261908 ps |
| CPU time | 2533.83 seconds |
| Started | Oct 09 09:57:30 PM UTC 24 |
| Finished | Oct 09 10:40:13 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413724462 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.413724462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.2296119138 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 183938811442 ps |
| CPU time | 572.72 seconds |
| Started | Oct 09 10:30:48 PM UTC 24 |
| Finished | Oct 09 10:40:28 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296119138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2296119138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.265497243 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 66258053657 ps |
| CPU time | 57 seconds |
| Started | Oct 09 10:31:17 PM UTC 24 |
| Finished | Oct 09 10:32:16 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265497243 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.265497243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.323351967 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 391336278909 ps |
| CPU time | 1138.17 seconds |
| Started | Oct 09 10:31:29 PM UTC 24 |
| Finished | Oct 09 10:50:40 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323351967 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.323351967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.537075207 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 84556679107 ps |
| CPU time | 151.45 seconds |
| Started | Oct 09 10:31:31 PM UTC 24 |
| Finished | Oct 09 10:34:05 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537075207 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.537075207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2118833166 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 516648081904 ps |
| CPU time | 340.1 seconds |
| Started | Oct 09 10:32:17 PM UTC 24 |
| Finished | Oct 09 10:38:02 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118833166 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2118833166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.711525645 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 549296849712 ps |
| CPU time | 1002.68 seconds |
| Started | Oct 09 10:32:24 PM UTC 24 |
| Finished | Oct 09 10:49:18 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711525645 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.711525645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.1320311042 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 67310569826 ps |
| CPU time | 126.98 seconds |
| Started | Oct 09 10:32:42 PM UTC 24 |
| Finished | Oct 09 10:34:52 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320311042 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1320311042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.2715752582 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 327431142123 ps |
| CPU time | 646.31 seconds |
| Started | Oct 09 09:57:50 PM UTC 24 |
| Finished | Oct 09 10:08:44 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715752582 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.2715752582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.3269139849 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 59906601434 ps |
| CPU time | 188.33 seconds |
| Started | Oct 09 09:57:48 PM UTC 24 |
| Finished | Oct 09 10:00:59 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269139849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3269139849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.2469594955 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 41875997728 ps |
| CPU time | 160.67 seconds |
| Started | Oct 09 09:57:53 PM UTC 24 |
| Finished | Oct 09 10:00:37 PM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469594955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2469594955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.1492802953 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 388935114827 ps |
| CPU time | 324.26 seconds |
| Started | Oct 09 10:33:05 PM UTC 24 |
| Finished | Oct 09 10:38:34 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492802953 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1492802953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.3737646721 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6783885997 ps |
| CPU time | 9.34 seconds |
| Started | Oct 09 10:33:31 PM UTC 24 |
| Finished | Oct 09 10:33:41 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737646721 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3737646721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.18881352 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 283961910422 ps |
| CPU time | 1256.44 seconds |
| Started | Oct 09 10:33:42 PM UTC 24 |
| Finished | Oct 09 10:54:53 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18881352 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.18881352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.3929054136 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 155096832787 ps |
| CPU time | 279.17 seconds |
| Started | Oct 09 10:34:06 PM UTC 24 |
| Finished | Oct 09 10:38:49 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929054136 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3929054136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.32427551 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 38331218379 ps |
| CPU time | 81.21 seconds |
| Started | Oct 09 10:34:13 PM UTC 24 |
| Finished | Oct 09 10:35:36 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32427551 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.32427551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.705331443 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 20622247272 ps |
| CPU time | 23.04 seconds |
| Started | Oct 09 10:34:52 PM UTC 24 |
| Finished | Oct 09 10:35:17 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705331443 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.705331443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.2272147445 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 325247725330 ps |
| CPU time | 252.27 seconds |
| Started | Oct 09 10:35:06 PM UTC 24 |
| Finished | Oct 09 10:39:23 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272147445 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2272147445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.2942361858 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 601081990599 ps |
| CPU time | 346.69 seconds |
| Started | Oct 09 09:58:07 PM UTC 24 |
| Finished | Oct 09 10:03:59 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942361858 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2942361858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.4079641030 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 379106747693 ps |
| CPU time | 141.89 seconds |
| Started | Oct 09 09:57:55 PM UTC 24 |
| Finished | Oct 09 10:00:20 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079641030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4079641030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1709986377 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 140359371039 ps |
| CPU time | 69.13 seconds |
| Started | Oct 09 09:58:08 PM UTC 24 |
| Finished | Oct 09 09:59:19 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709986377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1709986377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.3171759352 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 161439070450 ps |
| CPU time | 242.8 seconds |
| Started | Oct 09 10:35:17 PM UTC 24 |
| Finished | Oct 09 10:39:24 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171759352 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3171759352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.2293808439 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 105021876509 ps |
| CPU time | 182.39 seconds |
| Started | Oct 09 10:35:26 PM UTC 24 |
| Finished | Oct 09 10:38:31 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293808439 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2293808439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.4135808079 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 192643774780 ps |
| CPU time | 1037.26 seconds |
| Started | Oct 09 10:35:37 PM UTC 24 |
| Finished | Oct 09 10:53:07 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135808079 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4135808079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.4039620319 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 34417098054 ps |
| CPU time | 60.69 seconds |
| Started | Oct 09 10:35:38 PM UTC 24 |
| Finished | Oct 09 10:36:40 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039620319 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4039620319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.2086480354 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 20896466402 ps |
| CPU time | 171.55 seconds |
| Started | Oct 09 10:35:53 PM UTC 24 |
| Finished | Oct 09 10:38:48 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086480354 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2086480354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.3925306400 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 94170307966 ps |
| CPU time | 235.98 seconds |
| Started | Oct 09 10:35:54 PM UTC 24 |
| Finished | Oct 09 10:39:54 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925306400 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3925306400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.846271320 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 136146106542 ps |
| CPU time | 445.19 seconds |
| Started | Oct 09 10:35:56 PM UTC 24 |
| Finished | Oct 09 10:43:27 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846271320 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.846271320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.4294224035 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 64428052301 ps |
| CPU time | 220.85 seconds |
| Started | Oct 09 10:36:04 PM UTC 24 |
| Finished | Oct 09 10:39:49 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294224035 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4294224035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.236594358 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 243324616956 ps |
| CPU time | 552.35 seconds |
| Started | Oct 09 09:58:29 PM UTC 24 |
| Finished | Oct 09 10:07:48 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236594358 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.236594358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.457509922 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 617574493214 ps |
| CPU time | 257.81 seconds |
| Started | Oct 09 09:58:27 PM UTC 24 |
| Finished | Oct 09 10:02:48 PM UTC 24 |
| Peak memory | 201152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457509922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.457509922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.68320677 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 118770378822 ps |
| CPU time | 504.38 seconds |
| Started | Oct 09 09:58:24 PM UTC 24 |
| Finished | Oct 09 10:06:55 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68320677 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.68320677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.1357170653 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 256755220 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 09:58:35 PM UTC 24 |
| Finished | Oct 09 09:58:37 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357170653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1357170653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all_with_rand_reset.1633161145 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2269061866 ps |
| CPU time | 26.63 seconds |
| Started | Oct 09 09:58:37 PM UTC 24 |
| Finished | Oct 09 09:59:05 PM UTC 24 |
| Peak memory | 205620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1633161145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.rv_timer_stress_all_with_rand_reset.1633161145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.4157124743 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 94936112444 ps |
| CPU time | 576.49 seconds |
| Started | Oct 09 10:36:41 PM UTC 24 |
| Finished | Oct 09 10:46:25 PM UTC 24 |
| Peak memory | 201272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157124743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4157124743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.924652599 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 122566077571 ps |
| CPU time | 329.47 seconds |
| Started | Oct 09 10:36:55 PM UTC 24 |
| Finished | Oct 09 10:42:29 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924652599 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.924652599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.1992283955 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 308330837755 ps |
| CPU time | 375.09 seconds |
| Started | Oct 09 10:37:10 PM UTC 24 |
| Finished | Oct 09 10:43:30 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992283955 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1992283955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1520649181 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 421569389889 ps |
| CPU time | 794.65 seconds |
| Started | Oct 09 10:37:24 PM UTC 24 |
| Finished | Oct 09 10:50:50 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520649181 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1520649181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.693666650 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 750441705391 ps |
| CPU time | 950.36 seconds |
| Started | Oct 09 10:37:26 PM UTC 24 |
| Finished | Oct 09 10:53:29 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693666650 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.693666650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.2504608856 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 22482041370 ps |
| CPU time | 67.44 seconds |
| Started | Oct 09 10:37:51 PM UTC 24 |
| Finished | Oct 09 10:39:01 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504608856 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2504608856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.2779949416 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 363600329931 ps |
| CPU time | 152.09 seconds |
| Started | Oct 09 10:38:03 PM UTC 24 |
| Finished | Oct 09 10:40:37 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779949416 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2779949416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3458799825 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 35005830163 ps |
| CPU time | 39.05 seconds |
| Started | Oct 09 09:59:04 PM UTC 24 |
| Finished | Oct 09 09:59:45 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458799825 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3458799825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.3126495537 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 378617680399 ps |
| CPU time | 382.38 seconds |
| Started | Oct 09 09:58:51 PM UTC 24 |
| Finished | Oct 09 10:05:19 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126495537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3126495537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.592598579 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1975302962 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 09:59:06 PM UTC 24 |
| Finished | Oct 09 09:59:11 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592598579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.592598579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all_with_rand_reset.908928718 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2642308867 ps |
| CPU time | 32.17 seconds |
| Started | Oct 09 09:59:08 PM UTC 24 |
| Finished | Oct 09 09:59:41 PM UTC 24 |
| Peak memory | 205300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=908928718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.908928718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3142633191 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 243131181243 ps |
| CPU time | 315.16 seconds |
| Started | Oct 09 10:38:21 PM UTC 24 |
| Finished | Oct 09 10:43:41 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142633191 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3142633191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.867333295 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 254128564562 ps |
| CPU time | 459.46 seconds |
| Started | Oct 09 10:38:32 PM UTC 24 |
| Finished | Oct 09 10:46:18 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867333295 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.867333295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3104077574 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 127699653954 ps |
| CPU time | 167.12 seconds |
| Started | Oct 09 10:38:35 PM UTC 24 |
| Finished | Oct 09 10:41:25 PM UTC 24 |
| Peak memory | 201208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104077574 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3104077574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.3158785850 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 47752209216 ps |
| CPU time | 476.72 seconds |
| Started | Oct 09 10:38:47 PM UTC 24 |
| Finished | Oct 09 10:46:50 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158785850 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3158785850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.3806777002 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 603728185769 ps |
| CPU time | 482.15 seconds |
| Started | Oct 09 10:38:49 PM UTC 24 |
| Finished | Oct 09 10:46:57 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806777002 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3806777002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.400433952 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 58598436633 ps |
| CPU time | 96.86 seconds |
| Started | Oct 09 10:39:20 PM UTC 24 |
| Finished | Oct 09 10:40:59 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400433952 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.400433952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.3286722204 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 17420161089 ps |
| CPU time | 19.42 seconds |
| Started | Oct 09 09:59:24 PM UTC 24 |
| Finished | Oct 09 09:59:45 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286722204 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3286722204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.2408117780 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 563579517536 ps |
| CPU time | 294.06 seconds |
| Started | Oct 09 09:59:20 PM UTC 24 |
| Finished | Oct 09 10:04:18 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408117780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2408117780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.3900101307 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 68696371868 ps |
| CPU time | 44.17 seconds |
| Started | Oct 09 09:59:12 PM UTC 24 |
| Finished | Oct 09 09:59:58 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900101307 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3900101307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.2793894460 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5030130349896 ps |
| CPU time | 1073.97 seconds |
| Started | Oct 09 09:59:42 PM UTC 24 |
| Finished | Oct 09 10:17:49 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793894460 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.2793894460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.2643244203 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 406170888067 ps |
| CPU time | 1554.13 seconds |
| Started | Oct 09 10:39:38 PM UTC 24 |
| Finished | Oct 09 11:05:50 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643244203 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2643244203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.676687750 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 331341981959 ps |
| CPU time | 694.92 seconds |
| Started | Oct 09 10:39:40 PM UTC 24 |
| Finished | Oct 09 10:51:23 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676687750 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.676687750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.4125251417 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 43850616293 ps |
| CPU time | 196.92 seconds |
| Started | Oct 09 10:39:44 PM UTC 24 |
| Finished | Oct 09 10:43:04 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125251417 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4125251417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.1768040801 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 282057068763 ps |
| CPU time | 1343.74 seconds |
| Started | Oct 09 10:39:46 PM UTC 24 |
| Finished | Oct 09 11:02:25 PM UTC 24 |
| Peak memory | 201400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768040801 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1768040801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.2503804896 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 101643842867 ps |
| CPU time | 323.02 seconds |
| Started | Oct 09 10:39:49 PM UTC 24 |
| Finished | Oct 09 10:45:17 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503804896 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2503804896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.4287118017 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 99007957807 ps |
| CPU time | 220.91 seconds |
| Started | Oct 09 10:40:11 PM UTC 24 |
| Finished | Oct 09 10:43:56 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287118017 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4287118017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2551593439 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 103156647780 ps |
| CPU time | 227.32 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 10:00:38 PM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551593439 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2551593439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.3632339730 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 189558171368 ps |
| CPU time | 200.37 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 10:00:11 PM UTC 24 |
| Peak memory | 200868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632339730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3632339730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.2692617995 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 642102290978 ps |
| CPU time | 1719.11 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 10:25:48 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692617995 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2692617995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.2604424939 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7053124927 ps |
| CPU time | 11.66 seconds |
| Started | Oct 09 09:56:47 PM UTC 24 |
| Finished | Oct 09 09:57:01 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604424939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2604424939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1728111116 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 301031019 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:56:50 PM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728111116 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1728111116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2772759489 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 884248372285 ps |
| CPU time | 948.15 seconds |
| Started | Oct 09 09:59:46 PM UTC 24 |
| Finished | Oct 09 10:15:45 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772759489 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2772759489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.1158211027 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 217606701480 ps |
| CPU time | 153.51 seconds |
| Started | Oct 09 09:59:43 PM UTC 24 |
| Finished | Oct 09 10:02:19 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158211027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1158211027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.1141935435 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 17094397922 ps |
| CPU time | 68.45 seconds |
| Started | Oct 09 09:59:42 PM UTC 24 |
| Finished | Oct 09 10:00:53 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141935435 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1141935435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.2225773002 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 268022593680 ps |
| CPU time | 140.99 seconds |
| Started | Oct 09 09:59:47 PM UTC 24 |
| Finished | Oct 09 10:02:10 PM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225773002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2225773002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.561704218 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 466065631727 ps |
| CPU time | 439.37 seconds |
| Started | Oct 09 09:59:59 PM UTC 24 |
| Finished | Oct 09 10:07:24 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561704218 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.561704218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.286976022 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2229328480 ps |
| CPU time | 23.06 seconds |
| Started | Oct 09 09:59:58 PM UTC 24 |
| Finished | Oct 09 10:00:22 PM UTC 24 |
| Peak memory | 203516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=286976022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.286976022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.2869417199 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 78663088478 ps |
| CPU time | 136.02 seconds |
| Started | Oct 09 10:00:20 PM UTC 24 |
| Finished | Oct 09 10:02:39 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869417199 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.2869417199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.1511962278 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 150718401354 ps |
| CPU time | 284.7 seconds |
| Started | Oct 09 10:00:12 PM UTC 24 |
| Finished | Oct 09 10:05:01 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511962278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1511962278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.2989658069 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 121483508511 ps |
| CPU time | 325.7 seconds |
| Started | Oct 09 10:00:23 PM UTC 24 |
| Finished | Oct 09 10:05:54 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989658069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2989658069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.3816057017 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 173888953477 ps |
| CPU time | 795.41 seconds |
| Started | Oct 09 10:00:29 PM UTC 24 |
| Finished | Oct 09 10:13:56 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816057017 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.3816057017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.3182800153 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 14236982619 ps |
| CPU time | 41.33 seconds |
| Started | Oct 09 10:00:40 PM UTC 24 |
| Finished | Oct 09 10:01:23 PM UTC 24 |
| Peak memory | 201024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182800153 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.3182800153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.3482610928 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 126874520420 ps |
| CPU time | 185.06 seconds |
| Started | Oct 09 10:00:38 PM UTC 24 |
| Finished | Oct 09 10:03:46 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482610928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3482610928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.2324252187 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 65806919036 ps |
| CPU time | 276.08 seconds |
| Started | Oct 09 10:00:31 PM UTC 24 |
| Finished | Oct 09 10:05:12 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324252187 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2324252187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1980497285 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 87557220 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 10:00:45 PM UTC 24 |
| Finished | Oct 09 10:00:47 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980497285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1980497285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.150070935 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 371005232492 ps |
| CPU time | 765.37 seconds |
| Started | Oct 09 10:00:54 PM UTC 24 |
| Finished | Oct 09 10:13:48 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150070935 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.150070935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.769789541 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 276376651526 ps |
| CPU time | 393.37 seconds |
| Started | Oct 09 10:01:24 PM UTC 24 |
| Finished | Oct 09 10:08:03 PM UTC 24 |
| Peak memory | 201316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769789541 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.769789541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1339851726 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 69026568887 ps |
| CPU time | 150.81 seconds |
| Started | Oct 09 10:01:23 PM UTC 24 |
| Finished | Oct 09 10:03:57 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339851726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1339851726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.814235915 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 113693441868 ps |
| CPU time | 60.48 seconds |
| Started | Oct 09 10:01:00 PM UTC 24 |
| Finished | Oct 09 10:02:02 PM UTC 24 |
| Peak memory | 200924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814235915 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.814235915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.572047929 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 15093456690 ps |
| CPU time | 48.69 seconds |
| Started | Oct 09 10:01:28 PM UTC 24 |
| Finished | Oct 09 10:02:19 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572047929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.572047929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all_with_rand_reset.650753512 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5155360075 ps |
| CPU time | 58.9 seconds |
| Started | Oct 09 10:01:30 PM UTC 24 |
| Finished | Oct 09 10:02:30 PM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=650753512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.650753512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.66382624 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 137354297817 ps |
| CPU time | 64.36 seconds |
| Started | Oct 09 10:02:05 PM UTC 24 |
| Finished | Oct 09 10:03:11 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66382624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.66382624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.235662694 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 184246916982 ps |
| CPU time | 178.05 seconds |
| Started | Oct 09 10:02:03 PM UTC 24 |
| Finished | Oct 09 10:05:04 PM UTC 24 |
| Peak memory | 201212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235662694 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.235662694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.1203303415 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 77906018437 ps |
| CPU time | 18.07 seconds |
| Started | Oct 09 10:02:49 PM UTC 24 |
| Finished | Oct 09 10:03:08 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203303415 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.1203303415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.3425429651 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 405336937351 ps |
| CPU time | 249.48 seconds |
| Started | Oct 09 10:02:40 PM UTC 24 |
| Finished | Oct 09 10:06:53 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425429651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3425429651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.2687637588 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 113263309055 ps |
| CPU time | 91.49 seconds |
| Started | Oct 09 10:02:31 PM UTC 24 |
| Finished | Oct 09 10:04:05 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687637588 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2687637588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.3150181180 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1199852744871 ps |
| CPU time | 1650.4 seconds |
| Started | Oct 09 10:02:59 PM UTC 24 |
| Finished | Oct 09 10:30:48 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150181180 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.3150181180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3797892814 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 276952741981 ps |
| CPU time | 573.87 seconds |
| Started | Oct 09 10:03:12 PM UTC 24 |
| Finished | Oct 09 10:12:53 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797892814 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3797892814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.3333586803 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 520068778008 ps |
| CPU time | 305.91 seconds |
| Started | Oct 09 10:03:09 PM UTC 24 |
| Finished | Oct 09 10:08:19 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333586803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3333586803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.725398255 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 216974386681 ps |
| CPU time | 65.6 seconds |
| Started | Oct 09 10:03:27 PM UTC 24 |
| Finished | Oct 09 10:04:35 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725398255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.725398255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.2741085137 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 220561989826 ps |
| CPU time | 1906.1 seconds |
| Started | Oct 09 10:03:44 PM UTC 24 |
| Finished | Oct 09 10:35:52 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741085137 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.2741085137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.3175354937 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2096744615330 ps |
| CPU time | 723.76 seconds |
| Started | Oct 09 10:03:55 PM UTC 24 |
| Finished | Oct 09 10:16:07 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175354937 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.3175354937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.1846856514 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 133625437766 ps |
| CPU time | 75.39 seconds |
| Started | Oct 09 10:03:55 PM UTC 24 |
| Finished | Oct 09 10:05:12 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846856514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1846856514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.2197873567 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 215257991938 ps |
| CPU time | 602.21 seconds |
| Started | Oct 09 10:03:47 PM UTC 24 |
| Finished | Oct 09 10:13:56 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197873567 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2197873567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2288060823 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 847333063 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 10:03:58 PM UTC 24 |
| Finished | Oct 09 10:04:01 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288060823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2288060823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.4245273869 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 439362018826 ps |
| CPU time | 771.63 seconds |
| Started | Oct 09 10:04:01 PM UTC 24 |
| Finished | Oct 09 10:17:01 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245273869 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.4245273869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.2474960759 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 117435940925 ps |
| CPU time | 217.08 seconds |
| Started | Oct 09 10:04:15 PM UTC 24 |
| Finished | Oct 09 10:07:56 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474960759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2474960759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.819748078 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 30521059901 ps |
| CPU time | 122.99 seconds |
| Started | Oct 09 10:04:06 PM UTC 24 |
| Finished | Oct 09 10:06:12 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819748078 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.819748078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.340179665 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 39190412475 ps |
| CPU time | 138.71 seconds |
| Started | Oct 09 10:04:19 PM UTC 24 |
| Finished | Oct 09 10:06:41 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340179665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.340179665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.834958521 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1855034987689 ps |
| CPU time | 851.53 seconds |
| Started | Oct 09 10:04:28 PM UTC 24 |
| Finished | Oct 09 10:18:50 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834958521 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.834958521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.2215017497 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6665313914 ps |
| CPU time | 98.47 seconds |
| Started | Oct 09 10:04:19 PM UTC 24 |
| Finished | Oct 09 10:06:00 PM UTC 24 |
| Peak memory | 205228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2215017497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.2215017497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2658206935 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 252102355333 ps |
| CPU time | 524.68 seconds |
| Started | Oct 09 10:04:58 PM UTC 24 |
| Finished | Oct 09 10:13:50 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658206935 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2658206935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.3255528136 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 40217832831 ps |
| CPU time | 58.25 seconds |
| Started | Oct 09 10:04:52 PM UTC 24 |
| Finished | Oct 09 10:05:52 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255528136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3255528136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1586826843 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 767084709363 ps |
| CPU time | 1116.35 seconds |
| Started | Oct 09 10:04:36 PM UTC 24 |
| Finished | Oct 09 10:23:25 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586826843 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1586826843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.498954641 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 423807923554 ps |
| CPU time | 129.07 seconds |
| Started | Oct 09 10:05:01 PM UTC 24 |
| Finished | Oct 09 10:07:13 PM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498954641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.498954641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.2161048389 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 950511453922 ps |
| CPU time | 345.75 seconds |
| Started | Oct 09 10:05:12 PM UTC 24 |
| Finished | Oct 09 10:11:02 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161048389 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.2161048389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.1540437958 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 205032844138 ps |
| CPU time | 583.56 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:06:39 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540437958 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.1540437958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3145983165 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 256782275800 ps |
| CPU time | 214.48 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:00:26 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145983165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3145983165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3572749851 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 70744903988 ps |
| CPU time | 30.68 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:20 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572749851 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3572749851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.459506177 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 355961999 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:56:50 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459506177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.459506177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.2214743153 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 48190486 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:56:50 PM UTC 24 |
| Peak memory | 230492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214743153 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2214743153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3438766526 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 101328601370 ps |
| CPU time | 197.85 seconds |
| Started | Oct 09 10:05:19 PM UTC 24 |
| Finished | Oct 09 10:08:40 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438766526 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3438766526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.3671831283 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 195250532276 ps |
| CPU time | 290.4 seconds |
| Started | Oct 09 10:05:18 PM UTC 24 |
| Finished | Oct 09 10:10:13 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671831283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3671831283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.1220724923 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 303298672378 ps |
| CPU time | 435.37 seconds |
| Started | Oct 09 10:05:13 PM UTC 24 |
| Finished | Oct 09 10:12:35 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220724923 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1220724923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.676004142 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 56753594 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 10:05:53 PM UTC 24 |
| Finished | Oct 09 10:05:56 PM UTC 24 |
| Peak memory | 199628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=676004142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.676004142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.1111440956 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 484201609628 ps |
| CPU time | 281.64 seconds |
| Started | Oct 09 10:06:00 PM UTC 24 |
| Finished | Oct 09 10:10:46 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111440956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1111440956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.1073195974 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 79731064768 ps |
| CPU time | 273.96 seconds |
| Started | Oct 09 10:05:57 PM UTC 24 |
| Finished | Oct 09 10:10:35 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073195974 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1073195974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.1132897169 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 481302855176 ps |
| CPU time | 182.59 seconds |
| Started | Oct 09 10:06:05 PM UTC 24 |
| Finished | Oct 09 10:09:11 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132897169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1132897169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.782413562 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 6641216540343 ps |
| CPU time | 1795.64 seconds |
| Started | Oct 09 10:06:54 PM UTC 24 |
| Finished | Oct 09 10:37:09 PM UTC 24 |
| Peak memory | 201060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782413562 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.782413562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.565529949 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 26567533909 ps |
| CPU time | 43.25 seconds |
| Started | Oct 09 10:06:43 PM UTC 24 |
| Finished | Oct 09 10:07:27 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565529949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.565529949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.2735565511 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 172432175498 ps |
| CPU time | 87.58 seconds |
| Started | Oct 09 10:06:56 PM UTC 24 |
| Finished | Oct 09 10:08:25 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735565511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2735565511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1942125585 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1018895294747 ps |
| CPU time | 593.66 seconds |
| Started | Oct 09 10:07:25 PM UTC 24 |
| Finished | Oct 09 10:17:26 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942125585 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1942125585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.3194740349 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 89471810881 ps |
| CPU time | 110.83 seconds |
| Started | Oct 09 10:07:19 PM UTC 24 |
| Finished | Oct 09 10:09:12 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194740349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3194740349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1855544494 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 666423207846 ps |
| CPU time | 743.3 seconds |
| Started | Oct 09 10:07:15 PM UTC 24 |
| Finished | Oct 09 10:19:47 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855544494 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1855544494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.1824342924 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 49885637256 ps |
| CPU time | 843.78 seconds |
| Started | Oct 09 10:07:28 PM UTC 24 |
| Finished | Oct 09 10:21:42 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824342924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1824342924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.730453461 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 377181582692 ps |
| CPU time | 289.9 seconds |
| Started | Oct 09 10:07:49 PM UTC 24 |
| Finished | Oct 09 10:12:43 PM UTC 24 |
| Peak memory | 200996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730453461 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.730453461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.2239263954 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 486718368321 ps |
| CPU time | 229.19 seconds |
| Started | Oct 09 10:07:48 PM UTC 24 |
| Finished | Oct 09 10:11:40 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239263954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2239263954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1701234927 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 193372809736 ps |
| CPU time | 883.77 seconds |
| Started | Oct 09 10:07:41 PM UTC 24 |
| Finished | Oct 09 10:22:34 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701234927 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1701234927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.2653159483 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 67132244626 ps |
| CPU time | 66.76 seconds |
| Started | Oct 09 10:07:49 PM UTC 24 |
| Finished | Oct 09 10:08:57 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653159483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2653159483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.801985428 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10927015697 ps |
| CPU time | 101.88 seconds |
| Started | Oct 09 10:07:54 PM UTC 24 |
| Finished | Oct 09 10:09:38 PM UTC 24 |
| Peak memory | 205564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=801985428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.801985428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.913714829 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 94735221826 ps |
| CPU time | 192.61 seconds |
| Started | Oct 09 10:08:26 PM UTC 24 |
| Finished | Oct 09 10:11:42 PM UTC 24 |
| Peak memory | 200988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913714829 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.913714829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.2876478507 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 201982105703 ps |
| CPU time | 129.02 seconds |
| Started | Oct 09 10:08:20 PM UTC 24 |
| Finished | Oct 09 10:10:32 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876478507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2876478507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.402313412 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 735149901512 ps |
| CPU time | 411.1 seconds |
| Started | Oct 09 10:08:04 PM UTC 24 |
| Finished | Oct 09 10:15:00 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402313412 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.402313412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.3468945629 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 19835889208 ps |
| CPU time | 37.2 seconds |
| Started | Oct 09 10:08:41 PM UTC 24 |
| Finished | Oct 09 10:09:20 PM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468945629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3468945629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all_with_rand_reset.961544199 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2066409683 ps |
| CPU time | 35.84 seconds |
| Started | Oct 09 10:08:45 PM UTC 24 |
| Finished | Oct 09 10:09:22 PM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=961544199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.961544199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.1695251028 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 156573547890 ps |
| CPU time | 298.66 seconds |
| Started | Oct 09 10:09:15 PM UTC 24 |
| Finished | Oct 09 10:14:18 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695251028 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1695251028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3431244334 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 731426484179 ps |
| CPU time | 99.86 seconds |
| Started | Oct 09 10:09:13 PM UTC 24 |
| Finished | Oct 09 10:10:55 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431244334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3431244334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.4194699205 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 83008476506 ps |
| CPU time | 95.25 seconds |
| Started | Oct 09 10:09:58 PM UTC 24 |
| Finished | Oct 09 10:11:36 PM UTC 24 |
| Peak memory | 201412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194699205 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.4194699205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.3502580698 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 127497409210 ps |
| CPU time | 275.25 seconds |
| Started | Oct 09 10:09:39 PM UTC 24 |
| Finished | Oct 09 10:14:19 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502580698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3502580698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.3362152021 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 110281283981 ps |
| CPU time | 192.69 seconds |
| Started | Oct 09 10:09:26 PM UTC 24 |
| Finished | Oct 09 10:12:42 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362152021 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3362152021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.2486395446 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 31384689396 ps |
| CPU time | 140.96 seconds |
| Started | Oct 09 10:10:14 PM UTC 24 |
| Finished | Oct 09 10:12:37 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486395446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2486395446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.2679882107 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 533807276351 ps |
| CPU time | 245.17 seconds |
| Started | Oct 09 10:10:33 PM UTC 24 |
| Finished | Oct 09 10:14:41 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679882107 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.2679882107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2893413826 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 15714380726 ps |
| CPU time | 24.87 seconds |
| Started | Oct 09 10:10:47 PM UTC 24 |
| Finished | Oct 09 10:11:13 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893413826 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2893413826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.3171500948 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 62167551347 ps |
| CPU time | 200.64 seconds |
| Started | Oct 09 10:10:36 PM UTC 24 |
| Finished | Oct 09 10:14:00 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171500948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3171500948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.1718481537 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 309050289263 ps |
| CPU time | 172.64 seconds |
| Started | Oct 09 10:10:36 PM UTC 24 |
| Finished | Oct 09 10:13:31 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718481537 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1718481537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.394617474 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 24707461254 ps |
| CPU time | 57.68 seconds |
| Started | Oct 09 10:10:56 PM UTC 24 |
| Finished | Oct 09 10:11:56 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394617474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.394617474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.1656103560 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 124820388683 ps |
| CPU time | 133.27 seconds |
| Started | Oct 09 10:11:03 PM UTC 24 |
| Finished | Oct 09 10:13:19 PM UTC 24 |
| Peak memory | 201088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656103560 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.1656103560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.3906358104 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 363143796414 ps |
| CPU time | 170.58 seconds |
| Started | Oct 09 10:11:15 PM UTC 24 |
| Finished | Oct 09 10:14:08 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906358104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3906358104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.85934234 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 170883773348 ps |
| CPU time | 397.04 seconds |
| Started | Oct 09 10:11:37 PM UTC 24 |
| Finished | Oct 09 10:18:19 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85934234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.85934234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.4149807043 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12139955692 ps |
| CPU time | 11.96 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:01 PM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149807043 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.4149807043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2760756901 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 140464992461 ps |
| CPU time | 56.64 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:46 PM UTC 24 |
| Peak memory | 201044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760756901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2760756901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.408675390 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 135839325800 ps |
| CPU time | 94.97 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:58:25 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408675390 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.408675390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.1500043723 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3806864623 ps |
| CPU time | 44.3 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:34 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500043723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1500043723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.144086450 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 62524972 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:56:50 PM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144086450 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.144086450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3403336773 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 620312798921 ps |
| CPU time | 311.58 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:02:04 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403336773 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3403336773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.3372646168 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2767237024 ps |
| CPU time | 41.99 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:32 PM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3372646168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.3372646168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.1018029655 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 222616090521 ps |
| CPU time | 453.38 seconds |
| Started | Oct 09 10:12:36 PM UTC 24 |
| Finished | Oct 09 10:20:15 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018029655 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.1018029655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.2934352779 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 165438166855 ps |
| CPU time | 334.12 seconds |
| Started | Oct 09 10:11:56 PM UTC 24 |
| Finished | Oct 09 10:17:35 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934352779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2934352779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.3913263699 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 49233813069 ps |
| CPU time | 38.13 seconds |
| Started | Oct 09 10:11:55 PM UTC 24 |
| Finished | Oct 09 10:12:35 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913263699 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3913263699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.4112302565 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 8451221980 ps |
| CPU time | 29.34 seconds |
| Started | Oct 09 10:12:36 PM UTC 24 |
| Finished | Oct 09 10:13:06 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112302565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4112302565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.2132107695 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 77370666007 ps |
| CPU time | 129.8 seconds |
| Started | Oct 09 10:13:07 PM UTC 24 |
| Finished | Oct 09 10:15:19 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132107695 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.2132107695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.2738710051 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 108658188788 ps |
| CPU time | 231.68 seconds |
| Started | Oct 09 10:12:54 PM UTC 24 |
| Finished | Oct 09 10:16:49 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738710051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2738710051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.1397495345 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 76396653337 ps |
| CPU time | 159.75 seconds |
| Started | Oct 09 10:12:44 PM UTC 24 |
| Finished | Oct 09 10:15:26 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397495345 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1397495345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.3343990194 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 118560468370 ps |
| CPU time | 72.81 seconds |
| Started | Oct 09 10:13:13 PM UTC 24 |
| Finished | Oct 09 10:14:28 PM UTC 24 |
| Peak memory | 201008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343990194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3343990194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2966888459 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 489036580969 ps |
| CPU time | 122.57 seconds |
| Started | Oct 09 10:13:29 PM UTC 24 |
| Finished | Oct 09 10:15:34 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966888459 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2966888459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.1299173697 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 83949477704 ps |
| CPU time | 67.93 seconds |
| Started | Oct 09 10:13:51 PM UTC 24 |
| Finished | Oct 09 10:15:00 PM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299173697 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1299173697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.1808671746 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 69560792689 ps |
| CPU time | 225.24 seconds |
| Started | Oct 09 10:13:50 PM UTC 24 |
| Finished | Oct 09 10:17:38 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808671746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1808671746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.3361140504 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 455713682359 ps |
| CPU time | 165.29 seconds |
| Started | Oct 09 10:13:32 PM UTC 24 |
| Finished | Oct 09 10:16:21 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361140504 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3361140504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.94843152 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 700495741640 ps |
| CPU time | 351.33 seconds |
| Started | Oct 09 10:13:57 PM UTC 24 |
| Finished | Oct 09 10:19:53 PM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94843152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.94843152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3783746879 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 515418547709 ps |
| CPU time | 996.48 seconds |
| Started | Oct 09 10:13:57 PM UTC 24 |
| Finished | Oct 09 10:30:43 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783746879 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.3783746879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.1769455345 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 213678157214 ps |
| CPU time | 350.52 seconds |
| Started | Oct 09 10:14:11 PM UTC 24 |
| Finished | Oct 09 10:20:06 PM UTC 24 |
| Peak memory | 201264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769455345 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.1769455345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.1705151491 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 46142158145 ps |
| CPU time | 100.49 seconds |
| Started | Oct 09 10:14:09 PM UTC 24 |
| Finished | Oct 09 10:15:52 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705151491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1705151491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.364201038 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 209756564403 ps |
| CPU time | 81.49 seconds |
| Started | Oct 09 10:14:01 PM UTC 24 |
| Finished | Oct 09 10:15:24 PM UTC 24 |
| Peak memory | 200928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364201038 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.364201038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2898440832 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 194621168660 ps |
| CPU time | 196.37 seconds |
| Started | Oct 09 10:14:18 PM UTC 24 |
| Finished | Oct 09 10:17:38 PM UTC 24 |
| Peak memory | 201288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898440832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2898440832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.340510573 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 64577476 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:14:23 PM UTC 24 |
| Finished | Oct 09 10:14:26 PM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340510573 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.340510573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3875808249 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 22541137417 ps |
| CPU time | 57.52 seconds |
| Started | Oct 09 10:14:31 PM UTC 24 |
| Finished | Oct 09 10:15:30 PM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875808249 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3875808249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.1764540404 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 302428756882 ps |
| CPU time | 244.37 seconds |
| Started | Oct 09 10:14:29 PM UTC 24 |
| Finished | Oct 09 10:18:36 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764540404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1764540404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.3611084031 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 396323189180 ps |
| CPU time | 326.84 seconds |
| Started | Oct 09 10:14:27 PM UTC 24 |
| Finished | Oct 09 10:19:58 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611084031 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3611084031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2662578588 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 74345820298 ps |
| CPU time | 61.27 seconds |
| Started | Oct 09 10:14:42 PM UTC 24 |
| Finished | Oct 09 10:15:45 PM UTC 24 |
| Peak memory | 201348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662578588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2662578588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.3706403443 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 65542708913 ps |
| CPU time | 105.13 seconds |
| Started | Oct 09 10:15:01 PM UTC 24 |
| Finished | Oct 09 10:16:48 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706403443 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.3706403443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all_with_rand_reset.4032740608 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6888606241 ps |
| CPU time | 33.48 seconds |
| Started | Oct 09 10:15:01 PM UTC 24 |
| Finished | Oct 09 10:15:36 PM UTC 24 |
| Peak memory | 205204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4032740608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.rv_timer_stress_all_with_rand_reset.4032740608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2797440515 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 135074355228 ps |
| CPU time | 110.77 seconds |
| Started | Oct 09 10:15:25 PM UTC 24 |
| Finished | Oct 09 10:17:18 PM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797440515 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2797440515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1606183851 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 135093176087 ps |
| CPU time | 221.92 seconds |
| Started | Oct 09 10:15:20 PM UTC 24 |
| Finished | Oct 09 10:19:05 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606183851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1606183851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.3083843913 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 103276465541 ps |
| CPU time | 219 seconds |
| Started | Oct 09 10:15:06 PM UTC 24 |
| Finished | Oct 09 10:18:49 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083843913 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3083843913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all_with_rand_reset.3146531963 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6367748665 ps |
| CPU time | 16.93 seconds |
| Started | Oct 09 10:15:31 PM UTC 24 |
| Finished | Oct 09 10:15:49 PM UTC 24 |
| Peak memory | 205556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3146531963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.rv_timer_stress_all_with_rand_reset.3146531963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.3155420416 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 25687738617 ps |
| CPU time | 26.93 seconds |
| Started | Oct 09 10:15:46 PM UTC 24 |
| Finished | Oct 09 10:16:14 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155420416 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.3155420416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.4039199741 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 51752305897 ps |
| CPU time | 123.48 seconds |
| Started | Oct 09 10:15:46 PM UTC 24 |
| Finished | Oct 09 10:17:52 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039199741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4039199741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3449098679 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 399717140859 ps |
| CPU time | 566.83 seconds |
| Started | Oct 09 10:15:37 PM UTC 24 |
| Finished | Oct 09 10:25:11 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449098679 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3449098679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.299898174 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 128643571026 ps |
| CPU time | 45.58 seconds |
| Started | Oct 09 10:15:50 PM UTC 24 |
| Finished | Oct 09 10:16:37 PM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299898174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.299898174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.3016101465 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 398862409582 ps |
| CPU time | 658.87 seconds |
| Started | Oct 09 10:16:22 PM UTC 24 |
| Finished | Oct 09 10:27:29 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016101465 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3016101465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2065164358 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 22573117028 ps |
| CPU time | 30.49 seconds |
| Started | Oct 09 10:16:16 PM UTC 24 |
| Finished | Oct 09 10:16:48 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065164358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2065164358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.941422067 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 47217305076 ps |
| CPU time | 634.62 seconds |
| Started | Oct 09 10:16:15 PM UTC 24 |
| Finished | Oct 09 10:26:58 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941422067 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.941422067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.605390967 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 49984828401 ps |
| CPU time | 88.9 seconds |
| Started | Oct 09 10:16:38 PM UTC 24 |
| Finished | Oct 09 10:18:08 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605390967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.605390967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1391622603 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 379693514148 ps |
| CPU time | 211.96 seconds |
| Started | Oct 09 10:16:46 PM UTC 24 |
| Finished | Oct 09 10:20:21 PM UTC 24 |
| Peak memory | 201280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391622603 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1391622603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1158234779 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 140394113128 ps |
| CPU time | 122.07 seconds |
| Started | Oct 09 10:16:50 PM UTC 24 |
| Finished | Oct 09 10:18:55 PM UTC 24 |
| Peak memory | 201000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158234779 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1158234779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2421395246 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 93930917528 ps |
| CPU time | 427.14 seconds |
| Started | Oct 09 10:16:49 PM UTC 24 |
| Finished | Oct 09 10:24:02 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421395246 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2421395246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3025111711 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 42862323255 ps |
| CPU time | 135.27 seconds |
| Started | Oct 09 10:16:53 PM UTC 24 |
| Finished | Oct 09 10:19:11 PM UTC 24 |
| Peak memory | 201080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025111711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3025111711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.116542743 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 501902136913 ps |
| CPU time | 367.61 seconds |
| Started | Oct 09 10:17:05 PM UTC 24 |
| Finished | Oct 09 10:23:18 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116542743 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.116542743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3047680630 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1338623965346 ps |
| CPU time | 903.7 seconds |
| Started | Oct 09 10:17:27 PM UTC 24 |
| Finished | Oct 09 10:32:41 PM UTC 24 |
| Peak memory | 201328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047680630 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3047680630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.4118880651 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 632249695341 ps |
| CPU time | 251.72 seconds |
| Started | Oct 09 10:17:20 PM UTC 24 |
| Finished | Oct 09 10:21:35 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118880651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4118880651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.2527590027 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 12628772450 ps |
| CPU time | 33.75 seconds |
| Started | Oct 09 10:17:12 PM UTC 24 |
| Finished | Oct 09 10:17:47 PM UTC 24 |
| Peak memory | 201276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527590027 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2527590027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2250280656 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 355665836860 ps |
| CPU time | 127.8 seconds |
| Started | Oct 09 10:17:36 PM UTC 24 |
| Finished | Oct 09 10:19:46 PM UTC 24 |
| Peak memory | 201160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250280656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2250280656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.770014102 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 174215138000 ps |
| CPU time | 182.14 seconds |
| Started | Oct 09 10:17:39 PM UTC 24 |
| Finished | Oct 09 10:20:44 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770014102 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.770014102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.3974139728 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 816832566049 ps |
| CPU time | 637.23 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 10:07:33 PM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974139728 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.3974139728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.4201103711 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 33818602013 ps |
| CPU time | 16.28 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:06 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201103711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4201103711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.3846787317 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 42886247369 ps |
| CPU time | 89.62 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:58:20 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846787317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3846787317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.2326245263 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11883331414 ps |
| CPU time | 41.34 seconds |
| Started | Oct 09 10:17:47 PM UTC 24 |
| Finished | Oct 09 10:18:30 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326245263 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2326245263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.4000953326 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 523132609732 ps |
| CPU time | 293.23 seconds |
| Started | Oct 09 10:17:50 PM UTC 24 |
| Finished | Oct 09 10:22:47 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000953326 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4000953326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.3250085313 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 365523255402 ps |
| CPU time | 132.06 seconds |
| Started | Oct 09 10:17:52 PM UTC 24 |
| Finished | Oct 09 10:20:07 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250085313 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3250085313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.569569764 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 642485346953 ps |
| CPU time | 406.11 seconds |
| Started | Oct 09 10:18:09 PM UTC 24 |
| Finished | Oct 09 10:25:01 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569569764 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.569569764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.850103774 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 10063423986 ps |
| CPU time | 48.34 seconds |
| Started | Oct 09 10:18:21 PM UTC 24 |
| Finished | Oct 09 10:19:11 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850103774 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.850103774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.3143021422 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 54378096308 ps |
| CPU time | 147.59 seconds |
| Started | Oct 09 10:18:31 PM UTC 24 |
| Finished | Oct 09 10:21:01 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143021422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3143021422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.270426634 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 459926707610 ps |
| CPU time | 686.03 seconds |
| Started | Oct 09 10:18:38 PM UTC 24 |
| Finished | Oct 09 10:30:12 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270426634 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.270426634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.626426504 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 169087530945 ps |
| CPU time | 369.01 seconds |
| Started | Oct 09 10:18:49 PM UTC 24 |
| Finished | Oct 09 10:25:03 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626426504 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.626426504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.3449131121 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 378773303423 ps |
| CPU time | 437.74 seconds |
| Started | Oct 09 10:18:50 PM UTC 24 |
| Finished | Oct 09 10:26:14 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449131121 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3449131121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.1385010536 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 16430278952 ps |
| CPU time | 27.84 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:57:18 PM UTC 24 |
| Peak memory | 200184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385010536 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1385010536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.2664708590 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 643651077005 ps |
| CPU time | 152.29 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:59:24 PM UTC 24 |
| Peak memory | 200308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664708590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2664708590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.855401702 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 114117439050 ps |
| CPU time | 102.69 seconds |
| Started | Oct 09 09:56:48 PM UTC 24 |
| Finished | Oct 09 09:58:34 PM UTC 24 |
| Peak memory | 201084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855401702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.855401702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.4231436134 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 400472697617 ps |
| CPU time | 643.2 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:07:40 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231436134 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.4231436134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.4021054998 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 205789823419 ps |
| CPU time | 190.61 seconds |
| Started | Oct 09 10:18:50 PM UTC 24 |
| Finished | Oct 09 10:22:04 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021054998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4021054998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.139964824 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 48578919354 ps |
| CPU time | 158.8 seconds |
| Started | Oct 09 10:18:55 PM UTC 24 |
| Finished | Oct 09 10:21:37 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139964824 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.139964824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2468623240 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 47908003315 ps |
| CPU time | 1729.26 seconds |
| Started | Oct 09 10:19:06 PM UTC 24 |
| Finished | Oct 09 10:48:14 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468623240 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2468623240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.2691489689 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 6339362408 ps |
| CPU time | 84.42 seconds |
| Started | Oct 09 10:19:11 PM UTC 24 |
| Finished | Oct 09 10:20:38 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691489689 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2691489689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.256181352 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 81669263233 ps |
| CPU time | 72.33 seconds |
| Started | Oct 09 10:19:11 PM UTC 24 |
| Finished | Oct 09 10:20:26 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256181352 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.256181352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.115228937 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 845507169759 ps |
| CPU time | 474.15 seconds |
| Started | Oct 09 10:19:23 PM UTC 24 |
| Finished | Oct 09 10:27:24 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115228937 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.115228937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.3439271660 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 21851098176 ps |
| CPU time | 56.41 seconds |
| Started | Oct 09 10:19:47 PM UTC 24 |
| Finished | Oct 09 10:20:45 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439271660 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3439271660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.3678673058 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 429870053150 ps |
| CPU time | 2350.98 seconds |
| Started | Oct 09 10:19:48 PM UTC 24 |
| Finished | Oct 09 10:59:25 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678673058 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3678673058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.747521174 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 56734267128 ps |
| CPU time | 170.09 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:59:42 PM UTC 24 |
| Peak memory | 200992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747521174 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.747521174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.2404015670 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 79879535032 ps |
| CPU time | 135.07 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:59:07 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404015670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2404015670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.3546118058 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 56037026976 ps |
| CPU time | 90.62 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:58:22 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546118058 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3546118058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.1401344715 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 92498206947 ps |
| CPU time | 42.42 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:57:33 PM UTC 24 |
| Peak memory | 201048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401344715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1401344715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.2054668499 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 179662077921 ps |
| CPU time | 581.39 seconds |
| Started | Oct 09 10:20:08 PM UTC 24 |
| Finished | Oct 09 10:29:57 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054668499 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2054668499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2347482868 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1284257964644 ps |
| CPU time | 1070.39 seconds |
| Started | Oct 09 10:20:15 PM UTC 24 |
| Finished | Oct 09 10:38:20 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347482868 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2347482868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.2480572135 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 128613473341 ps |
| CPU time | 954.98 seconds |
| Started | Oct 09 10:20:16 PM UTC 24 |
| Finished | Oct 09 10:36:22 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480572135 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2480572135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.3536636194 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 46338507411 ps |
| CPU time | 63.53 seconds |
| Started | Oct 09 10:20:22 PM UTC 24 |
| Finished | Oct 09 10:21:28 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536636194 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3536636194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.64232176 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 603085308037 ps |
| CPU time | 101.03 seconds |
| Started | Oct 09 10:20:26 PM UTC 24 |
| Finished | Oct 09 10:22:10 PM UTC 24 |
| Peak memory | 201344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64232176 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.64232176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1266519188 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1282404770445 ps |
| CPU time | 1568.57 seconds |
| Started | Oct 09 10:20:39 PM UTC 24 |
| Finished | Oct 09 10:47:05 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266519188 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1266519188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.1662024009 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 423733258381 ps |
| CPU time | 1152 seconds |
| Started | Oct 09 10:20:45 PM UTC 24 |
| Finished | Oct 09 10:40:10 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662024009 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1662024009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.1420708257 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 25144832023 ps |
| CPU time | 81.54 seconds |
| Started | Oct 09 10:20:46 PM UTC 24 |
| Finished | Oct 09 10:22:09 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420708257 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1420708257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1772372490 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 103050479993 ps |
| CPU time | 207.04 seconds |
| Started | Oct 09 10:20:53 PM UTC 24 |
| Finished | Oct 09 10:24:23 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772372490 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1772372490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.3488614717 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 458906935198 ps |
| CPU time | 838.98 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:10:57 PM UTC 24 |
| Peak memory | 201232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488614717 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3488614717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.3666556261 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 210785964856 ps |
| CPU time | 158.27 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:59:30 PM UTC 24 |
| Peak memory | 200912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666556261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3666556261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3186712110 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 70637982082 ps |
| CPU time | 63.18 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:57:54 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186712110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3186712110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.1427433882 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 390167306561 ps |
| CPU time | 741.31 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:09:20 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427433882 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.1427433882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.3167305719 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 22474202801 ps |
| CPU time | 500.31 seconds |
| Started | Oct 09 10:21:02 PM UTC 24 |
| Finished | Oct 09 10:29:29 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167305719 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3167305719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.2473769725 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 93357403007 ps |
| CPU time | 157.25 seconds |
| Started | Oct 09 10:21:15 PM UTC 24 |
| Finished | Oct 09 10:23:55 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473769725 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2473769725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.3267169366 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 905554548309 ps |
| CPU time | 2066.22 seconds |
| Started | Oct 09 10:21:35 PM UTC 24 |
| Finished | Oct 09 10:56:26 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267169366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3267169366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.4130038678 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 101240253267 ps |
| CPU time | 83.87 seconds |
| Started | Oct 09 10:21:37 PM UTC 24 |
| Finished | Oct 09 10:23:03 PM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130038678 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4130038678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.2581619501 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 71168321579 ps |
| CPU time | 58.07 seconds |
| Started | Oct 09 10:21:43 PM UTC 24 |
| Finished | Oct 09 10:22:43 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581619501 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2581619501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.3410141123 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 616962310209 ps |
| CPU time | 1591.63 seconds |
| Started | Oct 09 10:22:05 PM UTC 24 |
| Finished | Oct 09 10:48:53 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410141123 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3410141123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.1152607093 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 345600274027 ps |
| CPU time | 583.02 seconds |
| Started | Oct 09 10:22:10 PM UTC 24 |
| Finished | Oct 09 10:32:00 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152607093 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1152607093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.1683189649 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 304282131456 ps |
| CPU time | 243.28 seconds |
| Started | Oct 09 10:22:11 PM UTC 24 |
| Finished | Oct 09 10:26:18 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683189649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1683189649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.897269315 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 118083714866 ps |
| CPU time | 89.7 seconds |
| Started | Oct 09 10:22:11 PM UTC 24 |
| Finished | Oct 09 10:23:42 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897269315 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.897269315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.603916237 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 24782835977 ps |
| CPU time | 61.05 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:57:52 PM UTC 24 |
| Peak memory | 201068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603916237 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.603916237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.2571665762 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 246778853036 ps |
| CPU time | 61.76 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:57:53 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571665762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2571665762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.1125508122 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 112667909263 ps |
| CPU time | 1579.74 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 10:23:27 PM UTC 24 |
| Peak memory | 201076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125508122 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1125508122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.2338182430 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 57076327 ps |
| CPU time | 2.5 seconds |
| Started | Oct 09 09:56:49 PM UTC 24 |
| Finished | Oct 09 09:56:53 PM UTC 24 |
| Peak memory | 200840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338182430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2338182430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.604956902 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 677654128072 ps |
| CPU time | 304.02 seconds |
| Started | Oct 09 10:22:11 PM UTC 24 |
| Finished | Oct 09 10:27:19 PM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604956902 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.604956902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.201442772 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 360462785687 ps |
| CPU time | 149.54 seconds |
| Started | Oct 09 10:22:35 PM UTC 24 |
| Finished | Oct 09 10:25:07 PM UTC 24 |
| Peak memory | 201340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201442772 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.201442772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.904303434 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 298568200085 ps |
| CPU time | 327.95 seconds |
| Started | Oct 09 10:22:48 PM UTC 24 |
| Finished | Oct 09 10:28:21 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904303434 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.904303434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.1196118786 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 733897164352 ps |
| CPU time | 3445.16 seconds |
| Started | Oct 09 10:23:01 PM UTC 24 |
| Finished | Oct 09 11:21:02 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196118786 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1196118786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1435388903 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 136950039323 ps |
| CPU time | 101.18 seconds |
| Started | Oct 09 10:23:04 PM UTC 24 |
| Finished | Oct 09 10:24:48 PM UTC 24 |
| Peak memory | 200924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435388903 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1435388903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.4238192892 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 38201909699 ps |
| CPU time | 118.95 seconds |
| Started | Oct 09 10:23:26 PM UTC 24 |
| Finished | Oct 09 10:25:27 PM UTC 24 |
| Peak memory | 201072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238192892 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4238192892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/rv_timer-sim-vcs/97.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |