| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.63 | 99.33 | 99.04 | 100.00 | 100.00 | 100.00 | 99.43 |
| T504 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2122853933 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 71194435 ps | ||
| T505 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3836995885 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 118102969 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1498767197 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 453109438 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.989412699 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 139455601 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2848247476 | Oct 12 05:36:59 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 52731684 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.641224027 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 182729646 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1751829142 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:02 PM UTC 24 | 335022636 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2671290868 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 264922854 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3265903089 | Oct 12 05:36:59 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 463418008 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3688920130 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 140656303 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1872247244 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 42931097 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3678549506 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 99955489 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3649704974 | Oct 12 05:37:00 PM UTC 24 | Oct 12 05:37:03 PM UTC 24 | 144622310 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1934779085 | Oct 12 05:37:03 PM UTC 24 | Oct 12 05:37:05 PM UTC 24 | 22032834 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.500727990 | Oct 12 05:37:03 PM UTC 24 | Oct 12 05:37:05 PM UTC 24 | 63116544 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2938740464 | Oct 12 05:37:03 PM UTC 24 | Oct 12 05:37:05 PM UTC 24 | 51214183 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2355574052 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 38767424 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1597813219 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:06 PM UTC 24 | 25437896 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.935626025 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 34456036 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1131155016 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:06 PM UTC 24 | 58639243 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1102080048 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:06 PM UTC 24 | 35606166 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1529087564 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 42369957 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3346331534 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 14462671 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3478811645 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 216574054 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1148097385 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 103294425 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1775781686 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 14606576 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1461705427 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 66252784 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1506802969 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 46469318 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2296000896 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 31222505 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.4259140071 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 18887201 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.282058113 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 38964280 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2745687129 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 17523833 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.151899563 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 156601091 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2885669875 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 13951056 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2958736961 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 93910676 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.327341649 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 142048539 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1348260895 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 15880339 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2343949200 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 17188474 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2218055763 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 34923318 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3360275360 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 234828896 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1151386207 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 245388599 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3892984257 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 119046846 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3639462163 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 59254610 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.548948179 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 49984165 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.1800120220 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 37240606 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1584349421 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 1643562641 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.134206413 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 120571828 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3804493842 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:07 PM UTC 24 | 34872274 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.60685538 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:08 PM UTC 24 | 75651171 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1576143130 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:08 PM UTC 24 | 303857958 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.813875724 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:08 PM UTC 24 | 185755486 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4108471680 | Oct 12 05:37:05 PM UTC 24 | Oct 12 05:37:08 PM UTC 24 | 47010178 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.638585861 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 44244756 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1500902211 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 23689398 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.598860817 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 12299858 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3444912960 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 14591558 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.928837860 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 14920307 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.168287799 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 90978262 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2487485607 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 40806932 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.411144145 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 41109946 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1240662835 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 52041465 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2775768881 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 15251736 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1820488407 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 18075252 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4010680666 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 15970027 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1378035082 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 15430249 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3735288082 | Oct 12 05:37:09 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 32099311 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2300458413 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 13930416 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.4269533271 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 29280862 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3961843812 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 20592918 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1586901713 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 23199080 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.3505952339 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:11 PM UTC 24 | 138834980 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2032478376 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 24702099 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1446249198 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 48778349 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2728662257 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 188972477 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2155016366 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 17612176 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.1394473760 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 35850809 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4286500433 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 36480823 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.4141602940 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 19260946 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1896331496 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 40151992 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.613132449 | Oct 12 05:37:10 PM UTC 24 | Oct 12 05:37:12 PM UTC 24 | 46809077 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.1432749732 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5373091362 ps |
| CPU time | 4.37 seconds |
| Started | Oct 12 03:14:40 PM UTC 24 |
| Finished | Oct 12 03:14:46 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432749732 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.1432749732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all_with_rand_reset.583263846 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6333852803 ps |
| CPU time | 29.12 seconds |
| Started | Oct 12 03:14:43 PM UTC 24 |
| Finished | Oct 12 03:15:13 PM UTC 24 |
| Peak memory | 202840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=583263846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.583263846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3105868122 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 289411269115 ps |
| CPU time | 283.33 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:18:43 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105868122 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3105868122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.1509459595 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1491146720553 ps |
| CPU time | 1014.38 seconds |
| Started | Oct 12 03:36:03 PM UTC 24 |
| Finished | Oct 12 03:53:09 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509459595 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.1509459595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4009037984 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 158330934 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009037984 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.4009037984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.3602322366 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 990006075953 ps |
| CPU time | 1425.09 seconds |
| Started | Oct 12 03:15:06 PM UTC 24 |
| Finished | Oct 12 03:39:06 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602322366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.3602322366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.3443549309 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 719998270357 ps |
| CPU time | 1716.45 seconds |
| Started | Oct 12 03:38:39 PM UTC 24 |
| Finished | Oct 12 04:07:33 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443549309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.3443549309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2627047318 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 475858366566 ps |
| CPU time | 1048.54 seconds |
| Started | Oct 12 03:16:05 PM UTC 24 |
| Finished | Oct 12 03:33:45 PM UTC 24 |
| Peak memory | 200220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627047318 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2627047318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.297849763 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14976091 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:19 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297849763 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.297849763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.2593025543 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7942119387366 ps |
| CPU time | 1908.53 seconds |
| Started | Oct 12 03:19:56 PM UTC 24 |
| Finished | Oct 12 03:52:03 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593025543 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.2593025543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.441976923 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2074259543448 ps |
| CPU time | 4074.76 seconds |
| Started | Oct 12 03:30:12 PM UTC 24 |
| Finished | Oct 12 04:38:49 PM UTC 24 |
| Peak memory | 200496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441976923 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.441976923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.2797162123 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 791556221531 ps |
| CPU time | 1088.78 seconds |
| Started | Oct 12 03:45:42 PM UTC 24 |
| Finished | Oct 12 04:04:02 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797162123 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.2797162123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.2768471900 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 154415715160 ps |
| CPU time | 238.38 seconds |
| Started | Oct 12 03:13:59 PM UTC 24 |
| Finished | Oct 12 03:18:00 PM UTC 24 |
| Peak memory | 196728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768471900 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2768471900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.3506016843 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3789172112601 ps |
| CPU time | 1590.46 seconds |
| Started | Oct 12 03:41:17 PM UTC 24 |
| Finished | Oct 12 04:08:04 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506016843 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.3506016843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.1451643407 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 551740503851 ps |
| CPU time | 3179.77 seconds |
| Started | Oct 12 03:20:52 PM UTC 24 |
| Finished | Oct 12 04:14:23 PM UTC 24 |
| Peak memory | 200380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451643407 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.1451643407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3402434538 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 387344881002 ps |
| CPU time | 1065.06 seconds |
| Started | Oct 12 03:17:00 PM UTC 24 |
| Finished | Oct 12 03:34:56 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402434538 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3402434538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.4048119170 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 240214271 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:13:58 PM UTC 24 |
| Peak memory | 229100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048119170 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.4048119170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.4143012888 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2316550233050 ps |
| CPU time | 4342.49 seconds |
| Started | Oct 12 03:39:56 PM UTC 24 |
| Finished | Oct 12 04:53:03 PM UTC 24 |
| Peak memory | 200368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143012888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.4143012888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.773559611 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 729017654222 ps |
| CPU time | 877.68 seconds |
| Started | Oct 12 03:47:45 PM UTC 24 |
| Finished | Oct 12 04:02:32 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773559611 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.773559611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.2752225302 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 553127274536 ps |
| CPU time | 774.61 seconds |
| Started | Oct 12 03:14:43 PM UTC 24 |
| Finished | Oct 12 03:27:46 PM UTC 24 |
| Peak memory | 200412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752225302 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.2752225302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.998299053 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3277882880199 ps |
| CPU time | 1264.09 seconds |
| Started | Oct 12 03:24:51 PM UTC 24 |
| Finished | Oct 12 03:46:07 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998299053 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.998299053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.634002706 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1448898825111 ps |
| CPU time | 1138.09 seconds |
| Started | Oct 12 03:44:15 PM UTC 24 |
| Finished | Oct 12 04:03:24 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634002706 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.634002706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1899652494 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2173924507811 ps |
| CPU time | 2746.17 seconds |
| Started | Oct 12 03:42:28 PM UTC 24 |
| Finished | Oct 12 04:28:42 PM UTC 24 |
| Peak memory | 200452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899652494 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1899652494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.1404387895 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1400847046017 ps |
| CPU time | 828.04 seconds |
| Started | Oct 12 03:21:49 PM UTC 24 |
| Finished | Oct 12 03:35:47 PM UTC 24 |
| Peak memory | 200444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404387895 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.1404387895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.1741872500 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 31975003470 ps |
| CPU time | 82.8 seconds |
| Started | Oct 12 03:39:07 PM UTC 24 |
| Finished | Oct 12 03:40:32 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741872500 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1741872500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1050458807 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 625984371199 ps |
| CPU time | 1250.69 seconds |
| Started | Oct 12 03:54:00 PM UTC 24 |
| Finished | Oct 12 04:15:03 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050458807 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1050458807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.2456178057 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 367931449254 ps |
| CPU time | 1127.01 seconds |
| Started | Oct 12 03:35:16 PM UTC 24 |
| Finished | Oct 12 03:54:16 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456178057 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.2456178057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.3493572308 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 146578329320 ps |
| CPU time | 634.05 seconds |
| Started | Oct 12 04:13:24 PM UTC 24 |
| Finished | Oct 12 04:24:06 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493572308 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3493572308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.978306813 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 119901910520 ps |
| CPU time | 547.32 seconds |
| Started | Oct 12 04:25:36 PM UTC 24 |
| Finished | Oct 12 04:34:49 PM UTC 24 |
| Peak memory | 200616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978306813 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.978306813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.2484830716 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 734429375195 ps |
| CPU time | 1654.5 seconds |
| Started | Oct 12 03:39:43 PM UTC 24 |
| Finished | Oct 12 04:07:35 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484830716 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.2484830716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3876454386 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3744832289236 ps |
| CPU time | 1271.44 seconds |
| Started | Oct 12 03:14:30 PM UTC 24 |
| Finished | Oct 12 03:35:55 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876454386 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3876454386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.661933900 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 42146604303 ps |
| CPU time | 33.2 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:14:30 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661933900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.661933900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1343383386 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 337860953148 ps |
| CPU time | 593.74 seconds |
| Started | Oct 12 04:09:44 PM UTC 24 |
| Finished | Oct 12 04:19:46 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343383386 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1343383386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.2127167244 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1710764473974 ps |
| CPU time | 638.87 seconds |
| Started | Oct 12 04:14:47 PM UTC 24 |
| Finished | Oct 12 04:25:34 PM UTC 24 |
| Peak memory | 200576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127167244 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2127167244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.3011691829 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 512275585099 ps |
| CPU time | 764.75 seconds |
| Started | Oct 12 03:23:08 PM UTC 24 |
| Finished | Oct 12 03:36:02 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011691829 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.3011691829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.2431639851 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 358652719677 ps |
| CPU time | 433.02 seconds |
| Started | Oct 12 04:33:44 PM UTC 24 |
| Finished | Oct 12 04:41:02 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431639851 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2431639851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1440168195 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 114756506804 ps |
| CPU time | 103.54 seconds |
| Started | Oct 12 03:39:43 PM UTC 24 |
| Finished | Oct 12 03:41:29 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440168195 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1440168195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1496479134 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 587257758147 ps |
| CPU time | 508.58 seconds |
| Started | Oct 12 04:19:45 PM UTC 24 |
| Finished | Oct 12 04:28:20 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496479134 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1496479134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.1240663278 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 614191110847 ps |
| CPU time | 456.8 seconds |
| Started | Oct 12 04:27:27 PM UTC 24 |
| Finished | Oct 12 04:35:09 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240663278 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1240663278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.1579425536 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 124566347909 ps |
| CPU time | 494.9 seconds |
| Started | Oct 12 04:28:14 PM UTC 24 |
| Finished | Oct 12 04:36:34 PM UTC 24 |
| Peak memory | 196808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579425536 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1579425536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.2577303729 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3406582962908 ps |
| CPU time | 3714.97 seconds |
| Started | Oct 12 03:27:08 PM UTC 24 |
| Finished | Oct 12 04:29:42 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577303729 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.2577303729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2229330337 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 341751013591 ps |
| CPU time | 526.11 seconds |
| Started | Oct 12 03:36:48 PM UTC 24 |
| Finished | Oct 12 03:45:40 PM UTC 24 |
| Peak memory | 198728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229330337 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2229330337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.420241935 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 576607227014 ps |
| CPU time | 327.22 seconds |
| Started | Oct 12 03:54:27 PM UTC 24 |
| Finished | Oct 12 03:59:58 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420241935 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.420241935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2343440404 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 84368393180 ps |
| CPU time | 200.99 seconds |
| Started | Oct 12 04:02:32 PM UTC 24 |
| Finished | Oct 12 04:05:57 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343440404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2343440404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.151899563 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 156601091 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151899563 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.151899563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.4019119486 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 77318517736 ps |
| CPU time | 689.04 seconds |
| Started | Oct 12 03:13:55 PM UTC 24 |
| Finished | Oct 12 03:25:32 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019119486 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4019119486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3920747756 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1156500212349 ps |
| CPU time | 626.46 seconds |
| Started | Oct 12 04:10:31 PM UTC 24 |
| Finished | Oct 12 04:21:05 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920747756 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3920747756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.1931194573 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 123680314368 ps |
| CPU time | 1985.16 seconds |
| Started | Oct 12 04:13:34 PM UTC 24 |
| Finished | Oct 12 04:47:01 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931194573 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1931194573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.87101878 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 198139633073 ps |
| CPU time | 694.67 seconds |
| Started | Oct 12 03:18:39 PM UTC 24 |
| Finished | Oct 12 03:30:21 PM UTC 24 |
| Peak memory | 198708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87101878 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.87101878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2889508920 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1684503645014 ps |
| CPU time | 1014.87 seconds |
| Started | Oct 12 03:40:02 PM UTC 24 |
| Finished | Oct 12 03:57:08 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889508920 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2889508920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.971630003 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 255855342024 ps |
| CPU time | 123.5 seconds |
| Started | Oct 12 03:41:51 PM UTC 24 |
| Finished | Oct 12 03:43:57 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971630003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.971630003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.269447424 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1046751571487 ps |
| CPU time | 1887.1 seconds |
| Started | Oct 12 03:54:27 PM UTC 24 |
| Finished | Oct 12 04:26:15 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269447424 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.269447424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1485657296 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 20656541 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485657296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.1485657296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.3169891790 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 21792449 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169891790 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3169891790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.793979792 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 501179009048 ps |
| CPU time | 307.45 seconds |
| Started | Oct 12 03:17:06 PM UTC 24 |
| Finished | Oct 12 03:22:17 PM UTC 24 |
| Peak memory | 196668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793979792 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.793979792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.157145993 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 545966769485 ps |
| CPU time | 336.6 seconds |
| Started | Oct 12 03:18:34 PM UTC 24 |
| Finished | Oct 12 03:24:15 PM UTC 24 |
| Peak memory | 196512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157145993 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.157145993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.2794823455 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 396977782527 ps |
| CPU time | 636.39 seconds |
| Started | Oct 12 03:18:59 PM UTC 24 |
| Finished | Oct 12 03:29:42 PM UTC 24 |
| Peak memory | 196964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794823455 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.2794823455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.3167617542 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 130528663696 ps |
| CPU time | 1832.69 seconds |
| Started | Oct 12 04:18:31 PM UTC 24 |
| Finished | Oct 12 04:49:22 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167617542 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3167617542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.361966204 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 236884023708 ps |
| CPU time | 574.3 seconds |
| Started | Oct 12 04:19:29 PM UTC 24 |
| Finished | Oct 12 04:29:11 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361966204 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.361966204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.3601831393 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6195707820894 ps |
| CPU time | 1975.61 seconds |
| Started | Oct 12 03:20:42 PM UTC 24 |
| Finished | Oct 12 03:53:58 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601831393 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3601831393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.440213571 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 69771129589 ps |
| CPU time | 541.71 seconds |
| Started | Oct 12 04:31:53 PM UTC 24 |
| Finished | Oct 12 04:41:02 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440213571 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.440213571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.3416599845 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 451115863170 ps |
| CPU time | 463.28 seconds |
| Started | Oct 12 03:13:59 PM UTC 24 |
| Finished | Oct 12 03:21:47 PM UTC 24 |
| Peak memory | 200364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416599845 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3416599845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.2962894950 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 48136366831 ps |
| CPU time | 152.02 seconds |
| Started | Oct 12 03:39:51 PM UTC 24 |
| Finished | Oct 12 03:42:26 PM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962894950 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.2962894950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2850985638 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 83892060666 ps |
| CPU time | 270.15 seconds |
| Started | Oct 12 03:59:29 PM UTC 24 |
| Finished | Oct 12 04:04:03 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850985638 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2850985638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3643794857 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 91781486809 ps |
| CPU time | 581.79 seconds |
| Started | Oct 12 04:03:35 PM UTC 24 |
| Finished | Oct 12 04:13:24 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643794857 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3643794857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.4073529026 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 580246888290 ps |
| CPU time | 877.83 seconds |
| Started | Oct 12 04:05:24 PM UTC 24 |
| Finished | Oct 12 04:20:12 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073529026 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4073529026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.2083008186 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 135455298067 ps |
| CPU time | 108.2 seconds |
| Started | Oct 12 04:11:03 PM UTC 24 |
| Finished | Oct 12 04:12:54 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083008186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2083008186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.3913975605 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 149137115654 ps |
| CPU time | 369.82 seconds |
| Started | Oct 12 04:14:10 PM UTC 24 |
| Finished | Oct 12 04:20:25 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913975605 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3913975605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.1233029599 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4626046601 ps |
| CPU time | 19.05 seconds |
| Started | Oct 12 04:14:25 PM UTC 24 |
| Finished | Oct 12 04:14:45 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233029599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1233029599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3751609871 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 498372137906 ps |
| CPU time | 581.4 seconds |
| Started | Oct 12 04:14:25 PM UTC 24 |
| Finished | Oct 12 04:24:13 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751609871 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3751609871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2007815373 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 137904082580 ps |
| CPU time | 236.13 seconds |
| Started | Oct 12 04:15:05 PM UTC 24 |
| Finished | Oct 12 04:19:04 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007815373 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2007815373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.1064317883 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 132774508853 ps |
| CPU time | 560.83 seconds |
| Started | Oct 12 04:15:13 PM UTC 24 |
| Finished | Oct 12 04:24:41 PM UTC 24 |
| Peak memory | 196732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064317883 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1064317883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.4053456844 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 138996640863 ps |
| CPU time | 527.89 seconds |
| Started | Oct 12 04:17:14 PM UTC 24 |
| Finished | Oct 12 04:26:09 PM UTC 24 |
| Peak memory | 198784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053456844 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4053456844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.790721328 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 464563103406 ps |
| CPU time | 534.21 seconds |
| Started | Oct 12 04:19:05 PM UTC 24 |
| Finished | Oct 12 04:28:06 PM UTC 24 |
| Peak memory | 200696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790721328 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.790721328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2027785369 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 137468490743 ps |
| CPU time | 917.43 seconds |
| Started | Oct 12 04:20:24 PM UTC 24 |
| Finished | Oct 12 04:35:52 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027785369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2027785369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2108271049 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 158198020362 ps |
| CPU time | 713.67 seconds |
| Started | Oct 12 04:21:06 PM UTC 24 |
| Finished | Oct 12 04:33:08 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108271049 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2108271049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.101045808 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 284089723299 ps |
| CPU time | 482.53 seconds |
| Started | Oct 12 04:22:13 PM UTC 24 |
| Finished | Oct 12 04:30:21 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101045808 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.101045808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.2688287993 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 586942138368 ps |
| CPU time | 2035.62 seconds |
| Started | Oct 12 03:20:08 PM UTC 24 |
| Finished | Oct 12 03:54:25 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688287993 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2688287993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.3292355826 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 49605283577 ps |
| CPU time | 249.97 seconds |
| Started | Oct 12 03:20:42 PM UTC 24 |
| Finished | Oct 12 03:24:55 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292355826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3292355826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.563238887 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 105492838253 ps |
| CPU time | 201.94 seconds |
| Started | Oct 12 04:24:07 PM UTC 24 |
| Finished | Oct 12 04:27:32 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563238887 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.563238887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.2951029740 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 305952058514 ps |
| CPU time | 534.79 seconds |
| Started | Oct 12 04:25:42 PM UTC 24 |
| Finished | Oct 12 04:34:42 PM UTC 24 |
| Peak memory | 200412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951029740 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2951029740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.3970231962 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 10165786543 ps |
| CPU time | 30.33 seconds |
| Started | Oct 12 03:21:27 PM UTC 24 |
| Finished | Oct 12 03:21:58 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970231962 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3970231962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.1932473419 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 40245295420 ps |
| CPU time | 123.56 seconds |
| Started | Oct 12 04:27:33 PM UTC 24 |
| Finished | Oct 12 04:29:39 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932473419 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1932473419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.883776318 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 217884666160 ps |
| CPU time | 199.85 seconds |
| Started | Oct 12 04:27:49 PM UTC 24 |
| Finished | Oct 12 04:31:13 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883776318 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.883776318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1366958710 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2346252581713 ps |
| CPU time | 1185.18 seconds |
| Started | Oct 12 03:14:03 PM UTC 24 |
| Finished | Oct 12 03:34:01 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366958710 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.1366958710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3153603536 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 143916913346 ps |
| CPU time | 445.69 seconds |
| Started | Oct 12 03:25:33 PM UTC 24 |
| Finished | Oct 12 03:33:04 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153603536 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.3153603536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.4279609131 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 982377600356 ps |
| CPU time | 330.88 seconds |
| Started | Oct 12 03:27:46 PM UTC 24 |
| Finished | Oct 12 03:33:21 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279609131 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.4279609131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.4132094388 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 82932046622 ps |
| CPU time | 142.49 seconds |
| Started | Oct 12 03:32:27 PM UTC 24 |
| Finished | Oct 12 03:34:52 PM UTC 24 |
| Peak memory | 198720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132094388 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.4132094388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1416933939 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 171656341571 ps |
| CPU time | 297.01 seconds |
| Started | Oct 12 03:34:42 PM UTC 24 |
| Finished | Oct 12 03:39:43 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416933939 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1416933939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2234382321 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 77689107130 ps |
| CPU time | 203.56 seconds |
| Started | Oct 12 03:40:42 PM UTC 24 |
| Finished | Oct 12 03:44:09 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234382321 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2234382321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.821663781 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1685719835636 ps |
| CPU time | 742.15 seconds |
| Started | Oct 12 03:49:16 PM UTC 24 |
| Finished | Oct 12 04:01:47 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821663781 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.821663781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3464481523 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 108651187 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464481523 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.3464481523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.169709441 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 77543507 ps |
| CPU time | 2 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169709441 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.169709441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1376225745 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13266585 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:19 PM UTC 24 |
| Peak memory | 199924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376225745 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1376225745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2806821733 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 218084263 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2806821733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.2806821733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.245350187 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 37727628 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:19 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245350187 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.245350187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.808381191 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 122902177 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808381191 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.808381191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2322558332 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 241067138 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322558332 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.2322558332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2588774724 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 154061098 ps |
| CPU time | 0.67 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588774724 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.2588774724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.616967358 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 438047927 ps |
| CPU time | 2.8 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:22 PM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616967358 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.616967358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.106920359 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 68572785 ps |
| CPU time | 0.59 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106920359 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.106920359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1297967880 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 77373393 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1297967880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.1297967880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.2800921381 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 34759477 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800921381 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2800921381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4292003523 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22333864 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292003523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.4292003523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.4034846517 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 50552891 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 203116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034846517 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4034846517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1572647020 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 525510758 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 05:36:17 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572647020 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1572647020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2699324778 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 31254878 ps |
| CPU time | 0.55 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2699324778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.2699324778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.442967512 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 14180417 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442967512 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.442967512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.4009312799 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 16256659 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009312799 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4009312799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2859372411 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 23994056 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859372411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.2859372411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.1498767197 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 453109438 ps |
| CPU time | 1.2 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498767197 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1498767197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2860699390 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 50202784 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860699390 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.2860699390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.447080232 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 56116285 ps |
| CPU time | 0.64 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=447080232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_cs r_mem_rw_with_rand_reset.447080232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.557018669 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 32802264 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557018669 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.557018669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.2364197907 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 34085778 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364197907 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2364197907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.456349590 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 18890727 ps |
| CPU time | 0.64 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456349590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.456349590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.1872247244 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 42931097 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872247244 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1872247244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.989412699 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 139455601 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989412699 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.989412699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3688920130 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 140656303 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3688920130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.3688920130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3491629381 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 45309781 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491629381 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3491629381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.634606382 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 20460897 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634606382 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.634606382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3836995885 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 118102969 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836995885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.3836995885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.3678549506 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 99955489 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678549506 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3678549506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1751829142 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 335022636 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751829142 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1751829142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2938740464 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 51214183 ps |
| CPU time | 0.56 seconds |
| Started | Oct 12 05:37:03 PM UTC 24 |
| Finished | Oct 12 05:37:05 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2938740464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2938740464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.1934779085 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 22032834 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:03 PM UTC 24 |
| Finished | Oct 12 05:37:05 PM UTC 24 |
| Peak memory | 199352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934779085 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1934779085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2122853933 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 71194435 ps |
| CPU time | 0.59 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122853933 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2122853933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.500727990 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 63116544 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:37:03 PM UTC 24 |
| Finished | Oct 12 05:37:05 PM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500727990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.500727990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.641224027 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 182729646 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641224027 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.641224027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2671290868 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 264922854 ps |
| CPU time | 0.96 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671290868 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.2671290868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2218055763 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 34923318 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2218055763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.2218055763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1131155016 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 58639243 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:06 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131155016 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1131155016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1597813219 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 25437896 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:06 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597813219 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1597813219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3478811645 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 216574054 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478811645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.3478811645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.1800120220 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 37240606 ps |
| CPU time | 1.64 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800120220 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1800120220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1148097385 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 103294425 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1148097385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1148097385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3346331534 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 14462671 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346331534 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3346331534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1102080048 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 35606166 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:06 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102080048 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1102080048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1461705427 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 66252784 ps |
| CPU time | 0.65 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461705427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.1461705427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2958736961 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 93910676 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958736961 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2958736961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3360275360 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 234828896 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360275360 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3360275360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2296000896 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 31222505 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2296000896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.2296000896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1775781686 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 14606576 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775781686 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1775781686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1506802969 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 46469318 ps |
| CPU time | 0.57 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506802969 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1506802969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2745687129 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 17523833 ps |
| CPU time | 0.63 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745687129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.2745687129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4108471680 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 47010178 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:08 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108471680 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4108471680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1584349421 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1643562641 ps |
| CPU time | 1.17 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584349421 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.1584349421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3892984257 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 119046846 ps |
| CPU time | 0.73 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3892984257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.3892984257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2885669875 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 13951056 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885669875 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2885669875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.4259140071 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 18887201 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259140071 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4259140071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1151386207 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 245388599 ps |
| CPU time | 0.69 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151386207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.1151386207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.1576143130 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 303857958 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:08 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576143130 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1576143130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.327341649 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 142048539 ps |
| CPU time | 0.74 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327341649 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.327341649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3804493842 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 34872274 ps |
| CPU time | 0.79 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3804493842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.3804493842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.759484074 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 32476453 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 198444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759484074 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.759484074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2343949200 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 17188474 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343949200 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2343949200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3639462163 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 59254610 ps |
| CPU time | 0.65 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639462163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3639462163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.813875724 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 185755486 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:08 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813875724 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.813875724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.548948179 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 49984165 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548948179 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.548948179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3735288082 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 32099311 ps |
| CPU time | 0.73 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3735288082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3735288082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1500902211 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 23689398 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500902211 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1500902211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.598860817 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 12299858 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598860817 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.598860817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.411144145 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 41109946 ps |
| CPU time | 0.75 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411144145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.411144145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.60685538 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 75651171 ps |
| CPU time | 0.86 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:08 PM UTC 24 |
| Peak memory | 199168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60685538 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.60685538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.134206413 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 120571828 ps |
| CPU time | 0.71 seconds |
| Started | Oct 12 05:37:05 PM UTC 24 |
| Finished | Oct 12 05:37:07 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134206413 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.134206413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.186880863 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 140345433 ps |
| CPU time | 0.7 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186880863 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.186880863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2016773175 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1633356231 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:23 PM UTC 24 |
| Peak memory | 200968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016773175 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2016773175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2453687827 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 67964181 ps |
| CPU time | 0.56 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453687827 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.2453687827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.775312534 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 87131087 ps |
| CPU time | 0.66 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=775312534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr _mem_rw_with_rand_reset.775312534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.2588026321 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 22978771 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588026321 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2588026321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2623152801 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 13898272 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:20 PM UTC 24 |
| Peak memory | 199192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623152801 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2623152801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3360109743 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 256327330 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360109743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.3360109743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.1641785560 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1301674734 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 201420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641785560 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1641785560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4038538596 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 109653813 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 198868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038538596 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.4038538596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3444912960 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 14591558 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444912960 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3444912960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.928837860 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 14920307 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928837860 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.928837860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.168287799 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 90978262 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168287799 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.168287799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2487485607 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 40806932 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487485607 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2487485607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1240662835 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 52041465 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:09 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240662835 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1240662835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1378035082 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 15430249 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378035082 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1378035082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1820488407 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 18075252 ps |
| CPU time | 0.53 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820488407 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1820488407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2300458413 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 13930416 ps |
| CPU time | 0.53 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300458413 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2300458413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.4269533271 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 29280862 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269533271 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.4269533271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3961843812 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 20592918 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961843812 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3961843812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4227190317 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 47638552 ps |
| CPU time | 0.58 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:00 PM UTC 24 |
| Peak memory | 199344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227190317 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.4227190317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2896316824 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1140293788 ps |
| CPU time | 2.84 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:23 PM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896316824 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.2896316824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.209108085 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 69682829 ps |
| CPU time | 0.57 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209108085 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.209108085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4172847814 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 254245840 ps |
| CPU time | 1.36 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4172847814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.4172847814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.2841445200 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 12761650 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841445200 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2841445200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.2901322609 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 18670603 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901322609 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2901322609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1971168339 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 56936216 ps |
| CPU time | 0.55 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971168339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.1971168339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2978299972 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 154356251 ps |
| CPU time | 1.23 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978299972 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2978299972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1093215600 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 84098154 ps |
| CPU time | 0.73 seconds |
| Started | Oct 12 05:36:18 PM UTC 24 |
| Finished | Oct 12 05:36:21 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093215600 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.1093215600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3161239689 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 55734615 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161239689 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3161239689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.3505952339 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 138834980 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505952339 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3505952339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2355574052 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 38767424 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355574052 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2355574052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1586901713 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 23199080 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586901713 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1586901713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.1529087564 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 42369957 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529087564 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1529087564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2775768881 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 15251736 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775768881 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2775768881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.282058113 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 38964280 ps |
| CPU time | 0.46 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:11 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282058113 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.282058113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.1348260895 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 15880339 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348260895 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1348260895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.935626025 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 34456036 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935626025 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.935626025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4010680666 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 15970027 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010680666 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4010680666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2293989609 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 32833114 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293989609 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.2293989609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.970786917 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 219413608 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970786917 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.970786917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.916269382 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12323196 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:00 PM UTC 24 |
| Peak memory | 199276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916269382 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.916269382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2475774485 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 37722167 ps |
| CPU time | 0.6 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2475774485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.2475774485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.397753239 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 23642069 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:00 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397753239 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.397753239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.2508235811 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 19985117 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:00 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508235811 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2508235811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.150808020 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20858490 ps |
| CPU time | 0.53 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150808020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.150808020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.3222599359 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 48231852 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 201016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222599359 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3222599359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.378633670 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 835837474 ps |
| CPU time | 0.98 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378633670 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.378633670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2032478376 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 24702099 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032478376 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2032478376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.638585861 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 44244756 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638585861 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.638585861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2728662257 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 188972477 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728662257 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2728662257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1446249198 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 48778349 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446249198 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1446249198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.4141602940 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 19260946 ps |
| CPU time | 0.55 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141602940 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4141602940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1896331496 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 40151992 ps |
| CPU time | 0.48 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896331496 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1896331496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2155016366 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 17612176 ps |
| CPU time | 0.52 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155016366 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2155016366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.1394473760 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 35850809 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394473760 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1394473760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4286500433 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 36480823 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286500433 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4286500433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.613132449 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 46809077 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:10 PM UTC 24 |
| Finished | Oct 12 05:37:12 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613132449 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.613132449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1659379797 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 32366239 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1659379797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.1659379797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.2437415629 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 12001359 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437415629 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2437415629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.4238443856 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 23284556 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238443856 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4238443856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3951508435 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 68993530 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951508435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.3951508435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.1661711279 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 64231931 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661711279 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1661711279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3948082931 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 344826598 ps |
| CPU time | 0.72 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948082931 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.3948082931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1262046908 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 299680688 ps |
| CPU time | 0.6 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1262046908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.1262046908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.183683851 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 14231754 ps |
| CPU time | 0.53 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183683851 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.183683851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.1175132548 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13660545 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175132548 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1175132548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3412553100 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 137624384 ps |
| CPU time | 0.54 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412553100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.3412553100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.666336087 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 58313445 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 201472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666336087 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.666336087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3761271578 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 453086665 ps |
| CPU time | 0.8 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761271578 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.3761271578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4263306044 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 163634186 ps |
| CPU time | 1.06 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4263306044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.4263306044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.1304614538 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 83923279 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304614538 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1304614538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.1111124415 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 36631716 ps |
| CPU time | 0.51 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111124415 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1111124415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3229525097 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 195126327 ps |
| CPU time | 0.62 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229525097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.3229525097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3265903089 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 463418008 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 200960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265903089 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3265903089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.254664785 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 24574706 ps |
| CPU time | 0.68 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=254664785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr _mem_rw_with_rand_reset.254664785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.3702971969 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 38028082 ps |
| CPU time | 0.49 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702971969 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3702971969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.1175383572 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 15360869 ps |
| CPU time | 0.47 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175383572 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1175383572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3517426718 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 33150723 ps |
| CPU time | 0.67 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517426718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.3517426718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.2848247476 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 52731684 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848247476 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2848247476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3915855400 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 46214562 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 05:36:59 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915855400 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.3915855400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2207940277 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 135913313 ps |
| CPU time | 0.76 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2207940277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.2207940277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.275418243 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 23420005 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275418243 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.275418243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.2881458512 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 34562291 ps |
| CPU time | 0.5 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:01 PM UTC 24 |
| Peak memory | 199176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881458512 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2881458512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1995976536 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 66129881 ps |
| CPU time | 0.67 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995976536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1995976536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3649704974 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 144622310 ps |
| CPU time | 2.22 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:03 PM UTC 24 |
| Peak memory | 201020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649704974 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3649704974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.242786201 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 250946656 ps |
| CPU time | 1 seconds |
| Started | Oct 12 05:37:00 PM UTC 24 |
| Finished | Oct 12 05:37:02 PM UTC 24 |
| Peak memory | 199112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242786201 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.242786201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.3687070639 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 65590774344 ps |
| CPU time | 25.3 seconds |
| Started | Oct 12 03:13:55 PM UTC 24 |
| Finished | Oct 12 03:14:22 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687070639 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3687070639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.740185011 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 41834414627 ps |
| CPU time | 104.44 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:15:42 PM UTC 24 |
| Peak memory | 197000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740185011 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.740185011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.1290934398 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 925019131043 ps |
| CPU time | 783.41 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:27:07 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290934398 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.1290934398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.758549439 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 93808006337 ps |
| CPU time | 179.04 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:16:58 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758549439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.758549439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3635976684 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 88604528408 ps |
| CPU time | 1964.25 seconds |
| Started | Oct 12 03:13:56 PM UTC 24 |
| Finished | Oct 12 03:47:03 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635976684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3635976684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.232839167 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1130033976 ps |
| CPU time | 1.35 seconds |
| Started | Oct 12 03:13:59 PM UTC 24 |
| Finished | Oct 12 03:14:01 PM UTC 24 |
| Peak memory | 228056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232839167 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.232839167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.1440274950 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 534653852052 ps |
| CPU time | 229.32 seconds |
| Started | Oct 12 03:13:58 PM UTC 24 |
| Finished | Oct 12 03:17:51 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440274950 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.1440274950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.3564771699 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 40272521074 ps |
| CPU time | 134.05 seconds |
| Started | Oct 12 03:17:06 PM UTC 24 |
| Finished | Oct 12 03:19:22 PM UTC 24 |
| Peak memory | 196760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564771699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3564771699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.1614708084 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 145798866191 ps |
| CPU time | 92.45 seconds |
| Started | Oct 12 03:17:03 PM UTC 24 |
| Finished | Oct 12 03:18:37 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614708084 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1614708084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.2592361632 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 105676005744 ps |
| CPU time | 73.51 seconds |
| Started | Oct 12 03:17:06 PM UTC 24 |
| Finished | Oct 12 03:18:21 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592361632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2592361632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.3618900036 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 231913856973 ps |
| CPU time | 301.43 seconds |
| Started | Oct 12 03:17:24 PM UTC 24 |
| Finished | Oct 12 03:22:30 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618900036 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3618900036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2113461808 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 588242351502 ps |
| CPU time | 384.86 seconds |
| Started | Oct 12 04:09:26 PM UTC 24 |
| Finished | Oct 12 04:15:56 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113461808 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2113461808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3321026127 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 186267589565 ps |
| CPU time | 309.65 seconds |
| Started | Oct 12 04:09:59 PM UTC 24 |
| Finished | Oct 12 04:15:12 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321026127 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3321026127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.3585575209 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 128593280341 ps |
| CPU time | 379.33 seconds |
| Started | Oct 12 04:10:09 PM UTC 24 |
| Finished | Oct 12 04:16:33 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585575209 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3585575209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.4266136781 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 351691694707 ps |
| CPU time | 1473.44 seconds |
| Started | Oct 12 04:11:03 PM UTC 24 |
| Finished | Oct 12 04:35:53 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266136781 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4266136781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.3493291634 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 108749637393 ps |
| CPU time | 1169.59 seconds |
| Started | Oct 12 04:11:05 PM UTC 24 |
| Finished | Oct 12 04:30:49 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493291634 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3493291634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.1408915587 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 42636461693 ps |
| CPU time | 102.78 seconds |
| Started | Oct 12 04:12:22 PM UTC 24 |
| Finished | Oct 12 04:14:07 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408915587 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1408915587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.2799903449 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 117777461119 ps |
| CPU time | 216.77 seconds |
| Started | Oct 12 04:12:56 PM UTC 24 |
| Finished | Oct 12 04:16:36 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799903449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2799903449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.4266931665 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 269139201425 ps |
| CPU time | 458.85 seconds |
| Started | Oct 12 03:17:46 PM UTC 24 |
| Finished | Oct 12 03:25:30 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266931665 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.4266931665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.2954447223 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 179621081182 ps |
| CPU time | 261.7 seconds |
| Started | Oct 12 03:17:42 PM UTC 24 |
| Finished | Oct 12 03:22:07 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954447223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2954447223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.4165032583 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 271068661314 ps |
| CPU time | 171.97 seconds |
| Started | Oct 12 03:17:42 PM UTC 24 |
| Finished | Oct 12 03:20:36 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165032583 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4165032583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1305546488 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 293834034 ps |
| CPU time | 1.38 seconds |
| Started | Oct 12 03:17:47 PM UTC 24 |
| Finished | Oct 12 03:17:49 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305546488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1305546488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.981744238 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 222443825673 ps |
| CPU time | 298.43 seconds |
| Started | Oct 12 03:17:50 PM UTC 24 |
| Finished | Oct 12 03:22:53 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981744238 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.981744238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.1853191664 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 378461988319 ps |
| CPU time | 246.48 seconds |
| Started | Oct 12 04:13:18 PM UTC 24 |
| Finished | Oct 12 04:17:28 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853191664 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1853191664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.4227580283 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1163700518985 ps |
| CPU time | 528.16 seconds |
| Started | Oct 12 04:14:08 PM UTC 24 |
| Finished | Oct 12 04:23:03 PM UTC 24 |
| Peak memory | 198988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227580283 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4227580283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.223747039 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 549780082568 ps |
| CPU time | 295.37 seconds |
| Started | Oct 12 04:14:29 PM UTC 24 |
| Finished | Oct 12 04:19:28 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223747039 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.223747039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.3175780936 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 48078477493 ps |
| CPU time | 231.77 seconds |
| Started | Oct 12 04:14:35 PM UTC 24 |
| Finished | Oct 12 04:18:30 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175780936 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3175780936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.2256727713 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 77976621646 ps |
| CPU time | 31.24 seconds |
| Started | Oct 12 03:18:16 PM UTC 24 |
| Finished | Oct 12 03:18:49 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256727713 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.2256727713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1616440221 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 97211787230 ps |
| CPU time | 177.1 seconds |
| Started | Oct 12 03:18:02 PM UTC 24 |
| Finished | Oct 12 03:21:02 PM UTC 24 |
| Peak memory | 196936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616440221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1616440221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.2909583907 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 63211434338 ps |
| CPU time | 502.49 seconds |
| Started | Oct 12 03:17:52 PM UTC 24 |
| Finished | Oct 12 03:26:21 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909583907 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2909583907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2512322155 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 19185588745 ps |
| CPU time | 16.3 seconds |
| Started | Oct 12 03:18:22 PM UTC 24 |
| Finished | Oct 12 03:18:40 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512322155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2512322155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.2838091284 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 335932941827 ps |
| CPU time | 134.4 seconds |
| Started | Oct 12 04:15:57 PM UTC 24 |
| Finished | Oct 12 04:18:14 PM UTC 24 |
| Peak memory | 196808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838091284 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2838091284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.707718507 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 67227451853 ps |
| CPU time | 393.48 seconds |
| Started | Oct 12 04:16:34 PM UTC 24 |
| Finished | Oct 12 04:23:12 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707718507 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.707718507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.184471746 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 96126337788 ps |
| CPU time | 172.49 seconds |
| Started | Oct 12 04:16:38 PM UTC 24 |
| Finished | Oct 12 04:19:33 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184471746 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.184471746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3647735627 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 393986810882 ps |
| CPU time | 1035.74 seconds |
| Started | Oct 12 04:16:50 PM UTC 24 |
| Finished | Oct 12 04:34:17 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647735627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3647735627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.1797884756 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 127577687202 ps |
| CPU time | 149.07 seconds |
| Started | Oct 12 04:17:12 PM UTC 24 |
| Finished | Oct 12 04:19:44 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797884756 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1797884756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.367725451 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 40948994684 ps |
| CPU time | 141.33 seconds |
| Started | Oct 12 04:17:26 PM UTC 24 |
| Finished | Oct 12 04:19:50 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367725451 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.367725451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1172692931 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 790236113517 ps |
| CPU time | 390.9 seconds |
| Started | Oct 12 04:17:30 PM UTC 24 |
| Finished | Oct 12 04:24:06 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172692931 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1172692931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.1879794286 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 108734049499 ps |
| CPU time | 175.81 seconds |
| Started | Oct 12 03:18:45 PM UTC 24 |
| Finished | Oct 12 03:21:43 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879794286 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1879794286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.3162556477 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 699388126167 ps |
| CPU time | 162.29 seconds |
| Started | Oct 12 03:18:41 PM UTC 24 |
| Finished | Oct 12 03:21:25 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162556477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3162556477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.3458087794 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 48706039671 ps |
| CPU time | 62.21 seconds |
| Started | Oct 12 03:18:51 PM UTC 24 |
| Finished | Oct 12 03:19:55 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458087794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3458087794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.1780795926 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 59537782316 ps |
| CPU time | 73.1 seconds |
| Started | Oct 12 04:18:17 PM UTC 24 |
| Finished | Oct 12 04:19:31 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780795926 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1780795926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.532308975 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 159270675036 ps |
| CPU time | 636.48 seconds |
| Started | Oct 12 04:19:25 PM UTC 24 |
| Finished | Oct 12 04:30:09 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532308975 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.532308975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.252736607 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 105332624717 ps |
| CPU time | 79.66 seconds |
| Started | Oct 12 04:19:33 PM UTC 24 |
| Finished | Oct 12 04:20:55 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252736607 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.252736607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.2765360410 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 230160417805 ps |
| CPU time | 1820.14 seconds |
| Started | Oct 12 04:19:33 PM UTC 24 |
| Finished | Oct 12 04:50:14 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765360410 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2765360410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.106955266 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 15057860161 ps |
| CPU time | 33.2 seconds |
| Started | Oct 12 04:19:47 PM UTC 24 |
| Finished | Oct 12 04:20:22 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106955266 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.106955266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1578775570 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 36618607197 ps |
| CPU time | 137.31 seconds |
| Started | Oct 12 04:19:52 PM UTC 24 |
| Finished | Oct 12 04:22:11 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578775570 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1578775570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2128984866 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5031592195 ps |
| CPU time | 17.55 seconds |
| Started | Oct 12 03:19:23 PM UTC 24 |
| Finished | Oct 12 03:19:42 PM UTC 24 |
| Peak memory | 196828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128984866 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2128984866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.2938771375 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 205987785775 ps |
| CPU time | 118.94 seconds |
| Started | Oct 12 03:19:07 PM UTC 24 |
| Finished | Oct 12 03:21:08 PM UTC 24 |
| Peak memory | 196816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938771375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2938771375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.1926006786 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 817174101346 ps |
| CPU time | 385.63 seconds |
| Started | Oct 12 03:19:05 PM UTC 24 |
| Finished | Oct 12 03:25:36 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926006786 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1926006786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.3351359223 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 27761536185 ps |
| CPU time | 55.2 seconds |
| Started | Oct 12 03:19:43 PM UTC 24 |
| Finished | Oct 12 03:20:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351359223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3351359223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.2733659982 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 472455600363 ps |
| CPU time | 1811.43 seconds |
| Started | Oct 12 04:20:14 PM UTC 24 |
| Finished | Oct 12 04:50:46 PM UTC 24 |
| Peak memory | 200576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733659982 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2733659982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.1000326210 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 276934153366 ps |
| CPU time | 396.67 seconds |
| Started | Oct 12 04:20:16 PM UTC 24 |
| Finished | Oct 12 04:26:57 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000326210 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1000326210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.1848014677 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 120901313480 ps |
| CPU time | 371.5 seconds |
| Started | Oct 12 04:20:26 PM UTC 24 |
| Finished | Oct 12 04:26:42 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848014677 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1848014677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.237380104 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14487513832 ps |
| CPU time | 120.41 seconds |
| Started | Oct 12 04:20:56 PM UTC 24 |
| Finished | Oct 12 04:22:59 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237380104 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.237380104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.3598273288 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 103337266693 ps |
| CPU time | 199.07 seconds |
| Started | Oct 12 04:23:01 PM UTC 24 |
| Finished | Oct 12 04:26:23 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598273288 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3598273288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.3542287377 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 99322662947 ps |
| CPU time | 170.05 seconds |
| Started | Oct 12 04:23:05 PM UTC 24 |
| Finished | Oct 12 04:25:58 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542287377 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3542287377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.3944379337 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 136969938980 ps |
| CPU time | 189.66 seconds |
| Started | Oct 12 04:23:13 PM UTC 24 |
| Finished | Oct 12 04:26:26 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944379337 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3944379337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.302849533 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 174914860159 ps |
| CPU time | 333.11 seconds |
| Started | Oct 12 03:20:38 PM UTC 24 |
| Finished | Oct 12 03:26:15 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302849533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.302849533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.2578416406 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 266808360879 ps |
| CPU time | 896 seconds |
| Started | Oct 12 04:24:03 PM UTC 24 |
| Finished | Oct 12 04:39:10 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578416406 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2578416406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.3514078981 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 129385710639 ps |
| CPU time | 275.47 seconds |
| Started | Oct 12 04:24:07 PM UTC 24 |
| Finished | Oct 12 04:28:46 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514078981 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3514078981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.447736261 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 91034609978 ps |
| CPU time | 95.45 seconds |
| Started | Oct 12 04:24:15 PM UTC 24 |
| Finished | Oct 12 04:25:53 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447736261 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.447736261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.1844441616 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 21463170980 ps |
| CPU time | 55.21 seconds |
| Started | Oct 12 04:24:44 PM UTC 24 |
| Finished | Oct 12 04:25:40 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844441616 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1844441616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.4256120566 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 158026331884 ps |
| CPU time | 122.65 seconds |
| Started | Oct 12 04:25:54 PM UTC 24 |
| Finished | Oct 12 04:27:59 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256120566 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4256120566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.910627958 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 237616621911 ps |
| CPU time | 349.1 seconds |
| Started | Oct 12 04:25:58 PM UTC 24 |
| Finished | Oct 12 04:31:52 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910627958 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.910627958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.1227714469 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 379538449948 ps |
| CPU time | 355.33 seconds |
| Started | Oct 12 04:26:10 PM UTC 24 |
| Finished | Oct 12 04:32:11 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227714469 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1227714469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2362812292 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 42723116548 ps |
| CPU time | 86 seconds |
| Started | Oct 12 03:21:10 PM UTC 24 |
| Finished | Oct 12 03:22:38 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362812292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2362812292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.642595935 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 461220838703 ps |
| CPU time | 215.48 seconds |
| Started | Oct 12 03:21:04 PM UTC 24 |
| Finished | Oct 12 03:24:43 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642595935 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.642595935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2560076450 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 15404067636 ps |
| CPU time | 26.41 seconds |
| Started | Oct 12 03:21:33 PM UTC 24 |
| Finished | Oct 12 03:22:01 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560076450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2560076450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.122374714 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 196613724032 ps |
| CPU time | 330.55 seconds |
| Started | Oct 12 04:26:16 PM UTC 24 |
| Finished | Oct 12 04:31:51 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122374714 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.122374714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.1675805649 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 52643194700 ps |
| CPU time | 58.72 seconds |
| Started | Oct 12 04:26:24 PM UTC 24 |
| Finished | Oct 12 04:27:25 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675805649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1675805649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.192034271 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 464781526731 ps |
| CPU time | 539.83 seconds |
| Started | Oct 12 04:26:27 PM UTC 24 |
| Finished | Oct 12 04:35:33 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192034271 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.192034271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.3629121345 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 85223236104 ps |
| CPU time | 575.16 seconds |
| Started | Oct 12 04:26:45 PM UTC 24 |
| Finished | Oct 12 04:36:27 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629121345 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3629121345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.1887145102 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 303694504807 ps |
| CPU time | 921.09 seconds |
| Started | Oct 12 04:26:59 PM UTC 24 |
| Finished | Oct 12 04:42:30 PM UTC 24 |
| Peak memory | 200504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887145102 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1887145102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.663997009 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 119291516305 ps |
| CPU time | 712.18 seconds |
| Started | Oct 12 04:27:59 PM UTC 24 |
| Finished | Oct 12 04:40:00 PM UTC 24 |
| Peak memory | 200384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663997009 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.663997009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.444691574 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 168549085864 ps |
| CPU time | 338.9 seconds |
| Started | Oct 12 04:28:07 PM UTC 24 |
| Finished | Oct 12 04:33:50 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444691574 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.444691574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.127890069 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3361596930980 ps |
| CPU time | 848.23 seconds |
| Started | Oct 12 03:22:01 PM UTC 24 |
| Finished | Oct 12 03:36:19 PM UTC 24 |
| Peak memory | 200344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127890069 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.127890069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.2639774211 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 137363003114 ps |
| CPU time | 184.6 seconds |
| Started | Oct 12 03:21:59 PM UTC 24 |
| Finished | Oct 12 03:25:06 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639774211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2639774211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.484086962 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 50184589775 ps |
| CPU time | 51.99 seconds |
| Started | Oct 12 03:21:53 PM UTC 24 |
| Finished | Oct 12 03:22:46 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484086962 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.484086962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.4170590277 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 72691531194 ps |
| CPU time | 91.27 seconds |
| Started | Oct 12 03:22:07 PM UTC 24 |
| Finished | Oct 12 03:23:40 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170590277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4170590277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.3943972812 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 777821446362 ps |
| CPU time | 316.54 seconds |
| Started | Oct 12 03:22:25 PM UTC 24 |
| Finished | Oct 12 03:27:46 PM UTC 24 |
| Peak memory | 196828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943972812 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.3943972812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3734454803 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 96879198254 ps |
| CPU time | 1502.35 seconds |
| Started | Oct 12 04:28:16 PM UTC 24 |
| Finished | Oct 12 04:53:35 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734454803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3734454803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.2026468380 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 407465291039 ps |
| CPU time | 199.88 seconds |
| Started | Oct 12 04:28:22 PM UTC 24 |
| Finished | Oct 12 04:31:45 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026468380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2026468380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2297861848 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 397791309081 ps |
| CPU time | 1298.67 seconds |
| Started | Oct 12 04:28:44 PM UTC 24 |
| Finished | Oct 12 04:50:37 PM UTC 24 |
| Peak memory | 200364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297861848 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2297861848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.3735026521 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 44085503472 ps |
| CPU time | 100.56 seconds |
| Started | Oct 12 04:28:48 PM UTC 24 |
| Finished | Oct 12 04:30:31 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735026521 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3735026521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.269869718 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1100072666989 ps |
| CPU time | 550.13 seconds |
| Started | Oct 12 04:29:12 PM UTC 24 |
| Finished | Oct 12 04:38:29 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269869718 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.269869718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.2435066250 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 79755147006 ps |
| CPU time | 161.04 seconds |
| Started | Oct 12 04:29:40 PM UTC 24 |
| Finished | Oct 12 04:32:24 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435066250 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2435066250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.1985542964 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 147837222180 ps |
| CPU time | 1894.13 seconds |
| Started | Oct 12 04:29:42 PM UTC 24 |
| Finished | Oct 12 05:01:37 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985542964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1985542964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.500666412 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 83062654070 ps |
| CPU time | 408.72 seconds |
| Started | Oct 12 04:30:02 PM UTC 24 |
| Finished | Oct 12 04:36:56 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500666412 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.500666412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.1404994652 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 176814343701 ps |
| CPU time | 236.24 seconds |
| Started | Oct 12 04:30:10 PM UTC 24 |
| Finished | Oct 12 04:34:11 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404994652 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1404994652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.645941999 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4762006818 ps |
| CPU time | 17.64 seconds |
| Started | Oct 12 03:22:48 PM UTC 24 |
| Finished | Oct 12 03:23:06 PM UTC 24 |
| Peak memory | 196864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645941999 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.645941999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.2588810599 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 135214835658 ps |
| CPU time | 382.34 seconds |
| Started | Oct 12 03:22:40 PM UTC 24 |
| Finished | Oct 12 03:29:07 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588810599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2588810599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.321634310 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 90766467244 ps |
| CPU time | 453.15 seconds |
| Started | Oct 12 03:22:31 PM UTC 24 |
| Finished | Oct 12 03:30:10 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321634310 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.321634310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2440521616 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 116524593714 ps |
| CPU time | 632.42 seconds |
| Started | Oct 12 03:22:54 PM UTC 24 |
| Finished | Oct 12 03:33:33 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440521616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2440521616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all_with_rand_reset.3628780539 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2470914642 ps |
| CPU time | 15.09 seconds |
| Started | Oct 12 03:22:54 PM UTC 24 |
| Finished | Oct 12 03:23:10 PM UTC 24 |
| Peak memory | 200900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3628780539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.rv_timer_stress_all_with_rand_reset.3628780539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.1162576525 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 177565725806 ps |
| CPU time | 393.09 seconds |
| Started | Oct 12 04:30:23 PM UTC 24 |
| Finished | Oct 12 04:37:01 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162576525 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1162576525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2539801945 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 304654334520 ps |
| CPU time | 1762.08 seconds |
| Started | Oct 12 04:30:33 PM UTC 24 |
| Finished | Oct 12 05:00:14 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539801945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2539801945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3135056308 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 758236378772 ps |
| CPU time | 818.34 seconds |
| Started | Oct 12 04:30:51 PM UTC 24 |
| Finished | Oct 12 04:44:39 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135056308 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3135056308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.3918202570 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 81765945308 ps |
| CPU time | 690.91 seconds |
| Started | Oct 12 04:31:15 PM UTC 24 |
| Finished | Oct 12 04:42:55 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918202570 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3918202570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.1486251703 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 170179440257 ps |
| CPU time | 387.71 seconds |
| Started | Oct 12 04:31:25 PM UTC 24 |
| Finished | Oct 12 04:37:58 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486251703 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1486251703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.2034545969 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 47492079284 ps |
| CPU time | 122.75 seconds |
| Started | Oct 12 04:31:45 PM UTC 24 |
| Finished | Oct 12 04:33:50 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034545969 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2034545969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1594976826 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 189139794643 ps |
| CPU time | 107.35 seconds |
| Started | Oct 12 04:31:53 PM UTC 24 |
| Finished | Oct 12 04:33:43 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594976826 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1594976826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.176887439 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 43638344449 ps |
| CPU time | 551.94 seconds |
| Started | Oct 12 04:32:11 PM UTC 24 |
| Finished | Oct 12 04:41:30 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176887439 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.176887439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.1307137487 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 58879911341 ps |
| CPU time | 186.28 seconds |
| Started | Oct 12 04:32:26 PM UTC 24 |
| Finished | Oct 12 04:35:35 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307137487 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1307137487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.3323652244 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 551169588053 ps |
| CPU time | 746.5 seconds |
| Started | Oct 12 03:24:16 PM UTC 24 |
| Finished | Oct 12 03:36:51 PM UTC 24 |
| Peak memory | 200344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323652244 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3323652244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1153116876 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 292739579672 ps |
| CPU time | 270.83 seconds |
| Started | Oct 12 03:23:42 PM UTC 24 |
| Finished | Oct 12 03:28:16 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153116876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1153116876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.2263872500 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 391204801744 ps |
| CPU time | 1776.09 seconds |
| Started | Oct 12 03:23:12 PM UTC 24 |
| Finished | Oct 12 03:53:07 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263872500 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2263872500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.2955864569 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8617780245 ps |
| CPU time | 16.5 seconds |
| Started | Oct 12 03:24:30 PM UTC 24 |
| Finished | Oct 12 03:24:48 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955864569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2955864569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.2435488704 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 87343594105 ps |
| CPU time | 342.41 seconds |
| Started | Oct 12 04:33:10 PM UTC 24 |
| Finished | Oct 12 04:38:57 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435488704 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2435488704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.2906778440 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2899615757611 ps |
| CPU time | 1343 seconds |
| Started | Oct 12 04:33:52 PM UTC 24 |
| Finished | Oct 12 04:56:30 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906778440 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2906778440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.1584044635 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 89740088053 ps |
| CPU time | 173.66 seconds |
| Started | Oct 12 04:33:52 PM UTC 24 |
| Finished | Oct 12 04:36:48 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584044635 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1584044635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.943646273 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 34637753619 ps |
| CPU time | 37.79 seconds |
| Started | Oct 12 04:34:12 PM UTC 24 |
| Finished | Oct 12 04:34:52 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943646273 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.943646273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.480707087 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 871765547 ps |
| CPU time | 4.37 seconds |
| Started | Oct 12 04:34:18 PM UTC 24 |
| Finished | Oct 12 04:34:24 PM UTC 24 |
| Peak memory | 196624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480707087 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.480707087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.397868010 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 11809549353 ps |
| CPU time | 24.43 seconds |
| Started | Oct 12 04:34:27 PM UTC 24 |
| Finished | Oct 12 04:34:52 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397868010 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.397868010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.3376067229 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 16708470688 ps |
| CPU time | 183.86 seconds |
| Started | Oct 12 04:34:43 PM UTC 24 |
| Finished | Oct 12 04:37:50 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376067229 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3376067229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1771138015 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 294576553649 ps |
| CPU time | 187.6 seconds |
| Started | Oct 12 04:34:51 PM UTC 24 |
| Finished | Oct 12 04:38:01 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771138015 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1771138015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2518681221 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 132917746812 ps |
| CPU time | 163.4 seconds |
| Started | Oct 12 04:34:53 PM UTC 24 |
| Finished | Oct 12 04:37:39 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518681221 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2518681221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.1016449179 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 121526647547 ps |
| CPU time | 181.55 seconds |
| Started | Oct 12 03:13:59 PM UTC 24 |
| Finished | Oct 12 03:17:03 PM UTC 24 |
| Peak memory | 196896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016449179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1016449179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.1422501587 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 104283240 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 03:14:01 PM UTC 24 |
| Finished | Oct 12 03:14:03 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422501587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1422501587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1254790630 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 213909038 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 03:14:05 PM UTC 24 |
| Finished | Oct 12 03:14:08 PM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254790630 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1254790630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2441652792 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10701420704 ps |
| CPU time | 5.32 seconds |
| Started | Oct 12 03:25:23 PM UTC 24 |
| Finished | Oct 12 03:25:29 PM UTC 24 |
| Peak memory | 197000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441652792 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2441652792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.674566039 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 569539155114 ps |
| CPU time | 292.96 seconds |
| Started | Oct 12 03:25:07 PM UTC 24 |
| Finished | Oct 12 03:30:04 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674566039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.674566039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.2259663613 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 44090962406 ps |
| CPU time | 369.76 seconds |
| Started | Oct 12 03:24:57 PM UTC 24 |
| Finished | Oct 12 03:31:11 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259663613 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2259663613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.2111347270 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 55555464020 ps |
| CPU time | 136.81 seconds |
| Started | Oct 12 03:25:31 PM UTC 24 |
| Finished | Oct 12 03:27:50 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111347270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2111347270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.2886534248 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4247684989 ps |
| CPU time | 73.83 seconds |
| Started | Oct 12 03:25:31 PM UTC 24 |
| Finished | Oct 12 03:26:46 PM UTC 24 |
| Peak memory | 202892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2886534248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.rv_timer_stress_all_with_rand_reset.2886534248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1639269200 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 95529910634 ps |
| CPU time | 57.99 seconds |
| Started | Oct 12 03:26:22 PM UTC 24 |
| Finished | Oct 12 03:27:21 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639269200 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1639269200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.1493920145 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 369512105339 ps |
| CPU time | 225.99 seconds |
| Started | Oct 12 03:26:18 PM UTC 24 |
| Finished | Oct 12 03:30:07 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493920145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1493920145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.1391625616 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 470939465636 ps |
| CPU time | 201.9 seconds |
| Started | Oct 12 03:25:37 PM UTC 24 |
| Finished | Oct 12 03:29:02 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391625616 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1391625616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.3285759749 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 501154170 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 03:26:48 PM UTC 24 |
| Finished | Oct 12 03:26:50 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285759749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3285759749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.2307106403 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6474263357 ps |
| CPU time | 70.49 seconds |
| Started | Oct 12 03:26:52 PM UTC 24 |
| Finished | Oct 12 03:28:04 PM UTC 24 |
| Peak memory | 202940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2307106403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.rv_timer_stress_all_with_rand_reset.2307106403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.4096751142 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 38143129956 ps |
| CPU time | 67.59 seconds |
| Started | Oct 12 03:27:46 PM UTC 24 |
| Finished | Oct 12 03:28:55 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096751142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4096751142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.1526549719 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 852835823033 ps |
| CPU time | 669.62 seconds |
| Started | Oct 12 03:27:22 PM UTC 24 |
| Finished | Oct 12 03:38:39 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526549719 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1526549719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.970800933 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 477268767 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 03:27:52 PM UTC 24 |
| Finished | Oct 12 03:27:56 PM UTC 24 |
| Peak memory | 196412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970800933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.970800933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.2209304853 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 412440480836 ps |
| CPU time | 425.38 seconds |
| Started | Oct 12 03:28:05 PM UTC 24 |
| Finished | Oct 12 03:35:15 PM UTC 24 |
| Peak memory | 196880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209304853 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.2209304853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.3420017150 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 44778419494 ps |
| CPU time | 75.05 seconds |
| Started | Oct 12 03:28:29 PM UTC 24 |
| Finished | Oct 12 03:29:46 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420017150 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3420017150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.2706230544 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 124568996931 ps |
| CPU time | 322 seconds |
| Started | Oct 12 03:28:19 PM UTC 24 |
| Finished | Oct 12 03:33:45 PM UTC 24 |
| Peak memory | 197080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706230544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2706230544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.2579412078 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 155155519509 ps |
| CPU time | 1391.25 seconds |
| Started | Oct 12 03:28:15 PM UTC 24 |
| Finished | Oct 12 03:51:41 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579412078 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2579412078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.4036297986 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 167242681285 ps |
| CPU time | 186.41 seconds |
| Started | Oct 12 03:28:57 PM UTC 24 |
| Finished | Oct 12 03:32:06 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036297986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4036297986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.1762900728 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 120451177822 ps |
| CPU time | 195.85 seconds |
| Started | Oct 12 03:29:07 PM UTC 24 |
| Finished | Oct 12 03:32:26 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762900728 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.1762900728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.3878163514 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 550435749065 ps |
| CPU time | 432.38 seconds |
| Started | Oct 12 03:29:48 PM UTC 24 |
| Finished | Oct 12 03:37:06 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878163514 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3878163514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.2742532136 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 58536924307 ps |
| CPU time | 73.48 seconds |
| Started | Oct 12 03:29:43 PM UTC 24 |
| Finished | Oct 12 03:30:59 PM UTC 24 |
| Peak memory | 196696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742532136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2742532136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.3402742714 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 141274214270 ps |
| CPU time | 441.15 seconds |
| Started | Oct 12 03:29:17 PM UTC 24 |
| Finished | Oct 12 03:36:44 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402742714 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3402742714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.892007225 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 8031336978 ps |
| CPU time | 9.68 seconds |
| Started | Oct 12 03:30:06 PM UTC 24 |
| Finished | Oct 12 03:30:17 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892007225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.892007225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2990284806 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 290527714567 ps |
| CPU time | 545.11 seconds |
| Started | Oct 12 03:30:38 PM UTC 24 |
| Finished | Oct 12 03:39:49 PM UTC 24 |
| Peak memory | 196680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990284806 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2990284806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.1783620530 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 313753376692 ps |
| CPU time | 378.57 seconds |
| Started | Oct 12 03:30:22 PM UTC 24 |
| Finished | Oct 12 03:36:46 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783620530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1783620530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.353725706 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 662652691102 ps |
| CPU time | 1164.9 seconds |
| Started | Oct 12 03:30:18 PM UTC 24 |
| Finished | Oct 12 03:49:56 PM UTC 24 |
| Peak memory | 200760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353725706 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.353725706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2795574593 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 84116376 ps |
| CPU time | 1.67 seconds |
| Started | Oct 12 03:31:00 PM UTC 24 |
| Finished | Oct 12 03:31:03 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795574593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2795574593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.1087667132 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 355682048518 ps |
| CPU time | 1049.33 seconds |
| Started | Oct 12 03:31:12 PM UTC 24 |
| Finished | Oct 12 03:48:54 PM UTC 24 |
| Peak memory | 200444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087667132 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.1087667132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.2523323178 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 79814504765 ps |
| CPU time | 149.74 seconds |
| Started | Oct 12 03:32:09 PM UTC 24 |
| Finished | Oct 12 03:34:41 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523323178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2523323178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2844562391 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 253762962686 ps |
| CPU time | 519.05 seconds |
| Started | Oct 12 03:31:27 PM UTC 24 |
| Finished | Oct 12 03:40:12 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844562391 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2844562391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1883901142 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 10335308941 ps |
| CPU time | 404.01 seconds |
| Started | Oct 12 03:33:05 PM UTC 24 |
| Finished | Oct 12 03:39:54 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883901142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1883901142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.4939297 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 68795229 ps |
| CPU time | 0.84 seconds |
| Started | Oct 12 03:33:29 PM UTC 24 |
| Finished | Oct 12 03:33:31 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4939297 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.4939297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.1641885886 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 17801510031 ps |
| CPU time | 28.56 seconds |
| Started | Oct 12 03:33:43 PM UTC 24 |
| Finished | Oct 12 03:34:13 PM UTC 24 |
| Peak memory | 197016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641885886 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1641885886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.3416392602 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 183767510335 ps |
| CPU time | 336 seconds |
| Started | Oct 12 03:33:35 PM UTC 24 |
| Finished | Oct 12 03:39:16 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416392602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3416392602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1287656126 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 200857980745 ps |
| CPU time | 117.84 seconds |
| Started | Oct 12 03:33:33 PM UTC 24 |
| Finished | Oct 12 03:35:33 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287656126 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1287656126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.3675513410 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 71932810807 ps |
| CPU time | 1431.99 seconds |
| Started | Oct 12 03:33:46 PM UTC 24 |
| Finished | Oct 12 03:57:54 PM UTC 24 |
| Peak memory | 200512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675513410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3675513410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.3735341178 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 495896158901 ps |
| CPU time | 849.64 seconds |
| Started | Oct 12 03:33:58 PM UTC 24 |
| Finished | Oct 12 03:48:17 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735341178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.3735341178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3564065179 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 63380730569 ps |
| CPU time | 156 seconds |
| Started | Oct 12 03:34:14 PM UTC 24 |
| Finished | Oct 12 03:36:52 PM UTC 24 |
| Peak memory | 196896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564065179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3564065179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.4225315667 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 53733390997 ps |
| CPU time | 115.9 seconds |
| Started | Oct 12 03:34:02 PM UTC 24 |
| Finished | Oct 12 03:36:00 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225315667 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4225315667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.918601279 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 120837947901 ps |
| CPU time | 88.43 seconds |
| Started | Oct 12 03:34:52 PM UTC 24 |
| Finished | Oct 12 03:36:22 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918601279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.918601279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.3035984308 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1357425824 ps |
| CPU time | 18.57 seconds |
| Started | Oct 12 03:34:58 PM UTC 24 |
| Finished | Oct 12 03:35:18 PM UTC 24 |
| Peak memory | 200900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3035984308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.3035984308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.1661120011 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 41104631181 ps |
| CPU time | 25.72 seconds |
| Started | Oct 12 03:35:49 PM UTC 24 |
| Finished | Oct 12 03:36:16 PM UTC 24 |
| Peak memory | 196944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661120011 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.1661120011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.476070172 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 440158095902 ps |
| CPU time | 251.65 seconds |
| Started | Oct 12 03:35:35 PM UTC 24 |
| Finished | Oct 12 03:39:50 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476070172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.476070172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.733014824 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 79466257134 ps |
| CPU time | 318.69 seconds |
| Started | Oct 12 03:35:18 PM UTC 24 |
| Finished | Oct 12 03:40:42 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733014824 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.733014824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1319551528 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 39634313849 ps |
| CPU time | 95.79 seconds |
| Started | Oct 12 03:35:57 PM UTC 24 |
| Finished | Oct 12 03:37:35 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319551528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1319551528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.621175027 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 129648807503 ps |
| CPU time | 113.72 seconds |
| Started | Oct 12 03:14:18 PM UTC 24 |
| Finished | Oct 12 03:16:14 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621175027 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.621175027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.13902273 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 183606645561 ps |
| CPU time | 203.68 seconds |
| Started | Oct 12 03:14:14 PM UTC 24 |
| Finished | Oct 12 03:17:40 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13902273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.13902273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.463205276 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 219548780286 ps |
| CPU time | 436.3 seconds |
| Started | Oct 12 03:14:09 PM UTC 24 |
| Finished | Oct 12 03:21:31 PM UTC 24 |
| Peak memory | 198732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463205276 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.463205276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.1239252832 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 72608487337 ps |
| CPU time | 103.82 seconds |
| Started | Oct 12 03:14:18 PM UTC 24 |
| Finished | Oct 12 03:16:04 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239252832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1239252832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.3327888196 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 92711443 ps |
| CPU time | 1.43 seconds |
| Started | Oct 12 03:14:22 PM UTC 24 |
| Finished | Oct 12 03:14:25 PM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327888196 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3327888196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.2101523512 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 18659925 ps |
| CPU time | 0.85 seconds |
| Started | Oct 12 03:14:20 PM UTC 24 |
| Finished | Oct 12 03:14:22 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101523512 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.2101523512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.2257222975 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 10116180639 ps |
| CPU time | 11.68 seconds |
| Started | Oct 12 03:36:21 PM UTC 24 |
| Finished | Oct 12 03:36:34 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257222975 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2257222975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2685450078 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 219942395448 ps |
| CPU time | 404.11 seconds |
| Started | Oct 12 03:36:17 PM UTC 24 |
| Finished | Oct 12 03:43:07 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685450078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2685450078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3436991309 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 30550963343 ps |
| CPU time | 145.8 seconds |
| Started | Oct 12 03:36:09 PM UTC 24 |
| Finished | Oct 12 03:38:38 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436991309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3436991309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.684610811 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4464833739 ps |
| CPU time | 87.75 seconds |
| Started | Oct 12 03:36:23 PM UTC 24 |
| Finished | Oct 12 03:37:53 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684610811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.684610811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.2720280691 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3944544138608 ps |
| CPU time | 865.85 seconds |
| Started | Oct 12 03:36:45 PM UTC 24 |
| Finished | Oct 12 03:51:21 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720280691 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.2720280691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.2397911218 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 25927829895 ps |
| CPU time | 44.52 seconds |
| Started | Oct 12 03:36:54 PM UTC 24 |
| Finished | Oct 12 03:37:40 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397911218 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2397911218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.758612260 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 644976199461 ps |
| CPU time | 175.26 seconds |
| Started | Oct 12 03:36:54 PM UTC 24 |
| Finished | Oct 12 03:39:52 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758612260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.758612260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.3458550430 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4364577729 ps |
| CPU time | 25.77 seconds |
| Started | Oct 12 03:37:08 PM UTC 24 |
| Finished | Oct 12 03:37:35 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458550430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3458550430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3645548538 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1819900931375 ps |
| CPU time | 1130.16 seconds |
| Started | Oct 12 03:37:14 PM UTC 24 |
| Finished | Oct 12 03:56:16 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645548538 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.3645548538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.293181169 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 169295543909 ps |
| CPU time | 358.45 seconds |
| Started | Oct 12 03:37:36 PM UTC 24 |
| Finished | Oct 12 03:43:39 PM UTC 24 |
| Peak memory | 197008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293181169 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.293181169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.419804833 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 320739095280 ps |
| CPU time | 240.33 seconds |
| Started | Oct 12 03:37:36 PM UTC 24 |
| Finished | Oct 12 03:41:40 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419804833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.419804833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.197645804 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 86967666526 ps |
| CPU time | 193.16 seconds |
| Started | Oct 12 03:37:24 PM UTC 24 |
| Finished | Oct 12 03:40:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197645804 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.197645804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.529334498 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 55972699026 ps |
| CPU time | 212.31 seconds |
| Started | Oct 12 03:37:40 PM UTC 24 |
| Finished | Oct 12 03:41:16 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529334498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.529334498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.917655090 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4381313757 ps |
| CPU time | 61.42 seconds |
| Started | Oct 12 03:37:54 PM UTC 24 |
| Finished | Oct 12 03:38:58 PM UTC 24 |
| Peak memory | 203224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=917655090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.917655090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.854203791 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 20497154513 ps |
| CPU time | 24.91 seconds |
| Started | Oct 12 03:38:59 PM UTC 24 |
| Finished | Oct 12 03:39:25 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854203791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.854203791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.4051868768 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 180975389708 ps |
| CPU time | 83.87 seconds |
| Started | Oct 12 03:38:41 PM UTC 24 |
| Finished | Oct 12 03:40:06 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051868768 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4051868768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3463279115 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 14166846120 ps |
| CPU time | 23.06 seconds |
| Started | Oct 12 03:39:17 PM UTC 24 |
| Finished | Oct 12 03:39:41 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463279115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3463279115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all_with_rand_reset.1493017288 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1849401514 ps |
| CPU time | 18.68 seconds |
| Started | Oct 12 03:39:27 PM UTC 24 |
| Finished | Oct 12 03:39:47 PM UTC 24 |
| Peak memory | 200964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1493017288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.rv_timer_stress_all_with_rand_reset.1493017288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.2334344822 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 60869599413 ps |
| CPU time | 102.44 seconds |
| Started | Oct 12 03:39:49 PM UTC 24 |
| Finished | Oct 12 03:41:34 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334344822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2334344822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.3344395606 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 11058139784 ps |
| CPU time | 7.32 seconds |
| Started | Oct 12 03:39:52 PM UTC 24 |
| Finished | Oct 12 03:40:00 PM UTC 24 |
| Peak memory | 196676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344395606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3344395606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.769975869 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5363064652 ps |
| CPU time | 54.84 seconds |
| Started | Oct 12 03:39:54 PM UTC 24 |
| Finished | Oct 12 03:40:50 PM UTC 24 |
| Peak memory | 203084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=769975869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.769975869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3233818217 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1000245275761 ps |
| CPU time | 420.7 seconds |
| Started | Oct 12 03:40:12 PM UTC 24 |
| Finished | Oct 12 03:47:18 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233818217 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3233818217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4112538317 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 125350479040 ps |
| CPU time | 120.56 seconds |
| Started | Oct 12 03:40:08 PM UTC 24 |
| Finished | Oct 12 03:42:11 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112538317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4112538317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.2923385267 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 31101805 ps |
| CPU time | 0.78 seconds |
| Started | Oct 12 03:40:32 PM UTC 24 |
| Finished | Oct 12 03:40:34 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923385267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2923385267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.2681551436 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 90567874754 ps |
| CPU time | 132.4 seconds |
| Started | Oct 12 03:40:42 PM UTC 24 |
| Finished | Oct 12 03:42:57 PM UTC 24 |
| Peak memory | 197016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681551436 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.2681551436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.3835580135 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 72214486184 ps |
| CPU time | 110.35 seconds |
| Started | Oct 12 03:40:51 PM UTC 24 |
| Finished | Oct 12 03:42:43 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835580135 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3835580135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2246738443 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 365555314783 ps |
| CPU time | 137.09 seconds |
| Started | Oct 12 03:40:42 PM UTC 24 |
| Finished | Oct 12 03:43:02 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246738443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2246738443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.2858873045 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 735539183 ps |
| CPU time | 3.86 seconds |
| Started | Oct 12 03:41:09 PM UTC 24 |
| Finished | Oct 12 03:41:14 PM UTC 24 |
| Peak memory | 196828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858873045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2858873045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.1514984233 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 243392074877 ps |
| CPU time | 413.82 seconds |
| Started | Oct 12 03:41:41 PM UTC 24 |
| Finished | Oct 12 03:48:40 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514984233 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.1514984233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.786636200 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 46329920942 ps |
| CPU time | 56.64 seconds |
| Started | Oct 12 03:41:35 PM UTC 24 |
| Finished | Oct 12 03:42:34 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786636200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.786636200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.870204631 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 697729386548 ps |
| CPU time | 148.35 seconds |
| Started | Oct 12 03:41:31 PM UTC 24 |
| Finished | Oct 12 03:44:02 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870204631 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.870204631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all_with_rand_reset.44798028 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10224749089 ps |
| CPU time | 33.44 seconds |
| Started | Oct 12 03:42:11 PM UTC 24 |
| Finished | Oct 12 03:42:46 PM UTC 24 |
| Peak memory | 202936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=44798028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.44798028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2120942088 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 381000234885 ps |
| CPU time | 285.37 seconds |
| Started | Oct 12 03:42:48 PM UTC 24 |
| Finished | Oct 12 03:47:37 PM UTC 24 |
| Peak memory | 196872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120942088 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2120942088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2874505726 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 481579042693 ps |
| CPU time | 283.85 seconds |
| Started | Oct 12 03:42:44 PM UTC 24 |
| Finished | Oct 12 03:47:32 PM UTC 24 |
| Peak memory | 196832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874505726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2874505726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.4006475979 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 377815955891 ps |
| CPU time | 130.54 seconds |
| Started | Oct 12 03:42:36 PM UTC 24 |
| Finished | Oct 12 03:44:48 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006475979 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4006475979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.2798871859 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 77620288 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 03:42:58 PM UTC 24 |
| Finished | Oct 12 03:43:01 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798871859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2798871859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3726494417 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 221574168996 ps |
| CPU time | 936.3 seconds |
| Started | Oct 12 03:43:02 PM UTC 24 |
| Finished | Oct 12 03:58:50 PM UTC 24 |
| Peak memory | 200452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726494417 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.3726494417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.695085250 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 16449447407 ps |
| CPU time | 43.14 seconds |
| Started | Oct 12 03:43:59 PM UTC 24 |
| Finished | Oct 12 03:44:43 PM UTC 24 |
| Peak memory | 196816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695085250 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.695085250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1086052743 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 45376671936 ps |
| CPU time | 145.9 seconds |
| Started | Oct 12 03:43:40 PM UTC 24 |
| Finished | Oct 12 03:46:09 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086052743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1086052743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.1953052365 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 559082401242 ps |
| CPU time | 967.75 seconds |
| Started | Oct 12 03:43:08 PM UTC 24 |
| Finished | Oct 12 03:59:27 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953052365 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1953052365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2385559826 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 159165264636 ps |
| CPU time | 120.02 seconds |
| Started | Oct 12 03:44:03 PM UTC 24 |
| Finished | Oct 12 03:46:05 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385559826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2385559826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3395538344 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 590184172866 ps |
| CPU time | 376.48 seconds |
| Started | Oct 12 03:14:25 PM UTC 24 |
| Finished | Oct 12 03:20:46 PM UTC 24 |
| Peak memory | 196752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395538344 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3395538344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.974035294 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 83601531804 ps |
| CPU time | 99.14 seconds |
| Started | Oct 12 03:14:25 PM UTC 24 |
| Finished | Oct 12 03:16:06 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974035294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.974035294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.4125496951 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 104632951308 ps |
| CPU time | 107.8 seconds |
| Started | Oct 12 03:14:25 PM UTC 24 |
| Finished | Oct 12 03:16:15 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125496951 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4125496951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.3996164074 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 93788674988 ps |
| CPU time | 310.15 seconds |
| Started | Oct 12 03:14:27 PM UTC 24 |
| Finished | Oct 12 03:19:42 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996164074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3996164074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.1329802197 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 58710595 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 03:14:32 PM UTC 24 |
| Finished | Oct 12 03:14:34 PM UTC 24 |
| Peak memory | 226008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329802197 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1329802197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.833473435 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 146031843178 ps |
| CPU time | 263.85 seconds |
| Started | Oct 12 03:44:49 PM UTC 24 |
| Finished | Oct 12 03:49:17 PM UTC 24 |
| Peak memory | 196928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833473435 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.833473435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1296488325 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 96368692286 ps |
| CPU time | 177.97 seconds |
| Started | Oct 12 03:44:45 PM UTC 24 |
| Finished | Oct 12 03:47:46 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296488325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1296488325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.2405744309 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 24933069788 ps |
| CPU time | 33.5 seconds |
| Started | Oct 12 03:44:29 PM UTC 24 |
| Finished | Oct 12 03:45:04 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405744309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2405744309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.3601782327 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 952901765 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 03:45:05 PM UTC 24 |
| Finished | Oct 12 03:45:09 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601782327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3601782327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.3148006832 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 5852273707 ps |
| CPU time | 94.23 seconds |
| Started | Oct 12 03:45:11 PM UTC 24 |
| Finished | Oct 12 03:46:48 PM UTC 24 |
| Peak memory | 203484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3148006832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.rv_timer_stress_all_with_rand_reset.3148006832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.4191929198 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4086777443431 ps |
| CPU time | 2250.36 seconds |
| Started | Oct 12 03:46:10 PM UTC 24 |
| Finished | Oct 12 04:24:02 PM UTC 24 |
| Peak memory | 200508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191929198 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.4191929198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.1721813027 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 204928483062 ps |
| CPU time | 92.96 seconds |
| Started | Oct 12 03:46:08 PM UTC 24 |
| Finished | Oct 12 03:47:43 PM UTC 24 |
| Peak memory | 196960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721813027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1721813027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.484972612 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 65527746339 ps |
| CPU time | 186.09 seconds |
| Started | Oct 12 03:46:06 PM UTC 24 |
| Finished | Oct 12 03:49:15 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484972612 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.484972612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.926973506 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 20318095154 ps |
| CPU time | 66.91 seconds |
| Started | Oct 12 03:46:10 PM UTC 24 |
| Finished | Oct 12 03:47:19 PM UTC 24 |
| Peak memory | 196812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926973506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.926973506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.497922812 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 324910963733 ps |
| CPU time | 458.95 seconds |
| Started | Oct 12 03:47:04 PM UTC 24 |
| Finished | Oct 12 03:54:49 PM UTC 24 |
| Peak memory | 198720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497922812 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.497922812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.3678143774 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1376181725493 ps |
| CPU time | 713.37 seconds |
| Started | Oct 12 03:47:20 PM UTC 24 |
| Finished | Oct 12 03:59:22 PM UTC 24 |
| Peak memory | 200436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678143774 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3678143774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.1734828050 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 279238624974 ps |
| CPU time | 98.47 seconds |
| Started | Oct 12 03:47:18 PM UTC 24 |
| Finished | Oct 12 03:48:59 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734828050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1734828050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.2007565572 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 141646081950 ps |
| CPU time | 2433.87 seconds |
| Started | Oct 12 03:47:14 PM UTC 24 |
| Finished | Oct 12 04:28:13 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007565572 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2007565572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1528575023 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 232602499110 ps |
| CPU time | 102.97 seconds |
| Started | Oct 12 03:47:33 PM UTC 24 |
| Finished | Oct 12 03:49:18 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528575023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1528575023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all_with_rand_reset.1548966750 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2430756811 ps |
| CPU time | 27.37 seconds |
| Started | Oct 12 03:47:39 PM UTC 24 |
| Finished | Oct 12 03:48:07 PM UTC 24 |
| Peak memory | 201092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1548966750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.rv_timer_stress_all_with_rand_reset.1548966750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.3321437640 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 96848838919 ps |
| CPU time | 62.52 seconds |
| Started | Oct 12 03:48:19 PM UTC 24 |
| Finished | Oct 12 03:49:24 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321437640 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3321437640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.3788421041 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 44032393061 ps |
| CPU time | 85.22 seconds |
| Started | Oct 12 03:48:09 PM UTC 24 |
| Finished | Oct 12 03:49:36 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788421041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3788421041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.478468739 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 393725891040 ps |
| CPU time | 426.72 seconds |
| Started | Oct 12 03:47:47 PM UTC 24 |
| Finished | Oct 12 03:54:58 PM UTC 24 |
| Peak memory | 196956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478468739 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.478468739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.3594152304 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 698508133000 ps |
| CPU time | 339.26 seconds |
| Started | Oct 12 03:48:41 PM UTC 24 |
| Finished | Oct 12 03:54:25 PM UTC 24 |
| Peak memory | 196684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594152304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3594152304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.901983864 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 38515079743 ps |
| CPU time | 76.35 seconds |
| Started | Oct 12 03:48:59 PM UTC 24 |
| Finished | Oct 12 03:50:17 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901983864 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.901983864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.1941931633 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1440429630554 ps |
| CPU time | 806.1 seconds |
| Started | Oct 12 03:49:20 PM UTC 24 |
| Finished | Oct 12 04:02:55 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941931633 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1941931633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.988659821 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 469713994608 ps |
| CPU time | 256.65 seconds |
| Started | Oct 12 03:49:18 PM UTC 24 |
| Finished | Oct 12 03:53:38 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988659821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.988659821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2071544019 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 37688581435 ps |
| CPU time | 272.55 seconds |
| Started | Oct 12 03:49:26 PM UTC 24 |
| Finished | Oct 12 03:54:03 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071544019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2071544019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.1422046039 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 442840528158 ps |
| CPU time | 660.96 seconds |
| Started | Oct 12 03:49:46 PM UTC 24 |
| Finished | Oct 12 04:00:54 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422046039 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.1422046039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.3399459047 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 14939132263 ps |
| CPU time | 7.34 seconds |
| Started | Oct 12 03:50:18 PM UTC 24 |
| Finished | Oct 12 03:50:27 PM UTC 24 |
| Peak memory | 198720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399459047 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.3399459047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.2309636508 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 133460301054 ps |
| CPU time | 2246.95 seconds |
| Started | Oct 12 03:49:58 PM UTC 24 |
| Finished | Oct 12 04:27:48 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309636508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2309636508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.2503974521 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 336441691 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 03:50:29 PM UTC 24 |
| Finished | Oct 12 03:50:31 PM UTC 24 |
| Peak memory | 195472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503974521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2503974521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.2987357148 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 716391216237 ps |
| CPU time | 1695.95 seconds |
| Started | Oct 12 03:50:49 PM UTC 24 |
| Finished | Oct 12 04:19:23 PM UTC 24 |
| Peak memory | 200364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987357148 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.2987357148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.3683809796 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1048519927100 ps |
| CPU time | 680.59 seconds |
| Started | Oct 12 03:52:05 PM UTC 24 |
| Finished | Oct 12 04:03:33 PM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683809796 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.3683809796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.477234118 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 113011624346 ps |
| CPU time | 132.8 seconds |
| Started | Oct 12 03:51:43 PM UTC 24 |
| Finished | Oct 12 03:53:59 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477234118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.477234118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3309905276 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 55903738756 ps |
| CPU time | 61.01 seconds |
| Started | Oct 12 03:51:23 PM UTC 24 |
| Finished | Oct 12 03:52:26 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309905276 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3309905276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.209577894 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 12145641565 ps |
| CPU time | 16.51 seconds |
| Started | Oct 12 03:52:11 PM UTC 24 |
| Finished | Oct 12 03:52:29 PM UTC 24 |
| Peak memory | 196548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209577894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.209577894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.799287674 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3029952619382 ps |
| CPU time | 2612.16 seconds |
| Started | Oct 12 03:52:30 PM UTC 24 |
| Finished | Oct 12 04:36:28 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799287674 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.799287674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.3121572262 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 440371430402 ps |
| CPU time | 696.12 seconds |
| Started | Oct 12 03:53:10 PM UTC 24 |
| Finished | Oct 12 04:04:54 PM UTC 24 |
| Peak memory | 200620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121572262 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3121572262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2129798638 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 38307958945 ps |
| CPU time | 53.37 seconds |
| Started | Oct 12 03:53:08 PM UTC 24 |
| Finished | Oct 12 03:54:03 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129798638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2129798638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3162819891 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 103905968209 ps |
| CPU time | 667.55 seconds |
| Started | Oct 12 03:52:42 PM UTC 24 |
| Finished | Oct 12 04:03:58 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162819891 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3162819891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.3969701087 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 7965261312 ps |
| CPU time | 10.08 seconds |
| Started | Oct 12 03:53:38 PM UTC 24 |
| Finished | Oct 12 03:53:49 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969701087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3969701087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1874516626 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 31469078411 ps |
| CPU time | 104.84 seconds |
| Started | Oct 12 03:54:05 PM UTC 24 |
| Finished | Oct 12 03:55:52 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874516626 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1874516626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.184518045 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 245644372153 ps |
| CPU time | 217.52 seconds |
| Started | Oct 12 03:54:05 PM UTC 24 |
| Finished | Oct 12 03:57:46 PM UTC 24 |
| Peak memory | 196756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184518045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.184518045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.1775556197 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1553871638825 ps |
| CPU time | 736.74 seconds |
| Started | Oct 12 03:54:00 PM UTC 24 |
| Finished | Oct 12 04:06:26 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775556197 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1775556197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.1436218560 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 8561947707 ps |
| CPU time | 32.13 seconds |
| Started | Oct 12 03:54:09 PM UTC 24 |
| Finished | Oct 12 03:54:42 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436218560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1436218560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.2153864681 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 292500091995 ps |
| CPU time | 466.38 seconds |
| Started | Oct 12 03:54:51 PM UTC 24 |
| Finished | Oct 12 04:02:43 PM UTC 24 |
| Peak memory | 196952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153864681 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.2153864681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.3132085785 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 445756315065 ps |
| CPU time | 239.4 seconds |
| Started | Oct 12 03:54:43 PM UTC 24 |
| Finished | Oct 12 03:58:47 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132085785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3132085785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.3142095681 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 16473775745 ps |
| CPU time | 53.84 seconds |
| Started | Oct 12 03:54:59 PM UTC 24 |
| Finished | Oct 12 03:55:55 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142095681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3142095681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1167738854 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 489173165245 ps |
| CPU time | 543.81 seconds |
| Started | Oct 12 03:55:22 PM UTC 24 |
| Finished | Oct 12 04:04:32 PM UTC 24 |
| Peak memory | 196768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167738854 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1167738854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.709162915 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 216604080621 ps |
| CPU time | 163.8 seconds |
| Started | Oct 12 03:14:36 PM UTC 24 |
| Finished | Oct 12 03:17:23 PM UTC 24 |
| Peak memory | 196740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709162915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.709162915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1777389025 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 85054741790 ps |
| CPU time | 92.39 seconds |
| Started | Oct 12 03:14:36 PM UTC 24 |
| Finished | Oct 12 03:16:11 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777389025 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1777389025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.1271338426 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 130404943647 ps |
| CPU time | 185.64 seconds |
| Started | Oct 12 03:14:40 PM UTC 24 |
| Finished | Oct 12 03:17:49 PM UTC 24 |
| Peak memory | 196760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271338426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1271338426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.3218229896 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 966619780171 ps |
| CPU time | 2108.54 seconds |
| Started | Oct 12 03:55:54 PM UTC 24 |
| Finished | Oct 12 04:31:24 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218229896 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3218229896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2219548449 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 79411846987 ps |
| CPU time | 425.28 seconds |
| Started | Oct 12 03:55:56 PM UTC 24 |
| Finished | Oct 12 04:03:07 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219548449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2219548449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.2555017567 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 426886080471 ps |
| CPU time | 165.59 seconds |
| Started | Oct 12 03:56:18 PM UTC 24 |
| Finished | Oct 12 03:59:06 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555017567 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2555017567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.452483634 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 176823278593 ps |
| CPU time | 683.07 seconds |
| Started | Oct 12 03:57:08 PM UTC 24 |
| Finished | Oct 12 04:08:39 PM UTC 24 |
| Peak memory | 200432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452483634 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.452483634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.2044039146 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1546093058264 ps |
| CPU time | 650.88 seconds |
| Started | Oct 12 03:57:46 PM UTC 24 |
| Finished | Oct 12 04:08:45 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044039146 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2044039146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.2331984924 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 453069805564 ps |
| CPU time | 571.6 seconds |
| Started | Oct 12 03:57:54 PM UTC 24 |
| Finished | Oct 12 04:07:33 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331984924 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2331984924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.3189217023 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 29649135577 ps |
| CPU time | 47.13 seconds |
| Started | Oct 12 03:58:49 PM UTC 24 |
| Finished | Oct 12 03:59:37 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189217023 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3189217023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.1753238410 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 224832319354 ps |
| CPU time | 394.98 seconds |
| Started | Oct 12 03:58:51 PM UTC 24 |
| Finished | Oct 12 04:05:31 PM UTC 24 |
| Peak memory | 196820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753238410 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1753238410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3340148566 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 736886917674 ps |
| CPU time | 706.21 seconds |
| Started | Oct 12 03:59:07 PM UTC 24 |
| Finished | Oct 12 04:11:01 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340148566 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3340148566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.3484939862 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 336020397033 ps |
| CPU time | 446.51 seconds |
| Started | Oct 12 03:59:23 PM UTC 24 |
| Finished | Oct 12 04:06:55 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484939862 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3484939862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.463391653 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 455097791086 ps |
| CPU time | 446.13 seconds |
| Started | Oct 12 03:14:53 PM UTC 24 |
| Finished | Oct 12 03:22:25 PM UTC 24 |
| Peak memory | 196672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463391653 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.463391653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.3465030806 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 158075113760 ps |
| CPU time | 249.06 seconds |
| Started | Oct 12 03:14:51 PM UTC 24 |
| Finished | Oct 12 03:19:03 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465030806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3465030806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.1147907651 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 685836639359 ps |
| CPU time | 349.02 seconds |
| Started | Oct 12 03:14:47 PM UTC 24 |
| Finished | Oct 12 03:20:40 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147907651 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1147907651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3245074518 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 47419657996 ps |
| CPU time | 565.86 seconds |
| Started | Oct 12 03:14:56 PM UTC 24 |
| Finished | Oct 12 03:24:28 PM UTC 24 |
| Peak memory | 200356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245074518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3245074518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all_with_rand_reset.931428206 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4776754624 ps |
| CPU time | 63.97 seconds |
| Started | Oct 12 03:14:58 PM UTC 24 |
| Finished | Oct 12 03:16:04 PM UTC 24 |
| Peak memory | 202940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=931428206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.931428206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.76648725 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 667920272533 ps |
| CPU time | 677.05 seconds |
| Started | Oct 12 03:59:39 PM UTC 24 |
| Finished | Oct 12 04:11:05 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76648725 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.76648725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1303767936 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 498846887532 ps |
| CPU time | 445.93 seconds |
| Started | Oct 12 03:59:59 PM UTC 24 |
| Finished | Oct 12 04:07:31 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303767936 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1303767936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.2807016929 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 72299202715 ps |
| CPU time | 159.21 seconds |
| Started | Oct 12 04:00:56 PM UTC 24 |
| Finished | Oct 12 04:03:37 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807016929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2807016929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2613292551 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 745573216360 ps |
| CPU time | 546.1 seconds |
| Started | Oct 12 04:01:48 PM UTC 24 |
| Finished | Oct 12 04:11:01 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613292551 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2613292551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.3216967028 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 245627871640 ps |
| CPU time | 1038.13 seconds |
| Started | Oct 12 04:02:45 PM UTC 24 |
| Finished | Oct 12 04:20:15 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216967028 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3216967028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.2474085701 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 309199708721 ps |
| CPU time | 262.97 seconds |
| Started | Oct 12 04:02:57 PM UTC 24 |
| Finished | Oct 12 04:07:23 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474085701 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2474085701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.2972406980 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 254174087069 ps |
| CPU time | 120.85 seconds |
| Started | Oct 12 04:03:09 PM UTC 24 |
| Finished | Oct 12 04:05:12 PM UTC 24 |
| Peak memory | 197020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972406980 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2972406980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.2355101277 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 41874433682 ps |
| CPU time | 327.94 seconds |
| Started | Oct 12 04:03:25 PM UTC 24 |
| Finished | Oct 12 04:08:57 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355101277 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2355101277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.3130605621 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 345208670789 ps |
| CPU time | 762 seconds |
| Started | Oct 12 03:15:23 PM UTC 24 |
| Finished | Oct 12 03:28:14 PM UTC 24 |
| Peak memory | 200556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130605621 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3130605621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.4250928709 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 199217941365 ps |
| CPU time | 144.6 seconds |
| Started | Oct 12 03:15:17 PM UTC 24 |
| Finished | Oct 12 03:17:44 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250928709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4250928709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.2814811412 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 66979351849 ps |
| CPU time | 103.05 seconds |
| Started | Oct 12 03:15:14 PM UTC 24 |
| Finished | Oct 12 03:16:59 PM UTC 24 |
| Peak memory | 196548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814811412 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2814811412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.964988722 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 201072104886 ps |
| CPU time | 148.78 seconds |
| Started | Oct 12 03:15:43 PM UTC 24 |
| Finished | Oct 12 03:18:15 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964988722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.964988722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1906295448 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 10741006146 ps |
| CPU time | 26.05 seconds |
| Started | Oct 12 04:03:39 PM UTC 24 |
| Finished | Oct 12 04:04:06 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906295448 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1906295448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2474135488 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 54407044067 ps |
| CPU time | 138.44 seconds |
| Started | Oct 12 04:03:59 PM UTC 24 |
| Finished | Oct 12 04:06:20 PM UTC 24 |
| Peak memory | 196728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474135488 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2474135488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.2286166767 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 389117446872 ps |
| CPU time | 318.21 seconds |
| Started | Oct 12 04:04:03 PM UTC 24 |
| Finished | Oct 12 04:09:26 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286166767 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2286166767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.3615651560 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13361510680 ps |
| CPU time | 19.26 seconds |
| Started | Oct 12 04:04:05 PM UTC 24 |
| Finished | Oct 12 04:04:26 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615651560 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3615651560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1105763085 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 106607094222 ps |
| CPU time | 228.66 seconds |
| Started | Oct 12 04:04:07 PM UTC 24 |
| Finished | Oct 12 04:08:00 PM UTC 24 |
| Peak memory | 196876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105763085 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1105763085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3981128899 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 608193755373 ps |
| CPU time | 767.67 seconds |
| Started | Oct 12 04:04:28 PM UTC 24 |
| Finished | Oct 12 04:17:24 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981128899 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3981128899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.844391311 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 514671309475 ps |
| CPU time | 215.48 seconds |
| Started | Oct 12 04:04:34 PM UTC 24 |
| Finished | Oct 12 04:08:12 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844391311 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.844391311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2172543427 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 199035110235 ps |
| CPU time | 282.69 seconds |
| Started | Oct 12 04:04:56 PM UTC 24 |
| Finished | Oct 12 04:09:42 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172543427 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2172543427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.713604172 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3579677346 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 04:05:14 PM UTC 24 |
| Finished | Oct 12 04:05:22 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713604172 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.713604172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.1309880522 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 177391381045 ps |
| CPU time | 172.55 seconds |
| Started | Oct 12 03:16:10 PM UTC 24 |
| Finished | Oct 12 03:19:05 PM UTC 24 |
| Peak memory | 196748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309880522 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.1309880522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.1176181871 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6315088074 ps |
| CPU time | 5.71 seconds |
| Started | Oct 12 03:16:08 PM UTC 24 |
| Finished | Oct 12 03:16:14 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176181871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1176181871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.1364584831 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1435335602193 ps |
| CPU time | 1783.01 seconds |
| Started | Oct 12 03:16:06 PM UTC 24 |
| Finished | Oct 12 03:46:08 PM UTC 24 |
| Peak memory | 200256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364584831 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1364584831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.2553508505 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9137288059 ps |
| CPU time | 15.25 seconds |
| Started | Oct 12 03:16:12 PM UTC 24 |
| Finished | Oct 12 03:16:28 PM UTC 24 |
| Peak memory | 196744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553508505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2553508505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.1097437809 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3124761985323 ps |
| CPU time | 1253.02 seconds |
| Started | Oct 12 03:16:16 PM UTC 24 |
| Finished | Oct 12 03:37:23 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097437809 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.1097437809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.3640679172 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 495550806135 ps |
| CPU time | 459.13 seconds |
| Started | Oct 12 04:05:32 PM UTC 24 |
| Finished | Oct 12 04:13:17 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640679172 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3640679172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3579284444 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 42916388942 ps |
| CPU time | 137.03 seconds |
| Started | Oct 12 04:05:58 PM UTC 24 |
| Finished | Oct 12 04:08:18 PM UTC 24 |
| Peak memory | 196892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579284444 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3579284444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.1773595421 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 559050786529 ps |
| CPU time | 618.11 seconds |
| Started | Oct 12 04:06:22 PM UTC 24 |
| Finished | Oct 12 04:16:48 PM UTC 24 |
| Peak memory | 200372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773595421 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1773595421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.4038158304 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 198378440010 ps |
| CPU time | 349.02 seconds |
| Started | Oct 12 04:06:27 PM UTC 24 |
| Finished | Oct 12 04:12:20 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038158304 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4038158304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.2778404387 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 136783129735 ps |
| CPU time | 210.01 seconds |
| Started | Oct 12 04:06:57 PM UTC 24 |
| Finished | Oct 12 04:10:30 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778404387 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2778404387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.3014176195 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 157284057401 ps |
| CPU time | 149.1 seconds |
| Started | Oct 12 04:07:25 PM UTC 24 |
| Finished | Oct 12 04:09:57 PM UTC 24 |
| Peak memory | 196700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014176195 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3014176195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.1160868879 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 51215157030 ps |
| CPU time | 46.46 seconds |
| Started | Oct 12 04:07:33 PM UTC 24 |
| Finished | Oct 12 04:08:21 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160868879 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1160868879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.235433325 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 59615018373 ps |
| CPU time | 1329.87 seconds |
| Started | Oct 12 04:07:35 PM UTC 24 |
| Finished | Oct 12 04:30:00 PM UTC 24 |
| Peak memory | 200576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235433325 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.235433325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.745308817 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 38546472604 ps |
| CPU time | 571.06 seconds |
| Started | Oct 12 04:07:35 PM UTC 24 |
| Finished | Oct 12 04:17:13 PM UTC 24 |
| Peak memory | 200576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745308817 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.745308817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.4044653790 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1803525338806 ps |
| CPU time | 1458.74 seconds |
| Started | Oct 12 03:16:33 PM UTC 24 |
| Finished | Oct 12 03:41:07 PM UTC 24 |
| Peak memory | 200556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044653790 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.4044653790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.1732757084 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 70156143359 ps |
| CPU time | 120.36 seconds |
| Started | Oct 12 03:16:30 PM UTC 24 |
| Finished | Oct 12 03:18:34 PM UTC 24 |
| Peak memory | 196824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732757084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1732757084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.704608337 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 22321010071 ps |
| CPU time | 45.35 seconds |
| Started | Oct 12 03:16:16 PM UTC 24 |
| Finished | Oct 12 03:17:03 PM UTC 24 |
| Peak memory | 196472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704608337 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.704608337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.4244245181 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 131118189125 ps |
| CPU time | 1000.24 seconds |
| Started | Oct 12 03:16:37 PM UTC 24 |
| Finished | Oct 12 03:33:28 PM UTC 24 |
| Peak memory | 200428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244245181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4244245181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.2183189301 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 425943602751 ps |
| CPU time | 406.42 seconds |
| Started | Oct 12 04:07:37 PM UTC 24 |
| Finished | Oct 12 04:14:28 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183189301 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2183189301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.1476753339 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 465197608380 ps |
| CPU time | 378.22 seconds |
| Started | Oct 12 04:08:01 PM UTC 24 |
| Finished | Oct 12 04:14:24 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476753339 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1476753339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.1624333959 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 11456964423 ps |
| CPU time | 6.18 seconds |
| Started | Oct 12 04:08:05 PM UTC 24 |
| Finished | Oct 12 04:08:13 PM UTC 24 |
| Peak memory | 196692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624333959 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1624333959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2444639084 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 62874842254 ps |
| CPU time | 112.15 seconds |
| Started | Oct 12 04:08:14 PM UTC 24 |
| Finished | Oct 12 04:10:08 PM UTC 24 |
| Peak memory | 196948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444639084 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2444639084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.3561339377 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 186582630658 ps |
| CPU time | 1817.15 seconds |
| Started | Oct 12 04:08:14 PM UTC 24 |
| Finished | Oct 12 04:38:51 PM UTC 24 |
| Peak memory | 200448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561339377 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3561339377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.790956035 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 160432482515 ps |
| CPU time | 308.38 seconds |
| Started | Oct 12 04:08:20 PM UTC 24 |
| Finished | Oct 12 04:13:32 PM UTC 24 |
| Peak memory | 197012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790956035 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.790956035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.240273511 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 209721248777 ps |
| CPU time | 341.68 seconds |
| Started | Oct 12 04:08:22 PM UTC 24 |
| Finished | Oct 12 04:14:08 PM UTC 24 |
| Peak memory | 196764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240273511 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.240273511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.3571731999 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 393362274857 ps |
| CPU time | 349.34 seconds |
| Started | Oct 12 04:08:40 PM UTC 24 |
| Finished | Oct 12 04:14:34 PM UTC 24 |
| Peak memory | 196688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571731999 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3571731999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.3527300265 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 257617994075 ps |
| CPU time | 498.64 seconds |
| Started | Oct 12 04:08:46 PM UTC 24 |
| Finished | Oct 12 04:17:11 PM UTC 24 |
| Peak memory | 200376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527300265 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3527300265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.168738154 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 319070851072 ps |
| CPU time | 1140.59 seconds |
| Started | Oct 12 04:08:58 PM UTC 24 |
| Finished | Oct 12 04:28:11 PM UTC 24 |
| Peak memory | 200380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168738154 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.168738154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/rv_timer-sim-vcs/99.rv_timer_random/latest |
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