Line Coverage for Module :
rv_timer_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 75 | 75 | 100.00 |
ALWAYS | 71 | 4 | 4 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 267 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
ALWAYS | 473 | 11 | 11 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 490 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
CONT_ASSIGN | 507 | 1 | 1 | 100.00 |
CONT_ASSIGN | 509 | 1 | 1 | 100.00 |
CONT_ASSIGN | 510 | 1 | 1 | 100.00 |
CONT_ASSIGN | 512 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 515 | 1 | 1 | 100.00 |
CONT_ASSIGN | 516 | 1 | 1 | 100.00 |
CONT_ASSIGN | 518 | 1 | 1 | 100.00 |
CONT_ASSIGN | 519 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 524 | 1 | 1 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 527 | 1 | 1 | 100.00 |
CONT_ASSIGN | 529 | 1 | 1 | 100.00 |
CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
CONT_ASSIGN | 532 | 1 | 1 | 100.00 |
CONT_ASSIGN | 533 | 1 | 1 | 100.00 |
CONT_ASSIGN | 535 | 1 | 1 | 100.00 |
ALWAYS | 539 | 11 | 11 | 100.00 |
ALWAYS | 554 | 13 | 13 | 100.00 |
CONT_ASSIGN | 608 | 0 | 0 | |
CONT_ASSIGN | 616 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
|
|
|
MISSING_ELSE |
80 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
162 |
1 |
1 |
176 |
1 |
1 |
267 |
1 |
1 |
281 |
1 |
1 |
428 |
1 |
1 |
467 |
1 |
1 |
473 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
476 |
1 |
1 |
477 |
1 |
1 |
478 |
1 |
1 |
479 |
1 |
1 |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
486 |
1 |
1 |
490 |
1 |
1 |
504 |
1 |
1 |
506 |
1 |
1 |
507 |
1 |
1 |
509 |
1 |
1 |
510 |
1 |
1 |
512 |
1 |
1 |
513 |
1 |
1 |
515 |
1 |
1 |
516 |
1 |
1 |
518 |
1 |
1 |
519 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
524 |
1 |
1 |
526 |
1 |
1 |
527 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
532 |
1 |
1 |
533 |
1 |
1 |
535 |
1 |
1 |
539 |
1 |
1 |
540 |
1 |
1 |
541 |
1 |
1 |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
545 |
1 |
1 |
546 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
549 |
1 |
1 |
554 |
1 |
1 |
555 |
1 |
1 |
557 |
1 |
1 |
561 |
1 |
1 |
565 |
1 |
1 |
569 |
1 |
1 |
573 |
1 |
1 |
577 |
1 |
1 |
578 |
1 |
1 |
582 |
1 |
1 |
586 |
1 |
1 |
590 |
1 |
1 |
594 |
1 |
1 |
608 |
|
unreachable |
616 |
1 |
1 |
617 |
1 |
1 |
Cond Coverage for Module :
rv_timer_reg_top
| Total | Covered | Percent |
Conditions | 125 | 125 | 100.00 |
Logical | 125 | 125 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T1,T2,T3 |
LINE 73
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T17,T18,T19 |
1 | 0 | Covered | T14,T31,T32 |
LINE 80
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T17,T18,T19 |
0 | 1 | 0 | Covered | T14,T31,T32 |
1 | 0 | 0 | Covered | T14,T31,T32 |
LINE 122
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T14,T31,T32 |
0 | 1 | 0 | Covered | T11,T12,T13 |
1 | 0 | 0 | Covered | T11,T12,T13 |
LINE 122
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T11,T12,T13 |
LINE 474
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_ALERT_TEST_OFFSET)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 475
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CTRL_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 476
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_ENABLE0_OFFSET)
------------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 477
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_STATE0_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 478
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_INTR_TEST0_OFFSET)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 479
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_CFG0_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 480
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_LOWER0_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 481
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_TIMER_V_UPPER0_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_LOWER0_0_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 483
EXPRESSION (reg_addr == rv_timer_reg_pkg::RV_TIMER_COMPARE_UPPER0_0_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 486
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 486
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 490
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))))
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T11,T12,T13 |
LINE 490
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))))
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T4,T7,T8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T4,T7,T8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T1,T4,T5 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T1,T4,T5 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T4,T7,T8 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T6,T7 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T6,T7 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T7,T8 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T7,T8 |
LINE 490
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T7,T8 |
1 | 1 | Covered | T4,T7,T8 |
LINE 490
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T7,T8 |
LINE 490
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T4,T6,T7 |
LINE 490
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 490
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 490
SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T7,T8 |
LINE 490
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 490
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 490
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T7,T8 |
LINE 490
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T7,T8 |
LINE 504
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T7,T8 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T33,T14,T15 |
LINE 507
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 510
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 513
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T3,T5,T6 |
LINE 516
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T7 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T6,T34,T11 |
LINE 519
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 524
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 527
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 530
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 533
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T11,T12,T13 |
1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
rv_timer_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
TERNARY |
486 |
2 |
2 |
100.00 |
IF |
71 |
3 |
3 |
100.00 |
CASE |
555 |
11 |
11 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 486 ((reg_re || reg_we)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 71 if ((!rst_ni))
-2-: 73 if ((intg_err || reg_we_err))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T14,T31,T32 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 555 case (1'b1)
Branches:
-1- | Status | Tests |
addr_hit[0] |
Covered |
T1,T2,T3 |
addr_hit[1] |
Covered |
T1,T2,T3 |
addr_hit[2] |
Covered |
T1,T2,T3 |
addr_hit[3] |
Covered |
T1,T2,T3 |
addr_hit[4] |
Covered |
T1,T2,T3 |
addr_hit[5] |
Covered |
T1,T2,T3 |
addr_hit[6] |
Covered |
T1,T2,T3 |
addr_hit[7] |
Covered |
T1,T2,T3 |
addr_hit[8] |
Covered |
T1,T2,T3 |
addr_hit[9] |
Covered |
T1,T2,T3 |
default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_timer_reg_top
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
en2addrHit |
2147483647 |
140237750 |
0 |
0 |
reAfterRv |
2147483647 |
140237735 |
0 |
0 |
rePulse |
2147483647 |
139911170 |
0 |
0 |
wePulse |
2147483647 |
326565 |
0 |
0 |
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
140237750 |
0 |
0 |
T1 |
877882 |
5679 |
0 |
0 |
T2 |
184141 |
451284 |
0 |
0 |
T3 |
453649 |
31231 |
0 |
0 |
T4 |
137916 |
17906 |
0 |
0 |
T5 |
574077 |
11416 |
0 |
0 |
T6 |
790061 |
343365 |
0 |
0 |
T7 |
122342 |
8358 |
0 |
0 |
T8 |
746452 |
21864 |
0 |
0 |
T9 |
499181 |
49391 |
0 |
0 |
T10 |
618139 |
287286 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
140237735 |
0 |
0 |
T1 |
877882 |
5679 |
0 |
0 |
T2 |
184141 |
451284 |
0 |
0 |
T3 |
453649 |
31231 |
0 |
0 |
T4 |
137916 |
17906 |
0 |
0 |
T5 |
574077 |
11416 |
0 |
0 |
T6 |
790061 |
343365 |
0 |
0 |
T7 |
122342 |
8358 |
0 |
0 |
T8 |
746452 |
21864 |
0 |
0 |
T9 |
499181 |
49391 |
0 |
0 |
T10 |
618139 |
287286 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
139911170 |
0 |
0 |
T1 |
877882 |
5653 |
0 |
0 |
T2 |
184141 |
451264 |
0 |
0 |
T3 |
453649 |
31172 |
0 |
0 |
T4 |
137916 |
17872 |
0 |
0 |
T5 |
574077 |
11387 |
0 |
0 |
T6 |
790061 |
343271 |
0 |
0 |
T7 |
122342 |
8338 |
0 |
0 |
T8 |
746452 |
21833 |
0 |
0 |
T9 |
499181 |
49381 |
0 |
0 |
T10 |
618139 |
287257 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
326565 |
0 |
0 |
T1 |
877882 |
26 |
0 |
0 |
T2 |
184141 |
20 |
0 |
0 |
T3 |
453649 |
59 |
0 |
0 |
T4 |
137916 |
34 |
0 |
0 |
T5 |
574077 |
29 |
0 |
0 |
T6 |
790061 |
94 |
0 |
0 |
T7 |
122342 |
20 |
0 |
0 |
T8 |
746452 |
31 |
0 |
0 |
T9 |
499181 |
10 |
0 |
0 |
T10 |
618139 |
29 |
0 |
0 |