Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 95.83 100.00 83.33 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 100.00 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.62 99.36 98.73 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_harts[0].u_core 100.00 100.00 100.00 100.00
gen_harts[0].u_intr_hw 100.00 100.00 100.00 100.00 100.00
rv_timer_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 99.71 99.24 99.29 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_timer
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN13211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
66 1 1
68 1 1
69 1 1
70 1 1
71 1 1
72 1 1
73 1 1
74 1 1
132 1 1

Cond Coverage for Module : rv_timer
TotalCoveredPercent
Conditions121083.33
Logical121083.33
Non-Logical00
Event00

 LINE       66
 EXPRESSION (reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe)
             -------------1------------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       73
 EXPRESSION (intr_timer_state_de | mtimecmp_update[0][0])
             ---------1---------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4 

 LINE       74
 EXPRESSION (intr_timer_state_d & ((~mtimecmp_update[0][0])))
             ---------1--------   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T5
11CoveredT2,T3,T4 

 LINE       132
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered
Toggle Coverage for Module : rv_timer
TotalCoveredPercent
Totals 27 27 100.00
Total Bits 334 334 100.00
Total Bits 0->1 167 167 100.00
Total Bits 1->0 167 167 100.00

Ports 27 27 100.00
Port Bits 334 334 100.00
Port Bits 0->1 167 167 100.00
Port Bits 1->0 167 167 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T8,T9,T10 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T5,T8 Yes T2,T5,T8 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T5 Yes T1,T2,T5 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T5 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
intr_timer_expired_hart0_timer0_o Yes Yes T2,T4,T5 Yes T2,T4,T5 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : rv_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 2147483647 2147483647 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 100 0 0
IntrTimerExpiredHart0Timer0Known 2147483647 2147483647 0 0
TlOAReadyKnown 2147483647 2147483647 0 0
TlODValidKnown 2147483647 2147483647 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 126492 126491 0 0
T2 139698 139698 0 0
T3 356494 356485 0 0
T4 992445 992439 0 0
T5 167553 167552 0 0
T6 535070 535004 0 0
T7 844123 844115 0 0
T8 494265 494261 0 0
T9 165827 165825 0 0
T10 277444 277419 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 100 0 0
T14 7713 30 0 0
T15 0 10 0 0
T16 0 20 0 0
T17 0 20 0 0
T18 0 20 0 0
T19 210427 0 0 0
T20 116639 0 0 0
T21 578829 0 0 0
T22 193689 0 0 0
T23 362318 0 0 0
T24 441514 0 0 0
T25 782312 0 0 0
T26 108319 0 0 0
T27 100288 0 0 0

IntrTimerExpiredHart0Timer0Known
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 126492 126491 0 0
T2 139698 139698 0 0
T3 356494 356485 0 0
T4 992445 992439 0 0
T5 167553 167552 0 0
T6 535070 535004 0 0
T7 844123 844115 0 0
T8 494265 494261 0 0
T9 165827 165825 0 0
T10 277444 277419 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 126492 126491 0 0
T2 139698 139698 0 0
T3 356494 356485 0 0
T4 992445 992439 0 0
T5 167553 167552 0 0
T6 535070 535004 0 0
T7 844123 844115 0 0
T8 494265 494261 0 0
T9 165827 165825 0 0
T10 277444 277419 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 126492 126491 0 0
T2 139698 139698 0 0
T3 356494 356485 0 0
T4 992445 992439 0 0
T5 167553 167552 0 0
T6 535070 535004 0 0
T7 844123 844115 0 0
T8 494265 494261 0 0
T9 165827 165825 0 0
T10 277444 277419 0 0

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