SPI_DEVICE Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_smoke 1.430s 19.925us 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.410s 121.673us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.800s 99.804us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 40.740s 5.972ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 27.440s 1.368ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.390s 88.034us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.800s 99.804us 20 20 100.00
spi_device_csr_aliasing 27.440s 1.368ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 14.620s 2.718ms 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 6.880s 645.333us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 base_random_seq spi_device_txrx 21.531m 222.444ms 50 50 100.00
V2 fifo_full spi_device_fifo_full 47.516m 227.297ms 48 50 96.00
V2 fifo_underflow_overflow spi_device_fifo_underflow_overflow 28.705m 1.078s 46 50 92.00
V2 dummy_sck_and_dummy_csb spi_device_dummy_item_extra_dly 33.753m 360.461ms 50 50 100.00
V2 extra_delay_on_spi spi_device_dummy_item_extra_dly 33.753m 360.461ms 50 50 100.00
V2 tx_async_fifo_reset spi_device_tx_async_fifo_reset 0.830s 26.112us 50 50 100.00
V2 rx_async_fifo_reset spi_device_rx_async_fifo_reset 0.950s 38.227us 48 50 96.00
V2 interrupts spi_device_intr 1.744m 26.633ms 49 50 98.00
V2 abort spi_device_abort 0.790s 52.580us 50 50 100.00
V2 byte_transfer_on_spi spi_device_byte_transfer 3.480s 836.148us 50 50 100.00
V2 rx_timeout spi_device_rx_timeout 7.650s 4.203ms 50 50 100.00
V2 bit_transfer_on_spi spi_device_bit_transfer 3.270s 338.629us 50 50 100.00
V2 extreme_fifo_setting spi_device_extreme_fifo_size 55.970m 576.009ms 50 50 100.00
V2 perf spi_device_perf 53.605m 56.083ms 50 50 100.00
V2 csb_read spi_device_csb_read 0.880s 16.130us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.160s 36.598us 16 20 80.00
V2 mem_cfg spi_device_ram_cfg 0.750s 33.430us 20 20 100.00
V2 tpm_read spi_device_tpm_rw 9.670s 992.798us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 9.670s 992.798us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 31.540s 9.166ms 50 50 100.00
spi_device_tpm_sts_read 1.410s 204.445us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 3.495m 48.530ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 36.790s 14.847ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 40.870s 34.386ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 40.870s 34.386ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 15.220s 4.408ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 15.220s 4.408ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 15.220s 4.408ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 15.220s 4.408ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 1.212m 23.914ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 49.470s 18.481ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 49.470s 18.481ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 49.470s 18.481ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 47.240s 46.608ms 48 50 96.00
spi_device_read_buffer_direct 8.550s 2.047ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 49.470s 18.481ms 50 50 100.00
spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.150m 383.003ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 22.950s 28.071ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 22.950s 28.071ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 9.540m 82.449ms 48 50 96.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 11.136m 171.179ms 46 50 92.00
V2 stress_all spi_device_stress_all 1.734h 495.347ms 14 50 28.00
V2 alert_test spi_device_alert_test 0.800s 41.577us 50 50 100.00
V2 intr_test spi_device_intr_test 0.830s 34.396us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 6.080s 554.875us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 6.080s 554.875us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.410s 121.673us 5 5 100.00
spi_device_csr_rw 2.800s 99.804us 20 20 100.00
spi_device_csr_aliasing 27.440s 1.368ms 5 5 100.00
spi_device_same_csr_outstanding 4.770s 886.302us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.410s 121.673us 5 5 100.00
spi_device_csr_rw 2.800s 99.804us 20 20 100.00
spi_device_csr_aliasing 27.440s 1.368ms 5 5 100.00
spi_device_same_csr_outstanding 4.770s 886.302us 20 20 100.00
V2 TOTAL 1623 1680 96.61
V2S tl_intg_err spi_device_sec_cm 1.130s 79.563us 5 5 100.00
spi_device_tl_intg_err 22.540s 1.142ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 22.540s 1.142ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1763 1820 96.87

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 36 36 27 75.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.92 99.01 96.23 98.63 92.06 97.95 96.16 98.40

Failure Buckets

Past Results