e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_device_smoke | 1.430s | 19.925us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.410s | 121.673us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_device_csr_rw | 2.800s | 99.804us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_device_csr_bit_bash | 40.740s | 5.972ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_device_csr_aliasing | 27.440s | 1.368ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 2.390s | 88.034us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.800s | 99.804us | 20 | 20 | 100.00 |
spi_device_csr_aliasing | 27.440s | 1.368ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_device_mem_walk | 14.620s | 2.718ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_device_mem_partial_access | 6.880s | 645.333us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | base_random_seq | spi_device_txrx | 21.531m | 222.444ms | 50 | 50 | 100.00 |
V2 | fifo_full | spi_device_fifo_full | 47.516m | 227.297ms | 48 | 50 | 96.00 |
V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 28.705m | 1.078s | 46 | 50 | 92.00 |
V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 33.753m | 360.461ms | 50 | 50 | 100.00 |
V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 33.753m | 360.461ms | 50 | 50 | 100.00 |
V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0.830s | 26.112us | 50 | 50 | 100.00 |
V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0.950s | 38.227us | 48 | 50 | 96.00 |
V2 | interrupts | spi_device_intr | 1.744m | 26.633ms | 49 | 50 | 98.00 |
V2 | abort | spi_device_abort | 0.790s | 52.580us | 50 | 50 | 100.00 |
V2 | byte_transfer_on_spi | spi_device_byte_transfer | 3.480s | 836.148us | 50 | 50 | 100.00 |
V2 | rx_timeout | spi_device_rx_timeout | 7.650s | 4.203ms | 50 | 50 | 100.00 |
V2 | bit_transfer_on_spi | spi_device_bit_transfer | 3.270s | 338.629us | 50 | 50 | 100.00 |
V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 55.970m | 576.009ms | 50 | 50 | 100.00 |
V2 | perf | spi_device_perf | 53.605m | 56.083ms | 50 | 50 | 100.00 |
V2 | csb_read | spi_device_csb_read | 0.880s | 16.130us | 50 | 50 | 100.00 |
V2 | mem_parity | spi_device_mem_parity | 1.160s | 36.598us | 16 | 20 | 80.00 |
V2 | mem_cfg | spi_device_ram_cfg | 0.750s | 33.430us | 20 | 20 | 100.00 |
V2 | tpm_read | spi_device_tpm_rw | 9.670s | 992.798us | 50 | 50 | 100.00 |
V2 | tpm_write | spi_device_tpm_rw | 9.670s | 992.798us | 50 | 50 | 100.00 |
V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 31.540s | 9.166ms | 50 | 50 | 100.00 |
spi_device_tpm_sts_read | 1.410s | 204.445us | 50 | 50 | 100.00 | ||
V2 | tpm_fully_random_case | spi_device_tpm_all | 3.495m | 48.530ms | 50 | 50 | 100.00 |
V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 36.790s | 14.847ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 40.870s | 34.386ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 40.870s | 34.386ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | cmd_info_slots | spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 |
V2 | cmd_read_status | spi_device_intercept | 15.220s | 4.408ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_jedec | spi_device_intercept | 15.220s | 4.408ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_sfdp | spi_device_intercept | 15.220s | 4.408ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | cmd_fast_read | spi_device_intercept | 15.220s | 4.408ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | flash_cmd_upload | spi_device_upload | 1.212m | 23.914ms | 50 | 50 | 100.00 |
V2 | mailbox_command | spi_device_mailbox | 49.470s | 18.481ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_outside_command | spi_device_mailbox | 49.470s | 18.481ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_inside_command | spi_device_mailbox | 49.470s | 18.481ms | 50 | 50 | 100.00 |
V2 | cmd_read_buffer | spi_device_flash_mode | 47.240s | 46.608ms | 48 | 50 | 96.00 |
spi_device_read_buffer_direct | 8.550s | 2.047ms | 50 | 50 | 100.00 | ||
V2 | cmd_dummy_cycle | spi_device_mailbox | 49.470s | 18.481ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 | ||
V2 | quad_spi | spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 |
V2 | dual_spi | spi_device_flash_all | 7.150m | 383.003ms | 50 | 50 | 100.00 |
V2 | 4b_3b_feature | spi_device_cfg_cmd | 22.950s | 28.071ms | 50 | 50 | 100.00 |
V2 | write_enable_disable | spi_device_cfg_cmd | 22.950s | 28.071ms | 50 | 50 | 100.00 |
V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 9.540m | 82.449ms | 48 | 50 | 96.00 |
V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 11.136m | 171.179ms | 46 | 50 | 92.00 |
V2 | stress_all | spi_device_stress_all | 1.734h | 495.347ms | 14 | 50 | 28.00 |
V2 | alert_test | spi_device_alert_test | 0.800s | 41.577us | 50 | 50 | 100.00 |
V2 | intr_test | spi_device_intr_test | 0.830s | 34.396us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_device_tl_errors | 6.080s | 554.875us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_device_tl_errors | 6.080s | 554.875us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.410s | 121.673us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.800s | 99.804us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 27.440s | 1.368ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.770s | 886.302us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.410s | 121.673us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.800s | 99.804us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 27.440s | 1.368ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.770s | 886.302us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1623 | 1680 | 96.61 | |||
V2S | tl_intg_err | spi_device_sec_cm | 1.130s | 79.563us | 5 | 5 | 100.00 |
spi_device_tl_intg_err | 22.540s | 1.142ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.540s | 1.142ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1763 | 1820 | 96.87 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 36 | 36 | 27 | 75.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 0 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.92 | 99.01 | 96.23 | 98.63 | 92.06 | 97.95 | 96.16 | 98.40 |
UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch
has 31 failures:
0.spi_device_stress_all.1711220024
Line 242, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log
UVM_ERROR @ 18296726712 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x93 [10010011] vs 0x1 [1]) addr 0x2da07308 read out mismatch
UVM_ERROR @ 18296726712 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x50 [1010000] vs 0x3b [111011]) addr 0x2da07309 read out mismatch
UVM_ERROR @ 18296726712 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xf5 [11110101] vs 0x7c [1111100]) addr 0x2da0730a read out mismatch
UVM_ERROR @ 18296726712 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xcb [11001011] vs 0x93 [10010011]) addr 0x2da0730b read out mismatch
UVM_ERROR @ 18298835395 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xcd [11001101] vs 0xb8 [10111000]) addr 0x2da0730c read out mismatch
3.spi_device_stress_all.3334718004
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log
UVM_ERROR @ 514472185860 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x33 [110011] vs 0x6d [1101101]) addr 0xe9359220 read out mismatch
UVM_ERROR @ 514472185860 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x9b [10011011] vs 0x2c [101100]) addr 0xe9359221 read out mismatch
UVM_ERROR @ 514472185860 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x90 [10010000] vs 0x3d [111101]) addr 0xe9359222 read out mismatch
UVM_ERROR @ 514472185860 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xc4 [11000100] vs 0x8f [10001111]) addr 0xe9359223 read out mismatch
UVM_ERROR @ 514485685860 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xbb [10111011] vs 0xc9 [11001001]) addr 0xe9359224 read out mismatch
... and 29 more failures.
UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
has 7 failures:
Test spi_device_stress_all has 2 failures.
9.spi_device_stress_all.1956588872
Line 223, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_stress_all/latest/run.log
UVM_WARNING @ 47394484689 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 47394484689 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 47394484689 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 47394484689 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 47394484689 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
10.spi_device_stress_all.78208305
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log
UVM_WARNING @ 491540136334 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 491540136334 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 491540136334 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 491540136334 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 491540136334 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
Test spi_device_flash_and_tpm_min_idle has 4 failures.
17.spi_device_flash_and_tpm_min_idle.3640066364
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_WARNING @ 2314224694 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 2314224694 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 2314224694 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 2314224694 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 2314224694 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
25.spi_device_flash_and_tpm_min_idle.1291606753
Line 234, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_WARNING @ 114733835854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 114733835854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 114733835854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 114733835854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 114733835854 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
... and 2 more failures.
Test spi_device_flash_and_tpm has 1 failures.
31.spi_device_flash_and_tpm.559907521
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_and_tpm/latest/run.log
UVM_WARNING @ 1225688827 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1225688827 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1225688827 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1225688827 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_WARNING @ 1225688827 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
UVM_ERROR (cip_base_vseq.sv:245) [spi_device_mem_parity_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
has 4 failures:
8.spi_device_mem_parity.756386112
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 4559087 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xbc read out mismatch
UVM_ERROR @ 4559087 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x000000bc
UVM_ERROR @ 4725755 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xbc read out mismatch
UVM_ERROR @ 4725755 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x000000bc
UVM_ERROR @ 4892423 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (28672 [0x7000] vs 4294967295 [0xffffffff]) addr 0xbc read out mismatch
11.spi_device_mem_parity.2664937910
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 862147 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x68 read out mismatch
UVM_ERROR @ 862147 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000068
UVM_ERROR @ 903815 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x68 read out mismatch
UVM_ERROR @ 903815 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000068
UVM_ERROR @ 945483 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x68 read out mismatch
... and 2 more failures.
Offending '(!dst_pulse_o)'
has 3 failures:
36.spi_device_fifo_underflow_overflow.2079402735
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 1396159143 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 25279987111ps failed at 25280024148ps
Offending '(!dst_pulse_o)'
UVM_ERROR @ 25280024148 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
37.spi_device_fifo_underflow_overflow.568814250
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 1685102346 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 2124080565 ps: (spi_device_txrx_vseq.sv:109) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] starting sequence 2/2
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 3083732415ps failed at 3083745236ps
Offending '(!dst_pulse_o)'
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1372) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*])
has 2 failures:
7.spi_device_rx_async_fifo_reset.902521694
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 95763433 ps: (spi_device_scoreboard.sv:1372) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 95763433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.spi_device_rx_async_fifo_reset.2636809520
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 38227468 ps: (spi_device_scoreboard.sv:1372) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 38227468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
21.spi_device_fifo_full.2648983278
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_fifo_full/latest/run.log
Job ID: smart:5d0563c0-f327-434c-8aaf-aa48fcbc2c8b
34.spi_device_fifo_full.1285244722
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_fifo_full/latest/run.log
Job ID: smart:86dbd9b3-4246-437a-a97c-a54b9a8c637a
UVM_FATAL (spi_device_scoreboard.sv:880) [scoreboard] timeout occurred!
has 1 failures:
2.spi_device_flash_mode.472914447
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 62411571143 ps: (spi_device_scoreboard.sv:880) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 62411571143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: *
has 1 failures:
4.spi_device_intr.59010644
Line 288, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_intr/latest/run.log
UVM_ERROR @ 17535026809 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_INFO @ 17586268032 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing TxFifoUnderflow
UVM_INFO @ 17589007703 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing TxFifoUnderflow
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.intr_state reset value: *
has 1 failures:
5.spi_device_stress_all.3448692438
Line 301, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_stress_all/latest/run.log
UVM_ERROR @ 5747430849 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 5748270849 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
UVM_ERROR @ 5748520139 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
UVM_ERROR @ 5748540849 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 5748620849 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0
UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp *
has 1 failures:
6.spi_device_flash_and_tpm.367205061
Line 230, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 7287449706 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
UVM_INFO @ 7687069296 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/11
UVM_INFO @ 7845796998 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/19
UVM_INFO @ 8259410020 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/11
UVM_INFO @ 8567362954 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/19
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
9.spi_device_fifo_underflow_overflow.2276905695
Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_fifo_underflow_overflow/latest/run.log
UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes::
has 1 failures:
26.spi_device_stress_all.3956912185
Line 289, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_stress_all/latest/run.log
UVM_ERROR @ 105014967550 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1096 [0x448]) get_sram_space_bytes::
UVM_ERROR @ 105016085225 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3418287030 [0xcbbeebb6] vs 2490329042 [0x946f67d2]) Compare SPI RX data, addr: 0x3dc
UVM_ERROR @ 105016320525 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2991721493 [0xb2520c15] vs 2984234333 [0xb1dfcd5d]) Compare SPI RX data, addr: 0x3e0
UVM_ERROR @ 105130170430 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4010168871 [0xef065227] vs 607369527 [0x2433b937]) Compare SPI RX data, addr: 0x3e4
UVM_ERROR @ 105130299845 ps: (spi_device_scoreboard.sv:971) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3822299673 [0xe3d3aa19] vs 3868285962 [0xe6915c0a]) Compare SPI RX data, addr: 0x3e8
UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp *
has 1 failures:
32.spi_device_flash_mode.2674754444
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/32.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 250668091 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_INFO @ 380349164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_device_base_vseq.sv:395) [spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail
has 1 failures:
41.spi_device_stress_all.3815049423
Line 229, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_stress_all/latest/run.log
UVM_FATAL @ 523507344905 ps: (spi_device_base_vseq.sv:395) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_tx_avail_bytes::SramSpaceAvail
UVM_INFO @ 523507344905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---