SPI_DEVICE Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.330s	75.820us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	377.326us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.850s	404.198us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.900s	12.424ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	27.280s	4.043ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.990s	54.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.850s	404.198us	20	20	100.00
		spi_device_csr_aliasing	27.280s	4.043ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.560s	201.820us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.990s	503.805us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	19.982m	78.604ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	46.990m	50.415ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	25.285m	1.500s	44	50	88.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	58.124m	605.512ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	58.124m	605.512ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.810s	55.371us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.950s	71.664us	49	50	98.00
V2	interrupts	spi_device_intr	2.190m	112.281ms	49	50	98.00
V2	abort	spi_device_abort	0.880s	17.891us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.550s	858.270us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	6.620s	4.661ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.230s	4.533ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	59.020m	66.268ms	49	50	98.00
V2	perf	spi_device_perf	47.586m	66.159ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.850s	27.259us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	31.454us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	21.042us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.490s	428.721us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.490s	428.721us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.900s	51.962ms	50	50	100.00
		spi_device_tpm_sts_read	1.370s	287.660us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.881m	15.963ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.320s	6.275ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.127m	49.147ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.127m	49.147ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	cmd_read_status	spi_device_intercept	14.750s	41.454ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	14.750s	41.454ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.750s	41.454ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	14.750s	41.454ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	54.610s	15.798ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	56.750s	20.329ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	56.750s	20.329ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	56.750s	20.329ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.430s	11.536ms	50	50	100.00
		spi_device_read_buffer_direct	7.830s	2.137ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	56.750s	20.329ms	50	50	100.00
		spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.426m	1.483s	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.550s	4.985ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.550s	4.985ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.882m	1.307s	47	50	94.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.560m	167.879ms	48	50	96.00
V2	stress_all	spi_device_stress_all	1.549h	314.209ms	46	50	92.00
V2	alert_test	spi_device_alert_test	0.810s	105.184us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	48.011us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.990s	249.657us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.990s	249.657us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	377.326us	5	5	100.00
		spi_device_csr_rw	2.850s	404.198us	20	20	100.00
		spi_device_csr_aliasing	27.280s	4.043ms	5	5	100.00
		spi_device_same_csr_outstanding	4.840s	474.652us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	377.326us	5	5	100.00
		spi_device_csr_rw	2.850s	404.198us	20	20	100.00
		spi_device_csr_aliasing	27.280s	4.043ms	5	5	100.00
		spi_device_same_csr_outstanding	4.840s	474.652us	20	20	100.00
V2		TOTAL			1662	1680	98.93
V2S	tl_intg_err	spi_device_sec_cm	1.800s	1.983ms	5	5	100.00
		spi_device_tl_intg_err	23.830s	3.337ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.830s	3.337ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1802	1820	99.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	29	80.56
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.99	99.02	96.23	98.63	92.06	97.97	96.45	98.59

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 5 failures:

Test spi_device_flash_and_tpm has 3 failures.

6.spi_device_flash_and_tpm.2817078212
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 3663273919 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3663273919 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3663273919 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3663273919 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3663273919 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

11.spi_device_flash_and_tpm.1751885857
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 3270578562 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3270578562 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3270578562 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3270578562 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3270578562 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

... and 1 more failures.

Test spi_device_flash_and_tpm_min_idle has 1 failures.

29.spi_device_flash_and_tpm_min_idle.3484749995
Line 237, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 40067600641 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 40067600641 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 40067600641 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 40067600641 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 40067600641 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_stress_all has 1 failures.

43.spi_device_stress_all.2666563894
Line 280, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 60149468386 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 60149468386 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 60149468386 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 60149468386 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 60149468386 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Offending '(!dst_pulse_o)' has 4 failures:

Test spi_device_fifo_underflow_overflow has 4 failures.

24.spi_device_fifo_underflow_overflow.726944490
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 677439164 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 1260401564ps failed at 1260412202ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 1260412202 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

27.spi_device_fifo_underflow_overflow.1637261165
Line 222, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 14940095067 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  Starting assertion attempts at time 32508043142ps: level = 0 arg = tb.dut.u_txf_underflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:455))
  Starting assertion attempts at time 32508043142ps: level = 0 arg = tb.dut.u_txf_underflow.DstPulseCheck_A (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:456))
  Starting assertion attempts at time 32508043142ps: level = 0 arg = tb.dut.u_rxf_overflow.SrcPulseCheck_M (from inst vcs_paramclassrepository (../src/lowrisc_dv_spi_device_env_0.1/seq_lib/spi_device_base_vseq.sv:457))

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_fifo_underflow_overflow has 2 failures.
  - 6.spi_device_fifo_underflow_overflow.1250219468
    Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.spi_device_fifo_underflow_overflow.4051136165
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test spi_device_extreme_fifo_size has 1 failures.
  - 7.spi_device_extreme_fifo_size.3138248151
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_extreme_fifo_size/latest/run.log
```
  Job ID: smart:6312d147-ef49-4b8f-935a-f88d6c7bbbfa
```
- Test spi_device_stress_all has 1 failures.
  - 47.spi_device_stress_all.3674468750
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_stress_all/latest/run.log
```
  Job ID: smart:f9d4fb0b-4e29-448d-ad88-21ceddb4c784
```

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

4.spi_device_stress_all.790865756
Line 232, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 102672366816 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 136 [0x88]) get_sram_space_bytes::
  UVM_ERROR @ 102817367976 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (56 [0x38] vs 136 [0x88]) get_sram_filled_bytes
  UVM_ERROR @ 102818387592 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (12 [0xc] vs 56 [0x38]) get_sram_space_bytes::
  UVM_ERROR @ 102904705364 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3905864747 [0xe8cec42b] vs 3430119806 [0xcc73797e]) Compare SPI TX data
  UVM_ERROR @ 102904705364 ps: (spi_device_env_pkg.sv:189) [uvm_test_top.env.scoreboard::get_tx_sram_filled_bytes] Check failed wptr >= rptr (56 [0x38] vs 144 [0x90]) get_sram_filled_bytes

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: * has 1 failures:

Test spi_device_intr has 1 failures.

11.spi_device_intr.2764914584
Line 247, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_intr/latest/run.log

  UVM_ERROR @ 4357682547 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 4361442547 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing TxFifoLtLevel
  UVM_ERROR @ 4362812547 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 4455072547 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

28.spi_device_flash_and_tpm_min_idle.2991072818
Line 231, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 14607166849 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 14818954849 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/18
  UVM_INFO @ 15061126849 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 10/12
  UVM_INFO @ 16964206849 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 11/12
  UVM_INFO @ 17864592849 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/18

UVM_ERROR (spi_device_scoreboard.sv:1391) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_rx_async_fifo_reset has 1 failures.
  - 39.spi_device_rx_async_fifo_reset.2198691588
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  21208699 ps: (spi_device_scoreboard.sv:1391) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  21208699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

40.spi_device_stress_all.2705030209
Line 286, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 117691153721 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 884 [0x374]) get_sram_filled_bytes
  UVM_ERROR @ 117691426451 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x377
  UVM_ERROR @ 117691426451 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x376
  UVM_ERROR @ 117691426451 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x375
  UVM_ERROR @ 117691426451 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x374