SPI_DEVICE Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.340s	190.677us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	165.910us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.650s	455.729us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.030s	1.359ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.450s	1.330ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.070s	37.004us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.650s	455.729us	20	20	100.00
		spi_device_csr_aliasing	24.450s	1.330ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	14.670s	1.943ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.650s	1.551ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	28.934m	64.370ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	51.095m	108.366ms	45	50	90.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	33.508m	1.500s	47	50	94.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	50.711m	105.038ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	50.711m	105.038ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.830s	17.007us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.960s	42.646us	49	50	98.00
V2	interrupts	spi_device_intr	1.494m	21.187ms	50	50	100.00
V2	abort	spi_device_abort	0.810s	12.734us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.780s	817.128us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.720s	4.287ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.530s	384.442us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.181h	360.382ms	50	50	100.00
V2	perf	spi_device_perf	54.705m	187.924ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.850s	17.209us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	27.155us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	24.191us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.830s	2.431ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.830s	2.431ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.900s	43.273ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	183.227us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.593m	15.592ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	55.050s	103.959ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.320s	48.603ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.320s	48.603ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	13.340s	23.941ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	13.340s	23.941ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.340s	23.941ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	13.340s	23.941ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.430s	6.775ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	54.930s	19.188ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.930s	19.188ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.930s	19.188ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.440s	11.529ms	48	50	96.00
		spi_device_read_buffer_direct	8.310s	12.344ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.930s	19.188ms	50	50	100.00
		spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.453m	176.782ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.670s	11.857ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.670s	11.857ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.180m	133.216ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.424m	784.141ms	48	50	96.00
V2	stress_all	spi_device_stress_all	1.855h	219.652ms	41	50	82.00
V2	alert_test	spi_device_alert_test	0.780s	11.453us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	50.739us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.190s	142.385us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.190s	142.385us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	165.910us	5	5	100.00
		spi_device_csr_rw	2.650s	455.729us	20	20	100.00
		spi_device_csr_aliasing	24.450s	1.330ms	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	234.612us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	165.910us	5	5	100.00
		spi_device_csr_rw	2.650s	455.729us	20	20	100.00
		spi_device_csr_aliasing	24.450s	1.330ms	5	5	100.00
		spi_device_same_csr_outstanding	4.530s	234.612us	20	20	100.00
V2		TOTAL			1657	1680	98.63
V2S	tl_intg_err	spi_device_sec_cm	1.210s	88.492us	5	5	100.00
		spi_device_tl_intg_err	22.230s	3.496ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.230s	3.496ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1797	1820	98.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	29	80.56
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	99.06	96.32	98.63	92.06	98.03	96.45	98.54

Failure Buckets

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test spi_device_fifo_full has 5 failures.
  - 3.spi_device_fifo_full.2653790115
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:6afbd87d-b534-48bf-97df-55afcbe8907d
```
  - 7.spi_device_fifo_full.816258206
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:0b6c84da-72a5-4cfe-8f6c-4e46fe111cb4
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 4 failures:

Test spi_device_stress_all has 2 failures.

1.spi_device_stress_all.2733796742
Line 284, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 313226453061 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 313226453061 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 313226453061 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 313226453061 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 313226453061 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

24.spi_device_stress_all.2655675518
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 64088256883 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 64088256883 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 64088256883 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 64088256883 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 64088256883 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_flash_and_tpm_min_idle has 1 failures.

16.spi_device_flash_and_tpm_min_idle.4210426200
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 3274966263 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3274966263 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3274966263 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3274966263 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3274966263 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_flash_and_tpm has 1 failures.

31.spi_device_flash_and_tpm.3731226627
Line 224, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 2413315867 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2413315867 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2413315867 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2413315867 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 2413315867 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Offending '(!dst_pulse_o)' has 2 failures:

Test spi_device_fifo_underflow_overflow has 2 failures.

15.spi_device_fifo_underflow_overflow.2627404266
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 11106266756 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 22824370360ps failed at 22824413838ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 22824413838 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

34.spi_device_fifo_underflow_overflow.2242878822
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 4110154645 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 5556607659ps failed at 5556628936ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 5556628936 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_stress_all has 1 failures.
  - 22.spi_device_stress_all.765111463
    Line 243, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 33.spi_device_fifo_underflow_overflow.1291823726
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:

Test spi_device_stress_all has 2 failures.

23.spi_device_stress_all.2352661056
Line 282, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 334989488219 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 334989575175 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 334992531679 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 334993366669 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 334993488195 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

36.spi_device_stress_all.2374859355
Line 283, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 822728698121 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 822729105528 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 822745735141 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 822753586985 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 822754438836 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

UVM_ERROR (spi_device_scoreboard.sv:1081) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 7.spi_device_flash_mode.1856252010
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1143997287 ps: (spi_device_scoreboard.sv:1081) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1198053107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

16.spi_device_stress_all.1700453612
Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 10298961843 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (0 [0x0] vs 688 [0x2b0]) get_sram_space_bytes::
  UVM_ERROR @ 10299001843 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 172 [0xac]) get_sram_filled_bytes
  UVM_ERROR @ 10299041843 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0xaf
  UVM_ERROR @ 10299041843 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0xae
  UVM_ERROR @ 10299041843 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0xad

UVM_ERROR (spi_device_scoreboard.sv:1391) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_rx_async_fifo_reset has 1 failures.
  - 27.spi_device_rx_async_fifo_reset.66491906
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @ 268612003 ps: (spi_device_scoreboard.sv:1391) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 268612003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 27.spi_device_flash_mode.1940910461
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 10561152541 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 10561152541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_base_vseq.sv:411) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 27.spi_device_stress_all.3003611915
    Line 229, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 82886052401 ps: (spi_device_base_vseq.sv:411) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 82886052401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1253) [scoreboard] Check failed data_act == data_exp (* [*] vs * [*]) Compare SPI TX data has 1 failures:

Test spi_device_stress_all has 1 failures.

43.spi_device_stress_all.4269641916
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 120163752433 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2650139937 [0x9df5ed21] vs 3685532622 [0xdbacc3ce]) Compare SPI TX data
  UVM_ERROR @ 120165401841 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (149781625 [0x8ed7c79] vs 4050311900 [0xf16adadc]) Compare SPI TX data
  UVM_ERROR @ 120168247498 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (1518397651 [0x5a80e8d3] vs 958419821 [0x3920536d]) Compare SPI TX data
  UVM_ERROR @ 120170515478 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (118055467 [0x709622b] vs 4280697004 [0xff2640ac]) Compare SPI TX data
  UVM_ERROR @ 120172164886 ps: (spi_device_scoreboard.sv:1253) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (181274120 [0xace0608] vs 1661450155 [0x6307b7ab]) Compare SPI TX data

UVM_ERROR (spi_device_scoreboard.sv:1081) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

46.spi_device_flash_and_tpm_min_idle.3576186130
Line 217, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 401203550 ps: (spi_device_scoreboard.sv:1081) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 424653550 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/8
  UVM_INFO @ 702392550 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/14
  UVM_INFO @ 929483550 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/8
  UVM_INFO @ 1119344550 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/14

UVM_ERROR (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (* [*] vs * [*]) get_sram_filled_bytes has 1 failures:

Test spi_device_stress_all has 1 failures.

49.spi_device_stress_all.3830233969
Line 229, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 138435976075 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (0 [0x0] vs 888 [0x378]) get_sram_filled_bytes
  UVM_ERROR @ 138436144491 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x37b
  UVM_ERROR @ 138436144491 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x37a
  UVM_ERROR @ 138436144491 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x379
  UVM_ERROR @ 138436144491 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x378