SPI_DEVICE Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.370s	89.665us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.440s	83.656us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	972.291us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.360s	590.763us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	27.260s	1.388ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.070s	65.578us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	972.291us	20	20	100.00
		spi_device_csr_aliasing	27.260s	1.388ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	14.650s	8.142ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	7.020s	2.164ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	31.346m	90.916ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	51.904m	54.813ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	45.127m	378.829ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	27.209m	94.204ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	27.209m	94.204ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.810s	17.966us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.950s	19.341us	50	50	100.00
V2	interrupts	spi_device_intr	2.047m	34.173ms	50	50	100.00
V2	abort	spi_device_abort	0.820s	22.472us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	4.070s	372.523us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.310s	1.040ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.420s	426.043us	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	53.619m	72.032ms	50	50	100.00
V2	perf	spi_device_perf	58.057m	249.167ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.860s	127.181us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	33.423us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	17.373us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	8.240s	231.566us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.240s	231.566us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	28.140s	35.131ms	50	50	100.00
		spi_device_tpm_sts_read	1.180s	181.684us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.705m	49.191ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	37.930s	27.157ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	58.300s	82.252ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	58.300s	82.252ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	16.740s	20.185ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	16.740s	20.185ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	16.740s	20.185ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	16.740s	20.185ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.510s	83.727ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	51.970s	17.487ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	51.970s	17.487ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	51.970s	17.487ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.279m	17.894ms	47	50	94.00
		spi_device_read_buffer_direct	7.410s	1.799ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	51.970s	17.487ms	50	50	100.00
		spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.669m	98.577ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.090s	3.836ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.090s	3.836ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.469m	388.553ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.684m	91.129ms	50	50	100.00
V2	stress_all	spi_device_stress_all	2.305h	472.894ms	44	50	88.00
V2	alert_test	spi_device_alert_test	0.780s	16.562us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.920s	20.539us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.190s	528.297us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.190s	528.297us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.440s	83.656us	5	5	100.00
		spi_device_csr_rw	2.780s	972.291us	20	20	100.00
		spi_device_csr_aliasing	27.260s	1.388ms	5	5	100.00
		spi_device_same_csr_outstanding	4.830s	627.359us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.440s	83.656us	5	5	100.00
		spi_device_csr_rw	2.780s	972.291us	20	20	100.00
		spi_device_csr_aliasing	27.260s	1.388ms	5	5	100.00
		spi_device_same_csr_outstanding	4.830s	627.359us	20	20	100.00
V2		TOTAL			1671	1680	99.46
V2S	tl_intg_err	spi_device_sec_cm	1.200s	74.945us	5	5	100.00
		spi_device_tl_intg_err	22.700s	3.368ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.700s	3.368ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1811	1820	99.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	34	94.44
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	99.06	96.32	98.63	92.06	98.03	96.45	98.54

Failure Buckets

UVM_ERROR (mem_model.sv:35) [rx_mem] read from uninitialized addr * has 2 failures:

Test spi_device_stress_all has 2 failures.

33.spi_device_stress_all.764772195
Line 239, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 157017616348 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x347
  UVM_ERROR @ 157017616348 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x346
  UVM_ERROR @ 157017616348 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x345
  UVM_ERROR @ 157017616348 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x344
  UVM_ERROR @ 157017616348 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4101885124 [0xf47dccc4] vs 3484662194 [0xcfb3b9b2]) Compare SPI RX data, addr: 0x344

45.spi_device_stress_all.2910824531
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 270248272342 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7f
  UVM_ERROR @ 270248272342 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7e
  UVM_ERROR @ 270248272342 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7d
  UVM_ERROR @ 270248272342 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x7c
  UVM_ERROR @ 270248272342 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (4134659868 [0xf671e71c] vs 3202572536 [0xbee360f8]) Compare SPI RX data, addr: 0x7c

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 5.spi_device_flash_mode.1757514733
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 119985021 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 1462998401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1257) [scoreboard] Check failed data_act == data_exp (* [*] vs * [*]) Compare SPI TX data has 1 failures:

Test spi_device_stress_all has 1 failures.

29.spi_device_stress_all.2607678478
Line 235, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 128613322929 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (921790825 [0x36f16969] vs 760078891 [0x2d4de22b]) Compare SPI TX data
  UVM_ERROR @ 128615752929 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (231345501 [0xdca0d5d] vs 1648569375 [0x62432c1f]) Compare SPI TX data
  UVM_ERROR @ 128618152929 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2505336194 [0x95546582] vs 2419396937 [0x90351149]) Compare SPI TX data
  UVM_ERROR @ 128620312929 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2420582229 [0x90472755] vs 3430056224 [0xcc728120]) Compare SPI TX data
  UVM_ERROR @ 128622032929 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (4239094176 [0xfcab71a0] vs 515366554 [0x1eb7de9a]) Compare SPI TX data

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 32.spi_device_flash_mode.1486091322
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/32.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 8374711353 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 11407136897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

34.spi_device_stress_all.2184171483
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 195224295356 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 195224347988 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 195227032220 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 195228190124 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 195228400652 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

37.spi_device_stress_all.1333416719
Line 242, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 495736773397 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 284 [0x11c]) get_sram_space_bytes::
  UVM_ERROR @ 495738133397 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x11f
  UVM_ERROR @ 495738133397 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x11e
  UVM_ERROR @ 495738133397 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x11d
  UVM_ERROR @ 495738133397 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x11c

UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 42.spi_device_flash_mode.3382988830
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 13976805620 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 13976805620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 42.spi_device_stress_all.3769727956
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_stress_all/latest/run.log
```
  Job ID: smart:4c4b0143-a4a4-402b-8ffc-99016b50240f
```