c06cc3921
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_device_smoke | 1.390s | 243.594us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.460s | 40.243us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_device_csr_rw | 2.750s | 435.605us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_device_csr_bit_bash | 33.690s | 596.443us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_device_csr_aliasing | 17.810s | 1.122ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.150s | 345.474us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.750s | 435.605us | 20 | 20 | 100.00 |
spi_device_csr_aliasing | 17.810s | 1.122ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_device_mem_walk | 9.870s | 443.153us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_device_mem_partial_access | 6.790s | 290.053us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | base_random_seq | spi_device_txrx | 27.132m | 315.490ms | 50 | 50 | 100.00 |
V2 | fifo_full | spi_device_fifo_full | 45.785m | 104.133ms | 48 | 50 | 96.00 |
V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 43.887m | 585.203ms | 48 | 50 | 96.00 |
V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 44.736m | 411.568ms | 50 | 50 | 100.00 |
V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 44.736m | 411.568ms | 50 | 50 | 100.00 |
V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0.800s | 16.704us | 50 | 50 | 100.00 |
V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0.950s | 82.408us | 49 | 50 | 98.00 |
V2 | interrupts | spi_device_intr | 1.978m | 117.034ms | 50 | 50 | 100.00 |
V2 | abort | spi_device_abort | 0.800s | 47.378us | 50 | 50 | 100.00 |
V2 | byte_transfer_on_spi | spi_device_byte_transfer | 4.040s | 1.620ms | 50 | 50 | 100.00 |
V2 | rx_timeout | spi_device_rx_timeout | 7.130s | 1.021ms | 50 | 50 | 100.00 |
V2 | bit_transfer_on_spi | spi_device_bit_transfer | 3.600s | 1.980ms | 50 | 50 | 100.00 |
V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 1.224h | 172.896ms | 50 | 50 | 100.00 |
V2 | perf | spi_device_perf | 51.225m | 64.606ms | 50 | 50 | 100.00 |
V2 | csb_read | spi_device_csb_read | 0.840s | 83.036us | 50 | 50 | 100.00 |
V2 | mem_parity | spi_device_mem_parity | 1.130s | 88.759us | 20 | 20 | 100.00 |
V2 | mem_cfg | spi_device_ram_cfg | 0.820s | 63.102us | 20 | 20 | 100.00 |
V2 | tpm_read | spi_device_tpm_rw | 5.830s | 201.774us | 50 | 50 | 100.00 |
V2 | tpm_write | spi_device_tpm_rw | 5.830s | 201.774us | 50 | 50 | 100.00 |
V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 32.760s | 47.802ms | 50 | 50 | 100.00 |
spi_device_tpm_sts_read | 1.150s | 184.898us | 50 | 50 | 100.00 | ||
V2 | tpm_fully_random_case | spi_device_tpm_all | 3.087m | 45.259ms | 50 | 50 | 100.00 |
V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 29.400s | 10.135ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 46.190s | 70.104ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 46.190s | 70.104ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | cmd_info_slots | spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 |
V2 | cmd_read_status | spi_device_intercept | 15.570s | 4.668ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_jedec | spi_device_intercept | 15.570s | 4.668ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | cmd_read_sfdp | spi_device_intercept | 15.570s | 4.668ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | cmd_fast_read | spi_device_intercept | 15.570s | 4.668ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | flash_cmd_upload | spi_device_upload | 34.610s | 9.907ms | 50 | 50 | 100.00 |
V2 | mailbox_command | spi_device_mailbox | 56.180s | 85.469ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_outside_command | spi_device_mailbox | 56.180s | 85.469ms | 50 | 50 | 100.00 |
V2 | mailbox_cross_inside_command | spi_device_mailbox | 56.180s | 85.469ms | 50 | 50 | 100.00 |
V2 | cmd_read_buffer | spi_device_flash_mode | 1.093m | 29.744ms | 49 | 50 | 98.00 |
spi_device_read_buffer_direct | 8.420s | 4.273ms | 50 | 50 | 100.00 | ||
V2 | cmd_dummy_cycle | spi_device_mailbox | 56.180s | 85.469ms | 50 | 50 | 100.00 |
spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 | ||
V2 | quad_spi | spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 |
V2 | dual_spi | spi_device_flash_all | 7.352m | 396.830ms | 50 | 50 | 100.00 |
V2 | 4b_3b_feature | spi_device_cfg_cmd | 10.270s | 15.754ms | 50 | 50 | 100.00 |
V2 | write_enable_disable | spi_device_cfg_cmd | 10.270s | 15.754ms | 50 | 50 | 100.00 |
V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 8.849m | 374.269ms | 50 | 50 | 100.00 |
V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 15.666m | 128.246ms | 50 | 50 | 100.00 |
V2 | stress_all | spi_device_stress_all | 1.523h | 4.622s | 42 | 50 | 84.00 |
V2 | alert_test | spi_device_alert_test | 0.800s | 15.925us | 50 | 50 | 100.00 |
V2 | intr_test | spi_device_intr_test | 0.820s | 19.721us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.040s | 810.635us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_device_tl_errors | 5.040s | 810.635us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.460s | 40.243us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.750s | 435.605us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 17.810s | 1.122ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.390s | 1.401ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.460s | 40.243us | 5 | 5 | 100.00 |
spi_device_csr_rw | 2.750s | 435.605us | 20 | 20 | 100.00 | ||
spi_device_csr_aliasing | 17.810s | 1.122ms | 5 | 5 | 100.00 | ||
spi_device_same_csr_outstanding | 4.390s | 1.401ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1666 | 1680 | 99.17 | |||
V2S | tl_intg_err | spi_device_sec_cm | 1.150s | 312.048us | 5 | 5 | 100.00 |
spi_device_tl_intg_err | 22.390s | 1.689ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.390s | 1.689ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1806 | 1820 | 99.23 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 36 | 36 | 31 | 86.11 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 0 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
96.97 | 99.06 | 96.32 | 98.63 | 92.06 | 98.03 | 96.16 | 98.54 |
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 3 failures:
Test spi_device_fifo_full has 2 failures.
16.spi_device_fifo_full.2212789898
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_fifo_full/latest/run.log
Job ID: smart:9d3d60d4-c863-45ef-9303-7ae53f1fae4f
26.spi_device_fifo_full.1935573789
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_fifo_full/latest/run.log
Job ID: smart:170310a9-7b02-43fa-81d1-1a6762f420dc
Test spi_device_stress_all has 1 failures.
44.spi_device_stress_all.181308829
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_stress_all/latest/run.log
Job ID: smart:bbf77b2d-8ad3-4fa1-92a3-532525d667a0
UVM_FATAL (spi_device_base_vseq.sv:411) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
has 3 failures:
17.spi_device_stress_all.1988758923
Line 223, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_stress_all/latest/run.log
UVM_FATAL @ 264318307890 ps: (spi_device_base_vseq.sv:411) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
UVM_INFO @ 264318307890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_device_stress_all.3537540953
Line 222, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_stress_all/latest/run.log
UVM_FATAL @ 765530136236 ps: (spi_device_base_vseq.sv:411) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
UVM_INFO @ 765530136236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!dst_pulse_o)'
has 2 failures:
18.spi_device_fifo_underflow_overflow.2717729432
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3385688750 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 14197833400 ps: (spi_device_txrx_vseq.sv:109) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] starting sequence 2/2
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 31917853991ps failed at 31917888474ps
Offending '(!dst_pulse_o)'
27.spi_device_fifo_underflow_overflow.2473996393
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_fifo_underflow_overflow/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 296562273 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 315003825ps failed at 315014351ps
Offending '(!dst_pulse_o)'
UVM_ERROR @ 315014351 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*])
has 1 failures:
10.spi_device_rx_async_fifo_reset.2394692008
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 36062680 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 36062680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: *
has 1 failures:
23.spi_device_stress_all.2093698483
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log
UVM_ERROR @ 8916487676 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_ERROR @ 8936533230 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2480285666 [0x93d627e2] vs 1744173869 [0x67f5fb2d]) Compare SPI TX data
UVM_ERROR @ 8936859758 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3547384880 [0xd370cc30] vs 640868665 [0x2632e139]) Compare SPI TX data
UVM_ERROR @ 8937089552 ps: (spi_device_env_pkg.sv:189) [read_rx_avail_bytes] Check failed wptr >= rptr (8 [0x8] vs 72 [0x48]) get_sram_filled_bytes
UVM_ERROR @ 8937109960 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (204848836 [0xc35bec4] vs 1592573873 [0x5eecbfb1]) Compare SPI RX data, addr: 0x48
UVM_ERROR (mem_model.sv:35) [rx_mem] read from uninitialized addr *
has 1 failures:
24.spi_device_stress_all.2537314589
Line 247, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log
UVM_ERROR @ 138623514202 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x3
UVM_ERROR @ 138623514202 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2
UVM_ERROR @ 138623514202 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x1
UVM_ERROR @ 138623514202 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x0
UVM_ERROR @ 138623514202 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (929165885 [0x3761f23d] vs 1568860348 [0x5d82e8bc]) Compare SPI RX data, addr: 0x0
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp *
has 1 failures:
25.spi_device_flash_mode.2128812345
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 28674608 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_INFO @ 425352633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes::
has 1 failures:
35.spi_device_stress_all.2998511352
Line 234, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_stress_all/latest/run.log
UVM_ERROR @ 89113921184 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 496 [0x1f0]) get_sram_space_bytes::
UVM_ERROR @ 89114616832 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x1f3
UVM_ERROR @ 89114616832 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x1f2
UVM_ERROR @ 89114616832 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x1f1
UVM_ERROR @ 89114616832 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x1f0
UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*])
has 1 failures:
45.spi_device_stress_all.1982001999
Line 278, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_stress_all/latest/run.log
UVM_ERROR @ 15801769399 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 15801993887 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 15803708159 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
UVM_ERROR @ 15804157135 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 15804851007 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0