SPI_DEVICE Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_smoke 1.390s 243.594us 50 50 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.460s 40.243us 5 5 100.00
V1 csr_rw spi_device_csr_rw 2.750s 435.605us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 33.690s 596.443us 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 17.810s 1.122ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.150s 345.474us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.750s 435.605us 20 20 100.00
spi_device_csr_aliasing 17.810s 1.122ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 9.870s 443.153us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 6.790s 290.053us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 base_random_seq spi_device_txrx 27.132m 315.490ms 50 50 100.00
V2 fifo_full spi_device_fifo_full 45.785m 104.133ms 48 50 96.00
V2 fifo_underflow_overflow spi_device_fifo_underflow_overflow 43.887m 585.203ms 48 50 96.00
V2 dummy_sck_and_dummy_csb spi_device_dummy_item_extra_dly 44.736m 411.568ms 50 50 100.00
V2 extra_delay_on_spi spi_device_dummy_item_extra_dly 44.736m 411.568ms 50 50 100.00
V2 tx_async_fifo_reset spi_device_tx_async_fifo_reset 0.800s 16.704us 50 50 100.00
V2 rx_async_fifo_reset spi_device_rx_async_fifo_reset 0.950s 82.408us 49 50 98.00
V2 interrupts spi_device_intr 1.978m 117.034ms 50 50 100.00
V2 abort spi_device_abort 0.800s 47.378us 50 50 100.00
V2 byte_transfer_on_spi spi_device_byte_transfer 4.040s 1.620ms 50 50 100.00
V2 rx_timeout spi_device_rx_timeout 7.130s 1.021ms 50 50 100.00
V2 bit_transfer_on_spi spi_device_bit_transfer 3.600s 1.980ms 50 50 100.00
V2 extreme_fifo_setting spi_device_extreme_fifo_size 1.224h 172.896ms 50 50 100.00
V2 perf spi_device_perf 51.225m 64.606ms 50 50 100.00
V2 csb_read spi_device_csb_read 0.840s 83.036us 50 50 100.00
V2 mem_parity spi_device_mem_parity 1.130s 88.759us 20 20 100.00
V2 mem_cfg spi_device_ram_cfg 0.820s 63.102us 20 20 100.00
V2 tpm_read spi_device_tpm_rw 5.830s 201.774us 50 50 100.00
V2 tpm_write spi_device_tpm_rw 5.830s 201.774us 50 50 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 32.760s 47.802ms 50 50 100.00
spi_device_tpm_sts_read 1.150s 184.898us 50 50 100.00
V2 tpm_fully_random_case spi_device_tpm_all 3.087m 45.259ms 50 50 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 29.400s 10.135ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 46.190s 70.104ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 46.190s 70.104ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 cmd_info_slots spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 cmd_read_status spi_device_intercept 15.570s 4.668ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 cmd_read_jedec spi_device_intercept 15.570s 4.668ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 cmd_read_sfdp spi_device_intercept 15.570s 4.668ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 cmd_fast_read spi_device_intercept 15.570s 4.668ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 flash_cmd_upload spi_device_upload 34.610s 9.907ms 50 50 100.00
V2 mailbox_command spi_device_mailbox 56.180s 85.469ms 50 50 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 56.180s 85.469ms 50 50 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 56.180s 85.469ms 50 50 100.00
V2 cmd_read_buffer spi_device_flash_mode 1.093m 29.744ms 49 50 98.00
spi_device_read_buffer_direct 8.420s 4.273ms 50 50 100.00
V2 cmd_dummy_cycle spi_device_mailbox 56.180s 85.469ms 50 50 100.00
spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 quad_spi spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 dual_spi spi_device_flash_all 7.352m 396.830ms 50 50 100.00
V2 4b_3b_feature spi_device_cfg_cmd 10.270s 15.754ms 50 50 100.00
V2 write_enable_disable spi_device_cfg_cmd 10.270s 15.754ms 50 50 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 8.849m 374.269ms 50 50 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 15.666m 128.246ms 50 50 100.00
V2 stress_all spi_device_stress_all 1.523h 4.622s 42 50 84.00
V2 alert_test spi_device_alert_test 0.800s 15.925us 50 50 100.00
V2 intr_test spi_device_intr_test 0.820s 19.721us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.040s 810.635us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.040s 810.635us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.460s 40.243us 5 5 100.00
spi_device_csr_rw 2.750s 435.605us 20 20 100.00
spi_device_csr_aliasing 17.810s 1.122ms 5 5 100.00
spi_device_same_csr_outstanding 4.390s 1.401ms 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.460s 40.243us 5 5 100.00
spi_device_csr_rw 2.750s 435.605us 20 20 100.00
spi_device_csr_aliasing 17.810s 1.122ms 5 5 100.00
spi_device_same_csr_outstanding 4.390s 1.401ms 20 20 100.00
V2 TOTAL 1666 1680 99.17
V2S tl_intg_err spi_device_sec_cm 1.150s 312.048us 5 5 100.00
spi_device_tl_intg_err 22.390s 1.689ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 22.390s 1.689ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1806 1820 99.23

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 36 36 31 86.11
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.97 99.06 96.32 98.63 92.06 98.03 96.16 98.54

Failure Buckets

Past Results