Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.31	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	3	45	93.75

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	3	45	93.75	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15151399	1			T36	8		T57	8		T60	8
all_values[1]	15151399	1			T36	8		T57	8		T60	8
all_values[2]	15151399	1			T36	8		T57	8		T60	8
all_values[3]	15151399	1			T36	8		T57	8		T60	8
all_values[4]	15151399	1			T36	8		T57	8		T60	8
all_values[5]	15151399	1			T36	8		T57	8		T60	8
all_values[6]	15151399	1			T36	8		T57	8		T60	8
all_values[7]	15151399	1			T36	8		T57	8		T60	8
all_values[8]	15151399	1			T36	8		T57	8		T60	8
all_values[9]	15151399	1			T36	8		T57	8		T60	8
all_values[10]	15151399	1			T36	8		T57	8		T60	8
all_values[11]	15151399	1			T36	8		T57	8		T60	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172358216

1

T36

38

T57

38

T60

38

auto[1]

9458572

1

T36

58

T57

58

T60

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181681405

1

T36

53

T57

53

T60

53

auto[1]

135383

1

T36

43

T57

43

T60

43

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[0]]	[auto[1]]	--	--	2
[all_values[9]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	15014076	1			T36	2		T57	2		T60	2
all_values[0]	auto[0]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[0]	auto[1]	auto[0]	137053	1			T29	2		T22	2795		T48	2
all_values[0]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[1]	auto[0]	auto[0]	13803066	1			T36	1		T57	1		T60	1
all_values[1]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[1]	auto[1]	auto[0]	1348153	1			T36	3		T57	3		T60	3
all_values[1]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[2]	auto[0]	auto[0]	15144953	1			T36	2		T57	2		T60	2
all_values[2]	auto[1]	auto[0]	6221	1			T36	1		T57	1		T60	1
all_values[2]	auto[1]	auto[1]	225	1			T36	5		T57	5		T60	5
all_values[3]	auto[0]	auto[0]	15011304	1			T36	2		T57	2		T60	2
all_values[3]	auto[1]	auto[0]	140050	1			T36	5		T57	5		T60	5
all_values[3]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[0]	auto[0]	13936768	1			T5	1		T8	1		T82	1
all_values[4]	auto[0]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[4]	auto[1]	auto[0]	1214361	1			T36	2		T57	2		T60	2
all_values[4]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[5]	auto[0]	auto[0]	15147778	1			T36	1		T57	1		T60	1
all_values[5]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[5]	auto[1]	auto[0]	3396	1			T36	2		T57	2		T60	2
all_values[5]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[6]	auto[0]	auto[0]	14934930	1			T36	2		T57	2		T60	2
all_values[6]	auto[0]	auto[1]	76366	1			T36	2		T57	2		T60	2
all_values[6]	auto[1]	auto[0]	138878	1			T36	4		T57	4		T60	4
all_values[6]	auto[1]	auto[1]	1225	1			T22	25		T42	25		T46	25
all_values[7]	auto[0]	auto[0]	13769476	1			T36	4		T57	4		T60	4
all_values[7]	auto[0]	auto[1]	33424	1			T36	3		T57	3		T60	3
all_values[7]	auto[1]	auto[0]	1342766	1			T36	1		T57	1		T60	1
all_values[7]	auto[1]	auto[1]	5733	1			T22	117		T42	117		T46	117
all_values[8]	auto[0]	auto[0]	13928602	1			T36	2		T57	2		T60	2
all_values[8]	auto[0]	auto[1]	14379	1			T36	1		T57	1		T60	1
all_values[8]	auto[1]	auto[0]	1205878	1			T36	3		T57	3		T60	3
all_values[8]	auto[1]	auto[1]	2540	1			T36	2		T57	2		T60	2
all_values[9]	auto[0]	auto[0]	13802773	1			T36	2		T57	2		T60	2
all_values[9]	auto[1]	auto[0]	1348581	1			T36	5		T57	5		T60	5
all_values[9]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[10]	auto[0]	auto[0]	13803156	1			T36	3		T57	3		T60	3
all_values[10]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[10]	auto[1]	auto[0]	1348108	1			T36	2		T57	2		T60	2
all_values[10]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[11]	auto[0]	auto[0]	13936529	1			T5	1		T8	1		T82	1
all_values[11]	auto[0]	auto[1]	141	1			T137	3		T138	3		T140	3
all_values[11]	auto[1]	auto[0]	1214549	1			T36	4		T57	4		T60	4
all_values[11]	auto[1]	auto[1]	180	1			T36	4		T57	4		T60	4