Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.43	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	1	15	93.75

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4445469

1

T18

2

T20

23638

T27

13217

auto[1]

1866731

1

T18

2

T20

11481

T24

8876

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443423

1

T18

4

T20

23638

T24

4444

auto[1]

3868777

1

T20

11481

T24

4432

T27

13217

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1699788

1

T24

4444

T27

6139

T28

6139

auto[1]

4612412

1

T18

4

T20

35119

T24

4432

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5143516

1

T18

4

T20

35119

T27

13217

auto[1]

1168684

1

T24

8876

T29

80

T30

8683

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5143516

1

T18

4

T20

35119

T27

13217

auto[1]

1168684

1

T24

8876

T29

80

T30

8683

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4445469

1

T18

2

T20

23638

T27

13217

auto[1]

1866731

1

T18

2

T20

11481

T24

8876

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

tx_order	rx_order	cp_cpol	cp_cpha	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

504210

1

T29

7

T22

9197

T48

7

auto[0]

auto[0]

auto[0]

auto[1]

300811

1

T27

6139

T28

6139

T179

6139

auto[0]

auto[0]

auto[1]

auto[0]

1182047

1

T18

2

T20

23638

T29

1

auto[0]

auto[0]

auto[1]

auto[1]

1922106

1

T27

7078

T28

7078

T30

10107

auto[0]

auto[1]

auto[0]

auto[0]

535021

1

T29

8

T30

8683

T22

2405

auto[0]

auto[1]

auto[0]

auto[1]

245

1

T29

5

T48

5

T180

5

auto[0]

auto[1]

auto[1]

auto[0]

735

1

T29

15

T48

15

T180

15

auto[0]

auto[1]

auto[1]

auto[1]

294

1

T29

6

T48

6

T180

6

auto[1]

auto[0]

auto[0]

auto[0]

11072

1

T147

134

T146

76

T110

12

auto[1]

auto[0]

auto[1]

auto[0]

98

1

T18

2

T181

2

T182

2

auto[1]

auto[0]

auto[1]

auto[1]

1223172

1

T20

11481

T22

9678

T172

3498

auto[1]

auto[1]

auto[0]

auto[0]

209603

1

T24

4444

T29

15

T48

15

auto[1]

auto[1]

auto[0]

auto[1]

138826

1

T29

13

T22

1389

T47

1461

auto[1]

auto[1]

auto[1]

auto[0]

637

1

T29

13

T48

13

T180

13

auto[1]

auto[1]

auto[1]

auto[1]

283323

1

T24

4432

T29

5

T48

5