Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.16	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	12	72	85.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	8	40	83.33	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	74962	1			T21	368		T22	411		T32	8
auto[SpiFlashAddrCfg]	13811	1			T21	55		T26	7		T22	78
auto[SpiFlashAddr3b]	19965	1			T21	84		T26	3		T22	111
auto[SpiFlashAddr4b]	14485	1			T21	74		T26	3		T22	74

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73681

1

T21

371

T26

13

T22

400

auto[1]

49542

1

T21

210

T22

274

T23

215

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63233

1

T21

299

T26

10

T22

247

auto[1]

59990

1

T21

282

T26

3

T22

427

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	84608	1			T21	395		T26	5		T22	463
values[1]	1670	1			T21	1		T26	2		T22	8
values[2]	1865	1			T21	6		T22	12		T23	5
values[3]	2715	1			T21	7		T22	12		T23	20
values[4]	3735	1			T21	23		T22	20		T23	13
values[5]	2401	1			T21	12		T22	12		T23	4
values[6]	2510	1			T21	8		T26	3		T22	15
values[7]	2302	1			T21	18		T22	9		T23	5
values[8]	21417	1			T21	111		T26	3		T22	123

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97271

1

T21

581

T22

652

T32

12

auto[1]

25952

1

T26

13

T22

22

T23

485

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

119429

1

T21

568

T26

13

T22

662

write

3794

1

T21

13

T22

12

T23

23

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

39790

1

T21

184

T26

6

T22

196

valids[0x1]

83433

1

T21

397

T26

7

T22

478

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	2509	1			T21	18		T22	8		T23	10
internal_process_ops[0x5a]	2714	1			T21	5		T22	17		T23	21
internal_process_ops[0x05]	46892	1			T21	235		T22	286		T23	154
internal_process_ops[0x35]	3822	1			T21	15		T22	18		T32	8
internal_process_ops[0x15]	3154	1			T21	16		T22	14		T23	18
internal_process_ops[0x03]	1862	1			T21	10		T26	2		T22	12
internal_process_ops[0x0b]	3280	1			T21	13		T26	5		T22	22
internal_process_ops[0x3b]	2542	1			T21	13		T22	14		T32	2
internal_process_ops[0x6b]	1661	1			T21	7		T26	3		T22	6
internal_process_ops[0xbb]	3030	1			T21	17		T26	3		T22	15
internal_process_ops[0xeb]	2257	1			T21	9		T22	10		T32	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121894

1

T21

576

T26

13

T22

669

auto[1]

1329

1

T21

5

T22

5

T23

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118782

1

T21

566

T26

13

T22

659

auto[1]

4441

1

T21

15

T22

15

T23

31

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	8	40	83.33	8
Automatically Generated Cross Bins	48	8	40	83.33	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	[auto[SpiFlashAddrCfg]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[write]	[auto[SpiFlashAddrCfg]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

38374

1

T21

259

T22

243

T32

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

21313

1

T21

105

T22

156

T33

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

6121

1

T21

36

T22

38

T34

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4016

1

T21

17

T22

34

T33

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

7434

1

T21

41

T22

47

T32

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

6464

1

T21

38

T22

51

T33

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5570

1

T21

27

T22

46

T32

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

5384

1

T21

45

T22

26

T33

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

147

1

T41

3

T43

3

T171

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

49

1

T21

1

T35

1

T44

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

441

1

T21

3

T22

1

T35

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

49

1

T41

1

T43

1

T171

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

294

1

T21

1

T22

3

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

196

1

T21

1

T22

1

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

343

1

T21

3

T22

3

T35

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

245

1

T21

2

T22

3

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

294

1

T41

6

T43

6

T171

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

98

1

T41

2

T43

2

T171

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T21

1

T35

1

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

49

1

T41

1

T43

1

T171

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T41

2

T43

2

T171

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

194

1

T21

1

T33

2

T35

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8692

1

T22

8

T23

166

T53

166

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5648

1

T22

2

T23

111

T53

111

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1935

1

T26

7

T22

1

T23

31

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

799

1

T22

1

T23

15

T53

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2538

1

T26

3

T22

6

T23

42

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2499

1

T22

1

T23

49

T53

49

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1392

1

T26

3

T22

2

T23

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1250

1

T23

25

T53

25

T66

25

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

200

1

T23

4

T53

4

T66

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

49

1

T22

1

T42

1

T46

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

50

1

T23

1

T53

1

T66

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T23

1

T53

1

T66

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

150

1

T23

3

T53

3

T66

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

200

1

T23

4

T53

4

T66

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

50

1

T23

1

T53

1

T66

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T23

2

T53

2

T66

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

250

1

T23

5

T53

5

T66

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T23

2

T53

2

T66

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[7]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	12377	1			T21	66		T22	81		T34	12
auto[0]	values[0]	valids[0x1]	54654	1			T21	329		T22	369		T32	8
auto[0]	values[1]	valids[0x1]	1174	1			T21	1		T22	8		T35	1
auto[0]	values[2]	valids[0x0]	1223	1			T21	6		T22	6		T35	6
auto[0]	values[2]	valids[0x1]	392	1			T22	6		T41	2		T42	6
auto[0]	values[3]	valids[0x0]	1225	1			T21	5		T22	6		T34	4
auto[0]	values[3]	valids[0x1]	490	1			T21	2		T22	6		T35	2
auto[0]	values[4]	valids[0x0]	1323	1			T21	12		T22	6		T35	12
auto[0]	values[4]	valids[0x1]	1713	1			T21	11		T22	13		T34	2
auto[0]	values[5]	valids[0x0]	1662	1			T21	9		T22	9		T33	2
auto[0]	values[5]	valids[0x1]	539	1			T21	3		T22	3		T34	4
auto[0]	values[6]	valids[0x0]	882	1			T21	6		T22	6		T35	6
auto[0]	values[6]	valids[0x1]	735	1			T21	2		T22	8		T35	2
auto[0]	values[7]	valids[0x0]	1317	1			T21	12		T22	1		T35	12
auto[0]	values[7]	valids[0x1]	735	1			T21	6		T22	8		T35	6
auto[0]	values[8]	valids[0x0]	10607	1			T21	68		T22	67		T32	4
auto[0]	values[8]	valids[0x1]	6223	1			T21	43		T22	49		T35	43
auto[1]	values[0]	valids[0x0]	4443	1			T22	7		T23	82		T53	82
auto[1]	values[0]	valids[0x1]	13134	1			T26	5		T22	6		T23	252
auto[1]	values[1]	valids[0x1]	496	1			T26	2		T23	8		T52	2
auto[1]	values[2]	valids[0x0]	250	1			T23	5		T53	5		T66	5
auto[1]	values[3]	valids[0x0]	750	1			T23	15		T53	15		T66	15
auto[1]	values[3]	valids[0x1]	250	1			T23	5		T53	5		T66	5
auto[1]	values[4]	valids[0x0]	300	1			T23	6		T53	6		T66	6
auto[1]	values[4]	valids[0x1]	399	1			T22	1		T23	7		T53	7
auto[1]	values[5]	valids[0x0]	100	1			T23	2		T53	2		T66	2
auto[1]	values[5]	valids[0x1]	100	1			T23	2		T53	2		T66	2
auto[1]	values[6]	valids[0x0]	494	1			T26	3		T23	7		T52	3
auto[1]	values[6]	valids[0x1]	399	1			T22	1		T23	7		T53	7
auto[1]	values[7]	valids[0x0]	250	1			T23	5		T53	5		T66	5
auto[1]	values[8]	valids[0x0]	2587	1			T26	3		T22	7		T23	42
auto[1]	values[8]	valids[0x1]	2000	1			T23	40		T53	40		T66	40