Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37276

1

T21

150

T26

11

T22

165

auto[1]

44147

1

T21

221

T22

274

T23

145

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27939

1

T21

105

T26

11

T22

121

auto[1]

53484

1

T21

266

T22

318

T32

8

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	20225	1			T21	79		T26	4		T22	151
auto[524288:1048575]	11367	1			T21	131		T26	3		T22	27
auto[1048576:1572863]	9408	1			T21	4		T26	1		T22	67
auto[1572864:2097151]	10538	1			T21	55		T22	51		T32	5
auto[2097152:2621439]	3695	1			T21	22		T22	17		T23	22
auto[2621440:3145727]	5568	1			T21	12		T22	30		T32	5
auto[3145728:3670015]	12169	1			T21	44		T26	2		T22	23
auto[3670016:4194303]	8453	1			T21	24		T26	1		T22	73

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79312

1

T21

359

T26

11

T22

430

auto[1]

2111

1

T21

12

T22

9

T23

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49514

1

T21

199

T26

8

T22

331

auto[1]

31909

1

T21

172

T26

3

T22

108

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	3225	1			T21	8		T26	4		T22	18
auto[0]	auto[0]	auto[0:524287]	auto[1]	1715	1			T21	3		T22	10		T32	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1872	1			T21	10		T26	3		T22	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	1283	1			T21	11		T22	2		T23	9
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1380	1			T22	9		T150	3		T23	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	692	1			T22	5		T23	6		T53	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1666	1			T21	6		T22	6		T32	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	735	1			T21	3		T22	5		T32	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	842	1			T21	6		T22	2		T23	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	892	1			T21	3		T22	3		T23	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	786	1			T21	4		T22	7		T23	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	493	1			T21	2		T22	3		T23	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1670	1			T21	6		T22	4		T32	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	1281	1			T21	3		T22	2		T150	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1180	1			T21	1		T26	1		T22	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	692	1			T21	1		T22	7		T23	6
auto[0]	auto[1]	auto[0:524287]	auto[0]	1473	1			T21	8		T22	5		T23	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	883	1			T21	3		T22	4		T23	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	977	1			T21	12		T22	1		T32	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	688	1			T21	11		T22	1		T23	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1720	1			T21	3		T26	1		T22	13
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	786	1			T21	1		T22	4		T32	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1177	1			T21	9		T22	2		T23	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	541	1			T21	6		T23	2		T53	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	734	1			T21	1		T22	5		T23	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	343	1			T21	1		T22	4		T35	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2109	1			T21	4		T22	9		T32	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	1085	1			T21	2		T22	6		T32	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1656	1			T21	3		T26	2		T22	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	835	1			T21	2		T22	2		T32	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1031	1			T21	9		T22	4		T23	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	834	1			T21	8		T22	1		T23	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	835	1			T21	2		T22	5		T23	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	11210	1			T21	55		T22	109		T23	38
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	447	1			T21	2		T22	1		T23	6
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2474	1			T21	11		T22	15		T23	24
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	298	1			T22	1		T23	4		T53	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2800	1			T22	22		T23	7		T53	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	196	1			T21	1		T22	1		T35	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4067	1			T21	20		T22	37		T35	20
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	148	1			T21	1		T22	1		T23	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	638	1			T21	10		T22	2		T23	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	49	1			T22	1		T42	1		T46	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	196	1			T22	4		T42	4		T46	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	494	1			T21	2		T23	4		T53	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3240	1			T21	28		T23	6		T53	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	199	1			T22	1		T23	3		T53	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1819	1			T22	31		T23	6		T53	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	197	1			T23	1		T53	1		T66	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	687	1			T23	1		T53	1		T66	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	196	1			T21	4		T35	4		T44	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	3430	1			T21	70		T35	70		T44	70
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	296	1			T22	2		T23	2		T53	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1436	1			T22	11		T23	15		T53	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	147	1			T21	1		T35	1		T41	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	2009	1			T21	9		T35	9		T41	32
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	49	1			T41	1		T43	1		T171	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	49	1			T41	1		T43	1		T171	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	300	1			T23	6		T53	6		T66	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	550	1			T23	11		T53	11		T66	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	295	1			T22	1		T23	1		T53	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	2698	1			T22	10		T23	3		T53	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	295	1			T21	2		T22	1		T23	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	2403	1			T21	3		T22	18		T23	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	20060	1			T21	67		T26	8		T22	97
auto[0]	auto[0]	auto[1]	344	1			T22	3		T23	1		T53	1
auto[0]	auto[1]	auto[0]	16480	1			T21	80		T26	3		T22	64
auto[0]	auto[1]	auto[1]	392	1			T21	3		T22	1		T35	3
auto[1]	auto[0]	auto[0]	28373	1			T21	128		T22	227		T23	100
auto[1]	auto[0]	auto[1]	737	1			T21	4		T22	4		T23	2
auto[1]	auto[1]	auto[0]	14399	1			T21	84		T22	42		T23	42
auto[1]	auto[1]	auto[1]	638	1			T21	5		T22	1		T23	1