Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	1	8	88.89
Crosses	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_write	2	0	2	100.00	100	1	1	0
cp_payload_size	7	1	6	85.71	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	8	1	7	87.50	100	1	1	0

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

2123

1

T21

7

T22

8

T23

16

write

2318

1

T21

8

T22

7

T23

15

---

Summary for Variable cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for cp_payload_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
frequent_use_values[4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
excess_fifo	937	1			T21	4		T22	2		T23	6
frequent_use_values[0]	2223	1			T21	7		T22	8		T23	18
frequent_use_values[1]	98	1			T21	2		T35	2		T44	2
frequent_use_values[2]	149	1			T22	1		T23	2		T53	2
frequent_use_values[3]	49	1			T41	1		T43	1		T171	1
frequent_use_values[256]	541	1			T21	1		T22	4		T23	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	1	7	87.50	1
Automatically Generated Cross Bins	8	1	7	87.50	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_is_write	cp_payload_size	COUNT	AT LEAST	NUMBER	STATUS
[write]	[frequent_use_values[4]]	0	1	1

Covered bins

cp_is_write	cp_payload_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read	frequent_use_values[0]	2123	1			T21	7		T22	8		T23	16
write	excess_fifo	937	1			T21	4		T22	2		T23	6
write	frequent_use_values[0]	100	1			T23	2		T53	2		T66	2
write	frequent_use_values[1]	98	1			T21	2		T35	2		T44	2
write	frequent_use_values[2]	149	1			T22	1		T23	2		T53	2
write	frequent_use_values[3]	49	1			T41	1		T43	1		T171	1
write	frequent_use_values[256]	541	1			T21	1		T22	4		T23	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
read_w_nonzero_payload	0	Illegal