Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
34.93	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	128	94	34	26.56

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	1	7	87.50	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	94	34	26.56	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58724

1

T21

371

T22

383

T32

12

auto[1]

38547

1

T21

210

T22

269

T33

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_data

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8183	1			T21	51		T22	40		T35	51
values[1]	6860	1			T21	40		T22	40		T35	40
values[2]	4753	1			T21	26		T22	31		T35	26
values[3]	11417	1			T21	61		T22	111		T35	61
values[5]	19208	1			T21	126		T22	134		T35	126
values[6]	24408	1			T21	150		T22	154		T32	12
values[7]	22442	1			T21	127		T22	142		T35	127

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	21756	1			T21	142		T22	119		T35	142
values[1]	3234	1			T22	20		T41	46		T42	20
values[2]	5635	1			T21	20		T22	75		T35	20
values[3]	19459	1			T21	130		T22	99		T32	12
values[4]	9163	1			T21	80		T22	59		T35	80
values[5]	9114	1			T21	51		T22	80		T35	51
values[6]	16562	1			T21	91		T22	140		T35	91
values[7]	12348	1			T21	67		T22	60		T35	67

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	94	34	26.56	94

Automatically Generated Cross Bins for cr_all

Element holes

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	10
*	[values[0]]	[values[7]]	--	--	2
*	[values[1]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	12
*	[values[2]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	12
*	[values[2]]	[values[7]]	--	--	2
*	[values[3]]	[values[1]]	--	--	2
*	[values[3]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	10
*	[values[4]]	*	--	--	16
*	[values[5]]	[values[1] , values[2] , values[3] , values[4]]	--	--	8
*	[values[6]]	[values[0] , values[1] , values[2]]	--	--	6
*	[values[6]]	[values[4]]	--	--	2
*	[values[6]]	[values[6] , values[7]]	--	--	4
*	[values[7]]	[values[2] , values[3]]	--	--	4
*	[values[7]]	[values[5] , values[6]]	--	--	4

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	3283	1			T21	10		T22	12		T35	10
auto[0]	values[0]	values[6]	1470	1			T21	10		T22	9		T35	10
auto[0]	values[1]	values[6]	1715	1			T21	13		T22	8		T35	13
auto[0]	values[1]	values[7]	2793	1			T21	16		T22	11		T35	16
auto[0]	values[2]	values[6]	4018	1			T21	21		T22	24		T35	21
auto[0]	values[3]	values[0]	2548	1			T21	9		T22	29		T35	9
auto[0]	values[3]	values[2]	1715	1			T21	8		T22	13		T35	8
auto[0]	values[5]	values[0]	1715	1			T21	12		T22	9		T35	12
auto[0]	values[5]	values[5]	3038	1			T21	23		T22	20		T35	23
auto[0]	values[5]	values[6]	2205	1			T21	17		T22	14		T35	17
auto[0]	values[5]	values[7]	3773	1			T21	12		T22	16		T35	12
auto[0]	values[6]	values[3]	15653	1			T21	114		T22	87		T32	12
auto[0]	values[6]	values[5]	2989	1			T21	11		T22	43		T35	11
auto[0]	values[7]	values[0]	2548	1			T21	10		T22	33		T35	10
auto[0]	values[7]	values[1]	1029	1			T22	12		T41	9		T42	12
auto[0]	values[7]	values[4]	6027	1			T21	66		T22	29		T35	66
auto[0]	values[7]	values[7]	2205	1			T21	19		T22	14		T35	19
auto[1]	values[0]	values[0]	1617	1			T21	21		T22	8		T35	21
auto[1]	values[0]	values[6]	1813	1			T21	10		T22	11		T35	10
auto[1]	values[1]	values[6]	1225	1			T21	7		T22	12		T35	7
auto[1]	values[1]	values[7]	1127	1			T21	4		T22	9		T35	4
auto[1]	values[2]	values[6]	735	1			T21	5		T22	7		T35	5
auto[1]	values[3]	values[0]	3234	1			T21	32		T22	7		T35	32
auto[1]	values[3]	values[2]	3920	1			T21	12		T22	62		T35	12
auto[1]	values[5]	values[0]	2695	1			T21	38		T22	11		T35	38
auto[1]	values[5]	values[5]	1127	1			T21	8		T22	5		T35	8
auto[1]	values[5]	values[6]	3381	1			T21	8		T22	55		T35	8
auto[1]	values[5]	values[7]	1274	1			T21	8		T22	4		T35	8
auto[1]	values[6]	values[3]	3806	1			T21	16		T22	12		T33	16
auto[1]	values[6]	values[5]	1960	1			T21	9		T22	12		T35	9
auto[1]	values[7]	values[0]	4116	1			T21	10		T22	10		T35	10
auto[1]	values[7]	values[1]	2205	1			T22	8		T41	37		T42	8
auto[1]	values[7]	values[4]	3136	1			T21	14		T22	30		T35	14
auto[1]	values[7]	values[7]	1176	1			T21	8		T22	6		T35	8