Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.75	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15151399	1			T36	8		T57	8		T60	8
all_pins[1]	15151399	1			T36	8		T57	8		T60	8
all_pins[2]	15151399	1			T36	8		T57	8		T60	8
all_pins[3]	15151399	1			T36	8		T57	8		T60	8
all_pins[4]	15151399	1			T36	8		T57	8		T60	8
all_pins[5]	15151399	1			T36	8		T57	8		T60	8
all_pins[6]	15151399	1			T36	8		T57	8		T60	8
all_pins[7]	15151399	1			T36	8		T57	8		T60	8
all_pins[8]	15151399	1			T36	8		T57	8		T60	8
all_pins[9]	15151399	1			T36	8		T57	8		T60	8
all_pins[10]	15151399	1			T36	8		T57	8		T60	8
all_pins[11]	15151399	1			T36	8		T57	8		T60	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	181647882	1			T36	70		T57	70		T60	70
values[0x1]	168906	1			T36	26		T57	26		T60	26
transitions[0x0=>0x1]	164150	1			T36	15		T57	15		T60	15
transitions[0x1=>0x0]	164195	1			T36	16		T57	16		T60	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[2]]	[transitions[0x1=>0x0]]	0	1	1
[all_pins[3]]	[transitions[0x0=>0x1]]	0	1	1
[all_pins[6]]	[transitions[0x0=>0x1]]	0	1	1
[all_pins[10]]	[transitions[0x0=>0x1]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15151264	1			T36	5		T57	5		T60	5
all_pins[0]	values[0x1]	135	1			T36	3		T57	3		T60	3
all_pins[0]	transitions[0x0=>0x1]	135	1			T36	3		T57	3		T60	3
all_pins[0]	transitions[0x1=>0x0]	138305	1			T36	3		T57	3		T60	3
all_pins[1]	values[0x0]	15013094	1			T36	5		T57	5		T60	5
all_pins[1]	values[0x1]	138305	1			T36	3		T57	3		T60	3
all_pins[1]	transitions[0x0=>0x1]	138072	1			T22	2808		T47	10		T178	10
all_pins[1]	transitions[0x1=>0x0]	1062	1			T36	2		T57	2		T60	2
all_pins[2]	values[0x0]	15150104	1			T36	3		T57	3		T60	3
all_pins[2]	values[0x1]	1295	1			T36	5		T57	5		T60	5
all_pins[2]	transitions[0x0=>0x1]	1250	1			T36	4		T57	4		T60	4
all_pins[3]	values[0x0]	15151354	1			T36	7		T57	7		T60	7
all_pins[3]	values[0x1]	45	1			T36	1		T57	1		T60	1
all_pins[3]	transitions[0x1=>0x0]	968	1			T36	2		T57	2		T60	2
all_pins[4]	values[0x0]	15150386	1			T36	5		T57	5		T60	5
all_pins[4]	values[0x1]	1013	1			T36	3		T57	3		T60	3
all_pins[4]	transitions[0x0=>0x1]	582	1			T36	1		T57	1		T60	1
all_pins[4]	transitions[0x1=>0x0]	1842	1			T36	1		T57	1		T60	1
all_pins[5]	values[0x0]	15149126	1			T36	5		T57	5		T60	5
all_pins[5]	values[0x1]	2273	1			T36	3		T57	3		T60	3
all_pins[5]	transitions[0x0=>0x1]	2273	1			T36	3		T57	3		T60	3
all_pins[5]	transitions[0x1=>0x0]	1274	1			T22	26		T42	26		T46	26
all_pins[6]	values[0x0]	15150125	1			T36	8		T57	8		T60	8
all_pins[6]	values[0x1]	1274	1			T22	26		T42	26		T46	26
all_pins[6]	transitions[0x1=>0x0]	4802	1			T22	98		T42	98		T46	98
all_pins[7]	values[0x0]	15145323	1			T36	8		T57	8		T60	8
all_pins[7]	values[0x1]	6076	1			T22	124		T42	124		T46	124
all_pins[7]	transitions[0x0=>0x1]	3528	1			T22	72		T42	72		T46	72
all_pins[7]	transitions[0x1=>0x0]	90	1			T36	2		T57	2		T60	2
all_pins[8]	values[0x0]	15148761	1			T36	6		T57	6		T60	6
all_pins[8]	values[0x1]	2638	1			T36	2		T57	2		T60	2
all_pins[8]	transitions[0x0=>0x1]	2638	1			T36	2		T57	2		T60	2
all_pins[8]	transitions[0x1=>0x0]	45	1			T36	1		T57	1		T60	1
all_pins[9]	values[0x0]	15151354	1			T36	7		T57	7		T60	7
all_pins[9]	values[0x1]	45	1			T36	1		T57	1		T60	1
all_pins[9]	transitions[0x0=>0x1]	45	1			T36	1		T57	1		T60	1
all_pins[9]	transitions[0x1=>0x0]	45	1			T36	1		T57	1		T60	1
all_pins[10]	values[0x0]	15151354	1			T36	7		T57	7		T60	7
all_pins[10]	values[0x1]	45	1			T36	1		T57	1		T60	1
all_pins[10]	transitions[0x1=>0x0]	15717	1			T36	3		T57	3		T60	3
all_pins[11]	values[0x0]	15135637	1			T36	4		T57	4		T60	4
all_pins[11]	values[0x1]	15762	1			T36	4		T57	4		T60	4
all_pins[11]	transitions[0x0=>0x1]	15627	1			T36	1		T57	1		T60	1
all_pins[11]	transitions[0x1=>0x0]	45	1			T36	1		T57	1		T60	1