Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.45	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	15	45	75.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	15	45	75.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	976	1			T21	4		T22	4		T32	2
auto[ReadAddrCrossIntoMailbox]	882	1			T21	6		T22	8		T35	6
auto[ReadAddrCrossOutOfMailbox]	784	1			T21	6		T22	2		T35	6
auto[ReadAddrCrossAllMailbox]	539	1			T21	3		T22	3		T35	3
auto[ReadAddrOutsideMailbox]	9729	1			T21	50		T22	60		T32	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6700

1

T21

39

T22

36

T32

2

auto[1]

6210

1

T21

30

T22

41

T32

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1666	1			T21	10		T22	12		T35	10
read_ops[0x0b]	2791	1			T21	13		T22	21		T34	4
read_ops[0x3b]	2442	1			T21	13		T22	14		T32	2
read_ops[0x6b]	1417	1			T21	7		T22	6		T33	4
read_ops[0xbb]	2687	1			T21	17		T22	14		T35	17
read_ops[0xeb]	1907	1			T21	9		T22	10		T32	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossOutOfMailbox] , auto[ReadAddrCrossAllMailbox]]	*	--	--	4
[read_ops[0x6b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2

Uncovered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossIntoMailbox]]	[auto[0]]	0	1	1
[read_ops[0x0b]]	[auto[ReadAddrWithinMailbox]]	[auto[1]]	0	1	1
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	[auto[0]]	0	1	1
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	[auto[1]]	0	1	1
[read_ops[0x6b]]	[auto[ReadAddrCrossAllMailbox]]	[auto[0]]	0	1	1
[read_ops[0xbb] , read_ops[0xeb]]	[auto[ReadAddrWithinMailbox]]	[auto[1]]	--	--	2
[read_ops[0xbb] , read_ops[0xeb]]	[auto[ReadAddrCrossAllMailbox]]	[auto[1]]	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	147	1			T22	2		T41	1		T42	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	98	1			T41	2		T43	2		T171	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	49	1			T41	1		T43	1		T171	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T21	4		T22	1		T35	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	1078	1			T21	6		T22	9		T35	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	98	1			T21	1		T22	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	98	1			T22	1		T41	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	49	1			T21	1		T35	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	49	1			T41	1		T43	1		T171	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	147	1			T22	2		T41	1		T42	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	49	1			T21	1		T35	1		T44	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	1175	1			T21	6		T22	9		T34	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	1126	1			T21	4		T22	8		T34	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	194	1			T22	1		T32	1		T38	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	96	1			T32	1		T38	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	98	1			T21	1		T22	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	98	1			T22	2		T42	2		T46	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	49	1			T21	1		T35	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	196	1			T21	1		T22	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	49	1			T21	1		T35	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	98	1			T21	1		T35	1		T41	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	831	1			T21	5		T22	3		T33	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	733	1			T21	3		T22	6		T33	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T21	1		T35	1		T44	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	98	1			T41	2		T43	2		T171	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	49	1			T22	1		T42	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	49	1			T22	1		T42	1		T46	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	831	1			T21	5		T22	2		T33	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	341	1			T21	1		T22	2		T33	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T21	1		T35	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	196	1			T21	1		T22	2		T35	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	98	1			T21	2		T35	2		T44	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	245	1			T21	2		T22	1		T35	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	49	1			T41	1		T43	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	49	1			T41	1		T43	1		T171	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	1074	1			T21	6		T22	5		T35	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	927	1			T21	5		T22	6		T35	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	147	1			T21	1		T35	1		T41	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	98	1			T22	1		T41	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	49	1			T21	1		T35	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	49	1			T41	1		T43	1		T171	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	147	1			T21	2		T35	2		T41	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	98	1			T41	2		T43	2		T171	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	586	1			T21	3		T22	3		T32	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	733	1			T21	2		T22	6		T32	1