Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
30.82	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	101	27	21.09

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	101	27	21.09	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	14700	1			T21	66		T22	94		T35	66
values[1]	10682	1			T21	70		T22	59		T35	70
values[2]	24402	1			T21	175		T22	213		T35	175
values[3]	10535	1			T21	45		T22	124		T35	45
values[4]	3528	1			T21	30		T22	20		T35	30
values[5]	3381	1			T21	27		T22	20		T35	27
values[6]	11270	1			T21	90		T22	60		T35	90
values[7]	18773	1			T21	78		T22	62		T32	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	11270	1			T21	70		T22	114		T35	70
values[1]	5782	1			T21	41		T22	36		T35	41
values[2]	20635	1			T21	87		T22	97		T32	12
values[3]	6664	1			T21	47		T22	40		T35	47
values[4]	8330	1			T21	70		T22	40		T35	70
values[5]	17101	1			T21	81		T22	140		T35	81
values[6]	4900	1			T21	31		T22	20		T35	31
values[7]	22589	1			T21	154		T22	165		T35	154

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96391

1

T21

576

T22

648

T32

12

auto[1]

880

1

T21

5

T22

4

T33

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	101	27	21.09	101

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	*	--	--	8
[auto[1]]	[values[5] , values[6]]	*	--	--	16

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[0]]	[values[0]]	[values[4]]	0	1	1
[auto[0]]	[values[0]]	[values[6]]	0	1	1
[auto[0]]	[values[1]]	[values[1]]	0	1	1
[auto[0]]	[values[1]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[0]]	[values[2]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[0]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[0]]	[values[3]]	[values[3] , values[4]]	--	--	2
[auto[0]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[0]]	[values[4]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[0]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[0]]	[values[5]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[0]]	[values[5]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[0]]	[values[6]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[0]]	[values[6]]	[values[5] , values[6]]	--	--	2
[auto[0]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[0]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[0]]	[values[7]]	[values[7]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[0]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[2]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[3]	3234	1			T21	20		T22	20		T35	20
auto[0]	values[0]	values[5]	4655	1			T21	24		T22	31		T35	24
auto[0]	values[0]	values[7]	6664	1			T21	20		T22	43		T35	20
auto[0]	values[1]	values[0]	5439	1			T21	50		T22	36		T35	50
auto[0]	values[1]	values[2]	4998	1			T21	20		T22	20		T35	20
auto[0]	values[2]	values[0]	5537	1			T21	19		T22	74		T35	19
auto[0]	values[2]	values[1]	5733	1			T21	41		T22	36		T35	41
auto[0]	values[2]	values[7]	12936	1			T21	114		T22	102		T35	114
auto[0]	values[3]	values[2]	4949	1			T21	20		T22	55		T35	20
auto[0]	values[3]	values[5]	5586	1			T21	25		T22	69		T35	25
auto[0]	values[4]	values[5]	3479	1			T21	30		T22	20		T35	30
auto[0]	values[5]	values[3]	3381	1			T21	27		T22	20		T35	27
auto[0]	values[6]	values[4]	8330	1			T21	70		T22	40		T35	70
auto[0]	values[6]	values[7]	2940	1			T21	20		T22	20		T35	20
auto[0]	values[7]	values[2]	10445	1			T21	45		T22	22		T32	12
auto[0]	values[7]	values[5]	3234	1			T22	20		T41	46		T42	20
auto[0]	values[7]	values[6]	4851	1			T21	31		T22	20		T35	31
auto[1]	values[0]	values[3]	49	1			T41	1		T43	1		T171	1
auto[1]	values[0]	values[5]	98	1			T21	2		T35	2		T44	2
auto[1]	values[1]	values[0]	196	1			T22	3		T41	1		T42	3
auto[1]	values[1]	values[2]	49	1			T41	1		T43	1		T171	1
auto[1]	values[2]	values[0]	98	1			T21	1		T22	1		T35	1
auto[1]	values[2]	values[1]	49	1			T41	1		T43	1		T171	1
auto[1]	values[2]	values[7]	49	1			T41	1		T43	1		T171	1
auto[1]	values[4]	values[5]	49	1			T41	1		T43	1		T171	1
auto[1]	values[7]	values[2]	194	1			T21	2		T33	2		T35	2
auto[1]	values[7]	values[6]	49	1			T41	1		T43	1		T171	1