Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_4b_en	2	0	2	100.00	100	1	1	2
cp_prev_addr_4b_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	4	0	4	100.00	100	1	1	0

Summary for Variable cp_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_4b_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3044

1

T21

9

T22

15

T23

16

auto[1]

3347

1

T21

13

T22

16

T23

15

---

Summary for Variable cp_prev_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_prev_addr_4b_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2996

1

T21

9

T22

15

T23

16

auto[1]

3395

1

T21

13

T22

16

T23

15

---

Summary for Cross cr_all

Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_4b_en

cp_prev_addr_4b_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1715

1

T21

4

T22

8

T23

9

auto[0]

auto[1]

1329

1

T21

5

T22

7

T23

7

auto[1]

auto[0]

1281

1

T21

5

T22

7

T23

7

auto[1]

auto[1]

2066

1

T21

8

T22

9

T23

8