Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.56	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	1	29	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	1	29	96.67	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4090

1

T31

11

T22

23

T51

11

auto[1]

3265

1

T31

8

T22

10

T51

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987

1

T31

19

T22

30

T51

19

auto[1]

4368

1

T22

3

T23

7

T136

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6298

1

T31

11

T22

25

T51

11

auto[1]

1057

1

T31

8

T22

8

T51

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	927	1			T31	2		T22	3		T51	2
valid[1]	1856	1			T31	3		T22	11		T51	3
valid[2]	1509	1			T31	4		T22	6		T51	4
valid[3]	1317	1			T31	3		T22	7		T51	3
valid[4]	1746	1			T31	7		T22	6		T51	7

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	1	29	96.67	1
Automatically Generated Cross Bins	30	1	29	96.67	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[valid[0]]	[auto[0]]	0	1	1

Covered bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	197	1			T22	2		T23	1		T53	1
auto[0]	auto[0]	valid[0]	auto[1]	196	1			T136	2		T139	2		T143	2
auto[0]	auto[0]	valid[1]	auto[0]	288	1			T31	2		T22	4		T51	2
auto[0]	auto[0]	valid[1]	auto[1]	639	1			T22	1		T23	2		T136	1
auto[0]	auto[0]	valid[2]	auto[0]	193	1			T31	1		T22	3		T51	1
auto[0]	auto[0]	valid[2]	auto[1]	540	1			T22	1		T23	1		T136	1
auto[0]	auto[0]	valid[3]	auto[0]	341	1			T31	1		T22	5		T51	1
auto[0]	auto[0]	valid[3]	auto[1]	294	1			T136	3		T139	3		T143	3
auto[0]	auto[0]	valid[4]	auto[0]	335	1			T31	3		T22	3		T51	3
auto[0]	auto[0]	valid[4]	auto[1]	588	1			T136	3		T139	8		T143	8
auto[0]	auto[1]	valid[0]	auto[0]	95	1			T31	1		T51	1		T141	1
auto[0]	auto[1]	valid[0]	auto[1]	344	1			T23	1		T136	1		T53	1
auto[0]	auto[1]	valid[1]	auto[0]	98	1			T22	1		T41	1		T42	1
auto[0]	auto[1]	valid[1]	auto[1]	491	1			T23	1		T136	3		T53	1
auto[0]	auto[1]	valid[2]	auto[0]	147	1			T22	2		T41	1		T42	2
auto[0]	auto[1]	valid[2]	auto[1]	392	1			T136	1		T139	6		T143	6
auto[0]	auto[1]	valid[3]	auto[0]	141	1			T31	2		T22	1		T51	2
auto[0]	auto[1]	valid[3]	auto[1]	392	1			T136	1		T139	7		T143	7
auto[0]	auto[1]	valid[4]	auto[0]	95	1			T31	1		T22	1		T51	1
auto[0]	auto[1]	valid[4]	auto[1]	492	1			T22	1		T23	2		T136	2
auto[1]	auto[0]	valid[1]	auto[0]	193	1			T31	1		T22	3		T51	1
auto[1]	auto[0]	valid[2]	auto[0]	187	1			T31	3		T51	3		T141	3
auto[1]	auto[0]	valid[3]	auto[0]	50	1			T23	1		T53	1		T66	1
auto[1]	auto[0]	valid[4]	auto[0]	49	1			T22	1		T42	1		T46	1
auto[1]	auto[1]	valid[0]	auto[0]	95	1			T31	1		T22	1		T51	1
auto[1]	auto[1]	valid[1]	auto[0]	147	1			T22	2		T41	1		T42	2
auto[1]	auto[1]	valid[2]	auto[0]	50	1			T23	1		T53	1		T66	1
auto[1]	auto[1]	valid[3]	auto[0]	99	1			T22	1		T23	1		T53	1
auto[1]	auto[1]	valid[4]	auto[0]	187	1			T31	3		T51	3		T141	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal