Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.11	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	26	46	63.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	26	46	63.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	315	1			T36	7		T57	7		T60	7
all_values[1]	315	1			T36	7		T57	7		T60	7
all_values[2]	315	1			T36	7		T57	7		T60	7
all_values[3]	315	1			T36	7		T57	7		T60	7
all_values[4]	315	1			T36	7		T57	7		T60	7
all_values[5]	315	1			T36	7		T57	7		T60	7
all_values[6]	315	1			T36	7		T57	7		T60	7
all_values[7]	315	1			T36	7		T57	7		T60	7
all_values[8]	315	1			T36	7		T57	7		T60	7
all_values[9]	315	1			T36	7		T57	7		T60	7
all_values[10]	315	1			T36	7		T57	7		T60	7
all_values[11]	315	1			T36	7		T57	7		T60	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2025

1

T36

45

T57

45

T60

45

auto[1]

1755

1

T36

39

T57

39

T60

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1755

1

T36

39

T57

39

T60

39

auto[1]

2025

1

T36

45

T57

45

T60

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2340

1

T36

52

T57

52

T60

52

auto[1]

1440

1

T36

32

T57

32

T60

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	26	46	63.89	26
Automatically Generated Cross Bins	72	26	46	63.89	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[6]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[7]]	*	[auto[1]]	[auto[1]]	--	--	2
[all_values[9]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[11]]	[auto[0]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[2]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[2]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[3]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[4]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[5]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[6]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[8]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[8]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[9]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[10]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[11]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[0]	auto[0]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[1]	auto[0]	auto[0]	auto[0]	90	1			T36	2		T57	2		T60	2
all_values[1]	auto[0]	auto[1]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[1]	auto[0]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[1]	auto[1]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[1]	auto[1]	auto[1]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[2]	auto[0]	auto[1]	auto[1]	180	1			T36	4		T57	4		T60	4
all_values[2]	auto[1]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[2]	auto[1]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[3]	auto[1]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[0]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[0]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[1]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[4]	auto[1]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[5]	auto[0]	auto[0]	auto[0]	90	1			T36	2		T57	2		T60	2
all_values[5]	auto[0]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[5]	auto[1]	auto[0]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[5]	auto[1]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[6]	auto[0]	auto[0]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[6]	auto[0]	auto[1]	auto[0]	90	1			T36	2		T57	2		T60	2
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[7]	auto[0]	auto[0]	auto[0]	90	1			T36	2		T57	2		T60	2
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[7]	auto[0]	auto[1]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[7]	auto[1]	auto[0]	auto[1]	135	1			T36	3		T57	3		T60	3
all_values[8]	auto[0]	auto[0]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[8]	auto[0]	auto[1]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[8]	auto[0]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[9]	auto[0]	auto[0]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[9]	auto[0]	auto[1]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[9]	auto[1]	auto[1]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[10]	auto[0]	auto[0]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[10]	auto[0]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[10]	auto[0]	auto[1]	auto[0]	45	1			T36	1		T57	1		T60	1
all_values[10]	auto[1]	auto[1]	auto[1]	90	1			T36	2		T57	2		T60	2
all_values[11]	auto[0]	auto[1]	auto[0]	135	1			T36	3		T57	3		T60	3
all_values[11]	auto[1]	auto[0]	auto[1]	45	1			T36	1		T57	1		T60	1
all_values[11]	auto[1]	auto[1]	auto[1]	135	1			T36	3		T57	3		T60	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal