Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81904

1

T31

645

T22

644

T51

645

auto[1]

40317

1

T22

23

T23

88

T136

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92109

1

T31

435

T22

445

T51

435

auto[1]

30112

1

T31

210

T22

222

T51

210

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	63611	1			T31	351		T22	345		T51	351
others[1]	10032	1			T31	46		T22	58		T51	46
others[2]	10585	1			T31	58		T22	56		T51	58
others[3]	10280	1			T31	60		T22	54		T51	60
interest[1]	7227	1			T31	30		T22	55		T51	30
interest[4]	41953	1			T31	230		T22	229		T51	230
interest[64]	20486	1			T31	100		T22	99		T51	100

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	27607	1			T31	245		T22	215		T51	245
auto[0]	auto[0]	others[1]	4433	1			T31	29		T22	44		T51	29
auto[0]	auto[0]	others[2]	4448	1			T31	39		T22	34		T51	39
auto[0]	auto[0]	others[3]	4443	1			T31	41		T22	34		T51	41
auto[0]	auto[0]	interest[1]	3087	1			T31	19		T22	30		T51	19
auto[0]	auto[0]	interest[4]	18605	1			T31	166		T22	148		T51	166
auto[0]	auto[0]	interest[64]	7774	1			T31	62		T22	65		T51	62
auto[0]	auto[1]	others[0]	20483	1			T22	7		T23	50		T136	18
auto[0]	auto[1]	others[1]	3338	1			T22	3		T23	6		T53	6
auto[0]	auto[1]	others[2]	3190	1			T22	4		T23	5		T53	5
auto[0]	auto[1]	others[3]	3291	1			T22	3		T23	8		T53	8
auto[0]	auto[1]	interest[1]	2159	1			T22	2		T23	3		T53	3
auto[0]	auto[1]	interest[4]	13653	1			T22	5		T23	31		T136	18
auto[0]	auto[1]	interest[64]	7856	1			T22	4		T23	16		T53	16
auto[1]	auto[0]	others[0]	15521	1			T31	106		T22	123		T51	106
auto[1]	auto[0]	others[1]	2261	1			T31	17		T22	11		T51	17
auto[1]	auto[0]	others[2]	2947	1			T31	19		T22	18		T51	19
auto[1]	auto[0]	others[3]	2546	1			T31	19		T22	17		T51	19
auto[1]	auto[0]	interest[1]	1981	1			T31	11		T22	23		T51	11
auto[1]	auto[0]	interest[4]	9695	1			T31	64		T22	76		T51	64
auto[1]	auto[0]	interest[64]	4856	1			T31	38		T22	30		T51	38

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal