Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	85297316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24932543

1

T36

20

T54

12929

T57

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96271184	1			T36	20		T54	9474		T57	20
values[0x0]	6994835	1			T36	6		T54	4733		T57	6
values[0x1]	6963840	1			T36	14		T54	4740		T57	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45655759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64574100

1

T36

25

T54

14182

T57

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	425662	1			T54	73		T58	5		T59	4
valid_sources[0x01]	438311	1			T54	54		T59	6		T1	31
valid_sources[0x02]	440290	1			T54	62		T58	11		T1	12
valid_sources[0x03]	432680	1			T54	59		T59	2		T1	10
valid_sources[0x04]	422037	1			T54	87		T1	1		T12	13
valid_sources[0x05]	433001	1			T54	66		T58	6		T1	26
valid_sources[0x06]	442879	1			T54	74		T1	30		T12	8
valid_sources[0x07]	424518	1			T54	51		T59	2		T1	14
valid_sources[0x08]	436206	1			T36	4		T54	63		T57	4
valid_sources[0x09]	426443	1			T54	95		T59	16		T1	54
valid_sources[0x0a]	412486	1			T54	102		T59	5		T1	40
valid_sources[0x0b]	435005	1			T54	93		T58	13		T59	8
valid_sources[0x0c]	434163	1			T54	74		T59	11		T1	31
valid_sources[0x0d]	427615	1			T54	72		T58	2		T1	36
valid_sources[0x0e]	413053	1			T54	55		T58	1		T59	1
valid_sources[0x0f]	440229	1			T54	80		T59	11		T1	45
valid_sources[0x10]	430728	1			T54	49		T59	10		T1	18
valid_sources[0x11]	455914	1			T54	55		T1	32		T12	21
valid_sources[0x12]	403960	1			T54	66		T58	1		T1	30
valid_sources[0x13]	452588	1			T54	43		T58	4		T1	31
valid_sources[0x14]	435146	1			T54	59		T59	1		T1	68
valid_sources[0x15]	430552	1			T54	47		T59	5		T1	39
valid_sources[0x16]	407813	1			T54	110		T59	17		T1	46
valid_sources[0x17]	409869	1			T54	78		T59	12		T1	53
valid_sources[0x18]	423680	1			T54	48		T58	5		T59	2
valid_sources[0x19]	438780	1			T54	111		T58	1		T1	44
valid_sources[0x1a]	428612	1			T54	55		T59	28		T1	15
valid_sources[0x1b]	430946	1			T54	72		T1	48		T12	14
valid_sources[0x1c]	413118	1			T54	45		T1	19		T12	3
valid_sources[0x1d]	435191	1			T54	61		T58	10		T59	7
valid_sources[0x1e]	436265	1			T54	32		T59	11		T1	34
valid_sources[0x1f]	441663	1			T54	50		T58	11		T59	4
valid_sources[0x20]	432441	1			T54	111		T1	31		T12	3
valid_sources[0x21]	441501	1			T54	54		T58	1		T1	32
valid_sources[0x22]	436878	1			T54	87		T59	7		T1	42
valid_sources[0x23]	431907	1			T54	122		T1	30		T12	6
valid_sources[0x24]	419790	1			T54	81		T1	19		T12	1
valid_sources[0x25]	417121	1			T54	93		T58	5		T59	9
valid_sources[0x26]	427860	1			T54	81		T1	16		T12	7
valid_sources[0x27]	411723	1			T54	75		T59	11		T1	22
valid_sources[0x28]	419853	1			T54	49		T1	20		T12	5
valid_sources[0x29]	435603	1			T54	60		T1	19		T12	2
valid_sources[0x2a]	429472	1			T54	49		T59	15		T1	79
valid_sources[0x2b]	429054	1			T54	60		T59	3		T1	16
valid_sources[0x2c]	419391	1			T54	101		T58	1		T1	25
valid_sources[0x2d]	425306	1			T54	89		T1	27		T12	9
valid_sources[0x2e]	428429	1			T54	71		T58	2		T1	42
valid_sources[0x2f]	429562	1			T36	5		T54	100		T57	5
valid_sources[0x30]	438287	1			T54	43		T59	14		T1	41
valid_sources[0x31]	422512	1			T54	43		T1	35		T14	17
valid_sources[0x32]	438410	1			T54	61		T59	13		T1	16
valid_sources[0x33]	413558	1			T54	70		T59	6		T1	45
valid_sources[0x34]	416546	1			T54	84		T59	6		T1	46
valid_sources[0x35]	440051	1			T54	63		T1	29		T14	47
valid_sources[0x36]	444606	1			T54	83		T58	10		T59	9
valid_sources[0x37]	421094	1			T54	48		T59	7		T1	33
valid_sources[0x38]	442259	1			T54	127		T58	1		T1	47
valid_sources[0x39]	449108	1			T54	83		T1	38		T12	7
valid_sources[0x3a]	432855	1			T54	61		T59	2		T1	30
valid_sources[0x3b]	429339	1			T54	37		T59	5		T1	54
valid_sources[0x3c]	426801	1			T54	65		T59	1		T1	25
valid_sources[0x3d]	448980	1			T54	57		T58	1		T59	1
valid_sources[0x3e]	429807	1			T54	107		T58	1		T59	5
valid_sources[0x3f]	414827	1			T54	109		T1	23		T12	1
valid_sources[0x40]	423064	1			T54	55		T59	1		T1	42
valid_sources[0x41]	425351	1			T54	126		T58	3		T1	39
valid_sources[0x42]	427136	1			T54	74		T59	10		T1	32
valid_sources[0x43]	417771	1			T54	40		T59	1		T1	49
valid_sources[0x44]	423247	1			T54	39		T59	1		T1	20
valid_sources[0x45]	407454	1			T54	93		T59	1		T1	36
valid_sources[0x46]	412858	1			T54	76		T58	1		T1	22
valid_sources[0x47]	442342	1			T54	89		T58	9		T59	1
valid_sources[0x48]	421644	1			T54	153		T58	3		T59	3
valid_sources[0x49]	427023	1			T54	90		T1	39		T14	37
valid_sources[0x4a]	454872	1			T54	93		T59	6		T1	43
valid_sources[0x4b]	415788	1			T54	93		T59	12		T1	34
valid_sources[0x4c]	435744	1			T54	57		T58	5		T59	7
valid_sources[0x4d]	419192	1			T54	64		T1	16		T14	27
valid_sources[0x4e]	441726	1			T54	60		T1	59		T12	6
valid_sources[0x4f]	444923	1			T54	89		T1	33		T12	12
valid_sources[0x50]	448136	1			T54	72		T1	36		T12	9
valid_sources[0x51]	407814	1			T54	85		T58	9		T59	1
valid_sources[0x52]	454614	1			T54	79		T1	16		T12	4
valid_sources[0x53]	442207	1			T36	7		T54	34		T57	7
valid_sources[0x54]	452282	1			T54	52		T59	6		T1	46
valid_sources[0x55]	445887	1			T54	60		T1	26		T12	9
valid_sources[0x56]	434972	1			T54	63		T59	5		T1	30
valid_sources[0x57]	436113	1			T54	91		T58	1		T1	36
valid_sources[0x58]	405675	1			T54	76		T59	10		T1	22
valid_sources[0x59]	418028	1			T54	70		T59	6		T1	29
valid_sources[0x5a]	407938	1			T54	110		T59	12		T1	26
valid_sources[0x5b]	416973	1			T54	69		T59	10		T1	22
valid_sources[0x5c]	444690	1			T54	82		T59	5		T1	24
valid_sources[0x5d]	417231	1			T54	60		T58	4		T1	21
valid_sources[0x5e]	433252	1			T36	2		T54	103		T57	2
valid_sources[0x5f]	421170	1			T54	63		T58	4		T1	25
valid_sources[0x60]	419474	1			T54	73		T1	26		T14	19
valid_sources[0x61]	429868	1			T54	114		T1	23		T12	3
valid_sources[0x62]	440003	1			T54	93		T58	3		T59	6
valid_sources[0x63]	435862	1			T54	36		T59	4		T1	49
valid_sources[0x64]	434220	1			T54	79		T58	1		T59	4
valid_sources[0x65]	429000	1			T36	3		T54	51		T57	3
valid_sources[0x66]	414767	1			T54	82		T59	6		T1	23
valid_sources[0x67]	408163	1			T54	66		T59	1		T1	20
valid_sources[0x68]	407453	1			T54	91		T59	1		T1	51
valid_sources[0x69]	432862	1			T54	78		T58	9		T59	6
valid_sources[0x6a]	436177	1			T54	98		T58	6		T59	1
valid_sources[0x6b]	415053	1			T54	63		T59	4		T1	29
valid_sources[0x6c]	430336	1			T54	51		T58	1		T59	3
valid_sources[0x6d]	432035	1			T54	66		T58	3		T1	23
valid_sources[0x6e]	441203	1			T54	52		T59	1		T1	29
valid_sources[0x6f]	421273	1			T54	82		T1	45		T12	7
valid_sources[0x70]	438772	1			T54	69		T59	5		T1	31
valid_sources[0x71]	440617	1			T54	48		T58	5		T1	51
valid_sources[0x72]	410134	1			T54	70		T58	7		T1	44
valid_sources[0x73]	440592	1			T54	61		T59	3		T1	14
valid_sources[0x74]	436727	1			T54	62		T1	36		T12	3
valid_sources[0x75]	461032	1			T54	77		T1	22		T12	8
valid_sources[0x76]	460544	1			T54	67		T58	1		T59	4
valid_sources[0x77]	404757	1			T54	65		T59	1		T1	28
valid_sources[0x78]	445806	1			T54	92		T59	11		T1	13
valid_sources[0x79]	425797	1			T54	69		T1	46		T12	3
valid_sources[0x7a]	419204	1			T54	72		T59	8		T1	20
valid_sources[0x7b]	422886	1			T54	64		T58	6		T1	26
valid_sources[0x7c]	426812	1			T54	99		T58	3		T59	3
valid_sources[0x7d]	442595	1			T54	57		T1	28		T12	10
valid_sources[0x7e]	450434	1			T54	40		T59	13		T1	40
valid_sources[0x7f]	425351	1			T54	93		T58	2		T1	39
valid_sources[0x80]	429721	1			T54	80		T58	1		T1	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11454362

1

T36

11

T54

4745

T57

11

values[0x0]

all_enables

biggest_size

6767615

1

T36

5

T54

4263

T57

5

values[0x1]

all_enables

biggest_size

6710566

1

T36

4

T54

3921

T57

4