Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::all_modes_cg

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	5	0	5	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_tpm_enabled	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	5	0	5	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	6312200	1			T18	4		T20	35119		T24	8876
auto[FlashMode]	136405	1			T31	645		T26	21		T22	583
auto[PassthroughMode]	114235	1			T21	581		T22	758		T32	36

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Summary for Variable cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tpm_enabled

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6352081

1

T18

4

T20

35119

T24

8876

auto[1]

210759

1

T31

645

T22

1341

T51

645

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Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_mode	cp_tpm_enabled	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[GenericMode]	auto[0]	6312200	1			T18	4		T20	35119		T24	8876
auto[FlashMode]	auto[0]	1008	1			T26	21		T52	21		T166	21
auto[FlashMode]	auto[1]	135397	1			T31	645		T22	583		T51	645
auto[PassthroughMode]	auto[0]	38873	1			T21	581		T32	36		T150	36
auto[PassthroughMode]	auto[1]	75362	1			T22	758		T41	780		T42	758

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded