Unified Coverage Report :: Module Instance :: tb.dut.u_fwmode.u_rx_fifo

Module Instance : tb.dut.u_fwmode.u_rx_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	91.67	100.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Module Instance : tb.dut.u_fwmode.u_tx_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	91.67	100.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.92	100.00	80.00			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.44	100.00	80.00			93.75	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.82	100.00	100.00		100.00	94.12	100.00	u_spid_status

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	99.04	93.66		91.67	93.58	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Module Instance : tb.dut.u_spi_tpm.u_wrfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	99.04	93.66		91.67	93.58	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Module Instance : tb.dut.u_spi_tpm.u_rdfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.44	100.00	93.75			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.59	99.04	93.66		91.67	93.58	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
214	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo

	Total	Covered	Percent
Conditions	30	29	96.67
Logical	30	29	96.67
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T20,T22,T47
1	1	Covered	T18,T20,T24

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T20,T27,T28
1	1	Covered	T18,T20,T24

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T22,T47

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T22,T47

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T22,T47

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T22,T47

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T24

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
1	0	Covered	T18,T20,T24
1	1	Covered	T18,T20,T24

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T22,T47
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T22,T47
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	1451396031	1451388973	0	0
GrayWptr_A	523661164	523659656	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451396031	1451388973	0	0
T18	2021	2020	0	0
T20	220000	219999	0	0
T21	116105	116105	0	0
T24	292735	292734	0	0
T25	12832	12831	0	0
T27	389119	389119	0	0
T28	389119	389119	0	0
T29	22296	22295	0	0
T31	190563	190562	0	0
T50	1126	1125	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523661164	523659656	0	0
T18	129	128	0	0
T20	112381	112380	0	0
T21	116105	116105	0	0
T24	357406	357405	0	0
T25	12832	12831	0	0
T27	422946	422945	0	0
T28	422946	422945	0	0
T29	3140	3139	0	0
T30	601281	601280	0	0
T31	190563	190562	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
214	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo

	Total	Covered	Percent
Conditions	30	29	96.67
Logical	30	29	96.67
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T18,T20,T24

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T47
1	0	Covered	T18,T20,T24
1	1	Covered	T18,T20,T24

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T24,T27

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T24,T27

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T24,T27

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T24,T27

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T18,T20,T24
1	Covered	T18,T19,T20

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T24

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
1	0	Covered	T18,T20,T24
1	1	Covered	T18,T20,T24

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T24,T27
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T24,T27
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T24
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	523662425	523659367	0	0
GrayWptr_A	1451396031	1451389579	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523662425	523659367	0	0
T18	130	128	0	0
T19	1	0	0	0
T20	112381	112380	0	0
T21	116106	116105	0	0
T24	357406	357404	0	0
T25	0	12831	0	0
T27	422946	422944	0	0
T28	422946	422944	0	0
T29	3141	3139	0	0
T30	0	601280	0	0
T31	190563	190561	0	0
T50	1	0	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1451396031	1451389579	0	0
T18	2021	2020	0	0
T20	220000	219999	0	0
T21	116105	116105	0	0
T24	292735	292734	0	0
T25	12832	12831	0	0
T27	389119	389119	0	0
T28	389119	389119	0	0
T29	22296	22295	0	0
T31	190563	190562	0	0
T50	1126	1125	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Cond Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Covered	Percent
Conditions	25	20	80.00
Logical	25	20	80.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T21,T25,T26

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Unreachable
1	1	Covered	T21,T25,T26

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T21,T25,T26
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T21,T25,T26
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T21,T25,T26
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T21,T25,T26
1	Covered	T18,T19,T20

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T21,T25,T26
1	Covered	T18,T19,T20

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	146	3	2	66.67
TERNARY	160	3	2	66.67
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T18,T19,T20
0	0	Covered	T21,T25,T26

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T18,T19,T20
0	0	Covered	T21,T25,T26

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T21,T25,T26

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T21,T25,T26
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T21,T25,T26
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T21,T25,T26
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T21,T25,T26
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T21,T25,T26
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	523661164	523659706	0	0
GrayWptr_A	2147483647	2147483647	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523661164	523659706	0	0
T18	129	128	0	0
T20	112381	112380	0	0
T21	116105	116105	0	0
T24	357406	357405	0	0
T25	12832	12831	0	0
T27	422946	422945	0	0
T28	422946	422945	0	0
T29	3140	3139	0	0
T30	601281	601280	0	0
T31	190563	190562	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2032	0	0
T19	2243	2180	0	0
T20	220007	220001	0	0
T21	477085	477078	0	0
T24	292742	292736	0	0
T27	389127	389120	0	0
T28	389127	389120	0	0
T29	22370	22307	0	0
T31	788392	788329	0	0
T50	1200	1137	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Covered	Percent
Conditions	26	24	92.31
Logical	26	24	92.31
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T31,T22,T51

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T22,T51
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T22,T51
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T20,T24

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	2147483647	2147483647	0	0
GrayWptr_A	523661164	523659706	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2032	0	0
T19	2243	2180	0	0
T20	220007	220001	0	0
T21	477085	477078	0	0
T24	292742	292736	0	0
T27	389127	389120	0	0
T28	389127	389120	0	0
T29	22370	22307	0	0
T31	788392	788329	0	0
T50	1200	1137	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523661164	523659706	0	0
T18	129	128	0	0
T20	112381	112380	0	0
T21	116105	116105	0	0
T24	357406	357405	0	0
T25	12832	12831	0	0
T27	422946	422945	0	0
T28	422946	422945	0	0
T29	3140	3139	0	0
T30	601281	601280	0	0
T31	190563	190562	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo

	Total	Covered	Percent
Conditions	32	30	93.75
Logical	32	30	93.75
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T31,T22,T51

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T22,T42,T46

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T22,T42,T46

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (7'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T22,T42,T46

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (7'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T22,T42,T46

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T42,T46
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T42,T46
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	2147483647	2147483647	0	0
GrayWptr_A	523661164	523659706	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2032	0	0
T19	2243	2180	0	0
T20	220007	220001	0	0
T21	477085	477078	0	0
T24	292742	292736	0	0
T27	389127	389120	0	0
T28	389127	389120	0	0
T29	22370	22307	0	0
T31	788392	788329	0	0
T50	1200	1137	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523661164	523659706	0	0
T18	129	128	0	0
T20	112381	112380	0	0
T21	116105	116105	0	0
T24	357406	357405	0	0
T25	12832	12831	0	0
T27	422946	422945	0	0
T28	422946	422945	0	0
T29	3140	3139	0	0
T30	601281	601280	0	0
T31	190563	190562	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo

	Total	Covered	Percent
Conditions	32	30	93.75
Logical	32	30	93.75
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T31,T22,T51

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (5'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (5'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T31,T22,T51
1	Covered	T18,T19,T20

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T31,T22,T51

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T22,T51
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T22,T51
0	1	Covered	T18,T19,T20
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T24,T31,T81

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T24,T31,T81

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T24,T31,T81

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T31,T22,T51
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	523662425	40116035	0	0
GrayWptr_A	2147483647	125730080	0	0
ParamCheckDepth_A	1600	1600	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523662425	40116035	0	0
T21	116106	0	0	0
T22	292318	353125	0	0
T23	0	88223	0	0
T25	12833	0	0	0
T26	51395	0	0	0
T29	3141	0	0	0
T30	601282	0	0	0
T31	190563	182219	0	0
T47	112354	0	0	0
T51	0	182219	0	0
T53	0	88223	0	0
T55	1	0	0	0
T81	1	0	0	0
T136	0	1278	0	0
T137	0	3886	0	0
T138	0	3886	0	0
T139	0	158844	0	0
T140	0	3886	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125730080	0	0
T21	477085	0	0	0
T22	0	249283	0	0
T23	0	709472	0	0
T24	292742	2983	0	0
T25	16456	0	0	0
T26	60875	0	0	0
T27	389127	0	0	0
T28	389127	0	0	0
T29	22370	0	0	0
T30	256348	0	0	0
T31	788392	731439	0	0
T50	1200	0	0	0
T51	0	731439	0	0
T81	0	209	0	0
T113	0	2983	0	0
T136	0	5166	0	0
T137	0	15607	0	0
T138	0	15607	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0