Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	96.31	94.03	97.00		93.33	96.30

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.39	96.31	94.03	97.00		93.33	96.30

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	96.31	94.03	97.00		93.33	96.30

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.04	98.96	95.60	98.63	92.06	97.97	87.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	1.64						1.64
tlul_assert_device	95.24	100.00				85.71	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_edge_0	100.00	100.00	100.00			100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	99.06	100.00	97.33		100.00	97.96	100.00
u_csb_buf	100.00	100.00
u_csb_edge_spiclk	94.44	100.00	83.33			100.00
u_csb_edge_sysclk	100.00	100.00	100.00			100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_fwmode	94.73	98.79	89.44		100.00	96.53	88.89
u_intr_cmdfifo_not_empty	93.75	100.00	75.00			100.00	100.00
u_intr_payload_not_empty	93.75	100.00	75.00			100.00	100.00
u_intr_payload_overflow	93.75	100.00	75.00			100.00	100.00
u_intr_readbuf_flip	91.67	100.00	66.67			100.00	100.00
u_intr_readbuf_watermark	91.67	100.00	66.67			100.00	100.00
u_intr_rxerr	80.52	85.71	36.36			100.00	100.00
u_intr_rxf	91.67	100.00	66.67			100.00	100.00
u_intr_rxlvl	93.75	100.00	75.00			100.00	100.00
u_intr_rxoverflow	91.67	100.00	66.67			100.00	100.00
u_intr_tpm_cmdaddr_notempty	86.94	90.00	77.78			80.00	100.00
u_intr_txlvl	93.75	100.00	75.00			100.00	100.00
u_intr_txunderflow	93.75	100.00	75.00			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_memory_2p	100.00	100.00	100.00			100.00	100.00
u_p2s	90.20	100.00	84.62			76.19	100.00
u_passthrough	90.46	94.33	90.09		75.00	92.86	100.00
u_readcmd	92.82	97.16	91.62		87.50	87.82	100.00
u_reg	99.66	99.49	99.47	100.00		99.32	100.00
u_rx_rst_scan_mux	64.81	100.00	44.44				50.00
u_rxf_overflow	75.00	100.00	100.00			100.00	0.00
u_s2p	89.85	100.00	85.71			73.68	100.00
u_scanmode_sync	100.00						100.00
u_sck_csb_edge	94.44	100.00	83.33			100.00
u_sck_tog_edge	100.00	100.00	100.00			100.00
u_spi_tpm	96.29	99.52	93.53		91.67	96.71	100.00
u_spid_addr_4b	98.41	100.00	95.24			100.00
u_spid_status	96.19	100.00	86.84		100.00	94.12	100.00
u_sram_clk_cg	83.33	100.00	50.00			100.00
u_sram_clk_scan	64.81	100.00	44.44				50.00
u_sram_clk_sel	100.00	100.00	100.00				100.00
u_sram_rst_scanmux	64.81	100.00	44.44				50.00
u_sram_rst_sel	96.30	100.00	88.89				100.00
u_sync_rxf	100.00	100.00				100.00
u_sync_txe	100.00	100.00				100.00
u_sys_sram_arbiter	87.03	100.00	70.73			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram	87.50	88.70	76.07			85.23	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tx_rst_scan_mux	64.81	100.00	44.44				50.00
u_txf_underflow	75.00	100.00	100.00			100.00	0.00
u_upload	91.13	98.58	73.82		100.00	93.98	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		244	235	96.31
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
ALWAYS	443	3	3	100.00
ALWAYS	447	3	3	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
ALWAYS	480	5	5	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	0	0
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
ALWAYS	497	5	5	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	737	4	4	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
ALWAYS	764	0	0
ALWAYS	764	2	2	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	770	1	1	100.00
ALWAYS	778	0	0
ALWAYS	778	12	12	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
ALWAYS	1095	6	6	100.00
ALWAYS	1121	4	4	100.00
CONT_ASSIGN	1140	1	1	100.00
ALWAYS	1164	3	3	100.00
ALWAYS	1170	8	8	100.00
ALWAYS	1208	35	35	100.00
ALWAYS	1301	13	13	100.00
ALWAYS	1338	3	3	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1548	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1588	1	0	0.00
CONT_ASSIGN	1618	1	0	0.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1703	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1708	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1714	1	1	100.00
CONT_ASSIGN	1717	1	1	100.00
CONT_ASSIGN	1720	1	1	100.00
CONT_ASSIGN	1723	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1737	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1881	1	0	0.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1891	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
CONT_ASSIGN	1893	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1908	1	1	100.00
CONT_ASSIGN	1909	1	1	100.00
CONT_ASSIGN	1910	1	1	100.00
CONT_ASSIGN	1911	1	1	100.00
CONT_ASSIGN	1912	1	1	100.00
CONT_ASSIGN	1913	1	1	100.00
CONT_ASSIGN	1915	1	1	100.00
CONT_ASSIGN	1919	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
CONT_ASSIGN	1922	1	1	100.00
CONT_ASSIGN	1929	1	1	100.00
CONT_ASSIGN	1931	1	1	100.00
CONT_ASSIGN	1933	1	1	100.00
CONT_ASSIGN	1937	1	1	100.00
CONT_ASSIGN	1939	1	1	100.00
CONT_ASSIGN	1940	1	1	100.00
CONT_ASSIGN	1976	1	1	100.00
ALWAYS	1983	6	6	100.00
CONT_ASSIGN	1994	1	1	100.00
CONT_ASSIGN	1994	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1997	1	1	100.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1998	1	1	100.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1999	1	1	100.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2046	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2049	1	1	100.00
CONT_ASSIGN	2050	1	1	100.00
CONT_ASSIGN	2052	1	1	100.00
CONT_ASSIGN	2053	1	1	100.00
CONT_ASSIGN	2054	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
191	1	1
341	1	1
400	1	1
401	1	1
402	1	1
403	1	1
405	1	1
406	1	1
408	1	1
410	1	1
414	1	1
415	1	1
416	1	1
417	1	1
419	1	1
420	1	1
423	1	1
424	1	1
427	1	1
430	1	1
431	1	1
434	1	1
435	1	1
438	1	1
439	1	1
443	2	2
444	1	1
447	2	2
448	1	1
463	1	1
467	1	1
468	1	1
480	1	1
481	1	1
482	1	1
484	1	1
485	1	1
490	1	1
491		unreachable
493	1	1
494	1	1
497	1	1
498	1	1
499	1	1
501	1	1
502	1	1
505	1	1
506	1	1
623	1	1
725	1	1
732	1	1
734	1	1
737	1	1
738	1	1
739	1	1
740	1	1
			MISSING_ELSE
745	1	1
751	1	1
754	1	1
755	1	1
759	1	1
764	1	1
765	1	1
769	1	1
770	1	1
778	1	1
779	1	1
797	1	1
798	1	1
802	1	1
803	1	1
805	1	1
806	1	1
808	1	1
809	1	1
811	1	1
812	1	1
844	1	1
845	1	1
846	1	1
1095	2	2
1096	1	1
1097	1	1
1098	1	1
1099	1	1
			MISSING_ELSE
1121	2	2
1122	1	1
1123	1	1
			MISSING_ELSE
1140	1	1
1164	2	2
1165	1	1
1170	1	1
1172	1	1
1173	1	1
1180	1	1
1184	1	1
1185	1	1
1189	1	1
1190	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
1213	1	1
1215	1	1
1221	1	1
1227	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1237	1	1
1238	1	1
1243	1	1
1244	1	1
1246	1	1
1248	1	1
1250	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1261	1	1
1263	1	1
1264	1	1
1265	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1278	1	1
1280	1	1
1281	1	1
1282	1	1
1301	1	1
1302	1	1
1304	1	1
1306	1	1
1307	1	1
1311	1	1
1313	1	1
1314	1	1
1318	1	1
1319	1	1
1320	1	1
1322	1	1
1323	1	1
1338	2	2
1339	1	1
1540	1	1
1542	1	1
1545	1	1
1546	1	1
1548	1	1
1549	1	1
1588	0	1
1618	0	1
1702	1	1
1703	1	1
1705	1	1
1707	1	1
1708	1	1
1710	1	1
1714	1	1
1717	1	1
1720	1	1
1723	1	1
1726	1	1
1729	1	1
1736	1	1
1737	1	1
1779	1	1
1881	0	1
1889	1	1
1890	1	1
1891	1	1
1892	1	1
1893	1	1
1896	1	1
1905	5	5
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1913	1	1
1915	1	1
1919	1	1
1921	1	1
1922	1	1
1929	1	1
1931	1	1
1933	1	1
1937	1	1
1939	1	1
1940	1	1
1976	1	1
1983	1	1
1984	1	1
1985	1	1
1986	1	1
1987	1	1
1989	1	1
			MISSING_ELSE
1994	2	2
1996	3	3
1997	1	3
1998	1	3
1999	1	3
2001	3	3
2002	3	3
2003	3	3
2046	1	1
2047	1	1
2048	1	1
2049	1	1
2050	1	1
2052	1	1
2053	1	1
2054	1	1
2114	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	67	63	94.03
Logical	67	63	94.03
Non-Logical	0	0
Event	0	0

 LINE       191
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       490
 EXPRESSION (((~sram_rxf_full_q)) & sram_rxf_full)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T27,T28
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T27,T28

 LINE       491
 EXPRESSION (((~fwm_rxerr_q)) & fwm_rxerr)
             --------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T18,T19,T20
1	1	Unreachable

 LINE       505
 EXPRESSION (((~rxlvl)) && rxlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T29,T22
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T29,T22

 LINE       506
 EXPRESSION (((~txlvl)) && txlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T24
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T20,T24

 LINE       845
 EXPRESSION ((cpha ^ cpol) ? sck_n : cio_sck_i)
             ------1------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T27

 LINE       845
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T20,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T20,T24,T27

 LINE       846
 EXPRESSION ((cpha ^ cpol) ? cio_sck_i : sck_n)
             ------1------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T27

 LINE       846
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T20,T29
1	0	Covered	T27,T28,T29
1	1	Covered	T20,T24,T27

 LINE       899
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T20,T24

 LINE       908
 EXPRESSION (rst_ni & ((~rst_txfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T107,T108,T109
1	1	Covered	T18,T19,T20

 LINE       917
 EXPRESSION (rst_ni & ((~rst_rxfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T110,T111,T112
1	1	Covered	T18,T19,T20

 LINE       928
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T24,T31,T81

 LINE       976
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T24

 LINE       1003
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T20,T24

 LINE       1140
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
1	0	Covered	T31,T22,T51

 LINE       1194
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       1304
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T24,T81,T113
1	0	Covered	T31,T22,T51
1	1	Covered	T31,T22,T51

 LINE       1540
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T21,T25,T26

 LINE       1548
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       1549
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       1736
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       1737
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T22,T23

 LINE       1986
 EXPRESSION ((0 != j) && sys_sram_l2m[j].req)
             ----1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T21,T22,T23

 LINE       1986
 SUB-EXPRESSION (0 != j)
                ----1---

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       2114
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T114,T115,T116
1	0	Covered	T18,T19,T20
1	1	Covered	T114,T115,T116

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	58	92.06
Total Bits	466	452	97.00
Total Bits 0->1	233	226	97.00
Total Bits 1->0	233	226	97.00

Ports	63	58	92.06
Port Bits	466	452	97.00
Port Bits 0->1	233	226	97.00
Port Bits 1->0	233	226	97.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
rst_ni	Yes	Yes	T58,T1,T2	Yes	T36,T54,T57	INPUT
tl_i.d_ready	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_address[31:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_source[7:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_size[1:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_i.a_valid	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
tl_o.a_ready	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_error	Yes	Yes	T58,T1,T2	Yes	T58,T1,T2	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T36,*T54,*T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T36,*T54,*T57	Yes	T36,T54,T57	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T1,T12	Yes	T54,T1,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T1,T12	Yes	T54,T1,T12	OUTPUT
cio_sck_i	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	INPUT
cio_csb_i	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	INPUT
cio_sd_o[3:0]	Yes	Yes	T21,T25,T26	Yes	T21,T25,T26	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T21,T25,T26	Yes	T21,T25,T26	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	INPUT
cio_tpm_csb_i	Yes	Yes	T24,T31,T81	Yes	T24,T31,T81	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T21,*T22,*T32	Yes	T21,T22,T32	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T1,T12,T17	Yes	T1,T12,T17	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	INPUT
intr_generic_rx_full_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_generic_rx_watermark_o	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
intr_generic_tx_watermark_o	Yes	Yes	T36,T54,T57	Yes	T36,T54,T57	OUTPUT
intr_generic_rx_error_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_generic_rx_overflow_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_generic_tx_underflow_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T98,T117,T118	Yes	T98,T117,T118	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T36,T57,T60	Yes	T36,T57,T60	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
sck_monitor_o	Yes	Yes	T18,T20,T24	Yes	T18,T20,T24	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	845	2	2	100.00
TERNARY	846	2	2	100.00
IF	443	2	2	100.00
IF	447	2	2	100.00
IF	480	2	2	100.00
IF	497	2	2	100.00
IF	737	3	3	100.00
IF	1095	4	4	100.00
IF	1121	3	3	100.00
IF	1164	2	2	100.00
CASE	1180	4	4	100.00
CASE	1227	8	6	75.00
IF	1304	5	4	80.00
IF	1338	2	2	100.00
IF	1986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	845	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T27
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	846	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T27
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	443	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	447	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	497	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	737	if ((!rst_ni))
-2-:	739	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T20,T24
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1095	if ((!tpm_rst_n))
-2-:	1096	if (spi_clk_csb_rst_pulse)
-3-:	1098	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T18,T19,T20
0	1	-	Covered	T31,T22,T51
0	0	1	Covered	T31,T22,T51
0	0	0	Covered	T31,T22,T51

	LineNo.	Expression
-1-:	1121	if ((!rst_ni))
-2-:	1122	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T31,T22,T51
0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1164	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	1180	case (cmd_dp_sel)
-2-:	1194	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T21,T25,T26
DpUpload	-	Covered	T21,T22,T23
default	1	Covered	T21,T22,T23
default	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1227	case (spi_mode)
-2-:	1246	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FwMode	-	Covered	T18,T20,T24
FlashMode PassThrough	DpNone	Covered	T18,T19,T20
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T21,T25,T26
FlashMode PassThrough	DpReadStatus	Covered	T21,T22,T32
FlashMode PassThrough	DpReadJEDEC	Covered	T21,T22,T23
FlashMode PassThrough	DpUpload	Covered	T21,T22,T23
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1304	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1311	case (spi_mode)
-3-:	1318	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T31,T22,T51
0	FwMode FlashMode	-	Covered	T18,T19,T20
0	PassThrough	1	Covered	T21,T22,T32
0	PassThrough	0	Covered	T21,T22,T32
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1338	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T20,T24

	LineNo.	Expression
-1-:	1986	if (((0 != j) && sys_sram_l2m[j].req))

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T18,T19,T20

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	27	27	100.00	26	96.30
Cover properties	0	0		0
Cover sequences	0	0		0
Total	27	27	100.00	26	96.30

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	2147483647	2147483647	0	0
CioSdoEnOKnown	2147483647	2147483647	0	0
CioSdoEnOffWhenInactive	2147483647	2147483647	0	0
CsPulseWidth_A	2147483647	2147483647	0	0
FpvSecCmRegWeOnehotCheck_A	2147483647	100	0	0
InterceptLevel_M	523662425	0	0	0
IntrReadbufFlipOKnown	2147483647	2147483647	0	0
IntrReadbufWatermarkOKnown	2147483647	2147483647	0	0
IntrRxerrOKnown	2147483647	2147483647	0	0
IntrRxfOKnown	2147483647	2147483647	0	0
IntrRxlvlOKnown	2147483647	2147483647	0	0
IntrRxoverflowOKnown	2147483647	2147483647	0	0
IntrTpmHeaderNotEmptyOKnown	2147483647	2147483647	0	0
IntrTxlvlOKnown	2147483647	2147483647	0	0
IntrTxunderflowOKnown	2147483647	2147483647	0	0
IntrUploadCmdfifoNotEmptyOKnown	2147483647	2147483647	0	0
IntrUploadPayloadNotEmptyOKnown	2147483647	2147483647	0	0
IntrUploadPayloadOverflowOKnown	2147483647	2147483647	0	0
PayloadStartIdxWidthMatch_A	1600	1600	0	0
SpiModeKnown_A	2147483647	2147483647	0	0
TpmEnableWhenTpmCsbIdle_M	2147483647	388	0	0
TpmRdfifoNotFull_A	2147483647	297216	0	0
TpmWrPtrMatch_A	1600	1600	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	2147483647	14548809	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	2147483647	4441	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	2147483647	3308	0	0
scanmodeKnown	2147483647	2147483647	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

CsPulseWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292414	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	55584	0	0
T50	1200	1138	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	100	0	0
T122	5697	20	0	0
T123	0	20	0	0
T124	0	20	0	0
T125	0	20	0	0
T126	0	20	0	0
T127	510588	0	0	0
T128	705453	0	0	0
T129	477085	0	0	0
T130	462839	0	0	0
T131	16456	0	0	0
T132	636124	0	0	0
T133	389127	0	0	0
T134	103524	0	0	0
T135	1320	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	523662425	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrRxerrOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrRxfOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrRxlvlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrRxoverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrTxlvlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrTxunderflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2033	0	0
T19	2243	2181	0	0
T20	220007	220001	0	0
T21	477085	477079	0	0
T24	292742	292736	0	0
T27	389127	389121	0	0
T28	389127	389121	0	0
T29	22370	22308	0	0
T31	788392	788330	0	0
T50	1200	1138	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	388	0	0
T21	477085	0	0	0
T22	658805	2	0	0
T23	0	1	0	0
T25	16456	0	0	0
T26	60875	0	0	0
T29	22370	0	0	0
T30	256348	0	0	0
T31	788392	1	0	0
T47	510588	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	1200	0	0	0
T81	1628	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

TpmRdfifoNotFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	297216	0	0
T21	477085	0	0	0
T22	658805	2443	0	0
T23	0	817	0	0
T25	16456	0	0	0
T26	60875	0	0	0
T29	22370	0	0	0
T30	256348	0	0	0
T31	788392	2469	0	0
T47	510588	0	0	0
T51	0	2469	0	0
T53	0	817	0	0
T55	1200	0	0	0
T81	1628	0	0	0
T137	0	46	0	0
T138	0	46	0	0
T140	0	46	0	0
T141	0	2469	0	0
T142	0	46	0	0

TpmWrPtrMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600	1600	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T50	1	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14548809	0	0
T18	2095	8	0	0
T19	2243	200	0	0
T20	220007	30693	0	0
T21	477085	18784	0	0
T24	292742	17752	0	0
T25	0	1024	0	0
T27	389127	26434	0	0
T28	389127	26434	0	0
T29	22370	176	0	0
T31	788392	0	0	0
T50	1200	3	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4441	0	0
T21	477085	15	0	0
T22	658805	15	0	0
T23	0	31	0	0
T25	16456	0	0	0
T26	60875	0	0	0
T29	22370	0	0	0
T30	256348	0	0	0
T35	0	15	0	0
T41	0	29	0	0
T42	0	15	0	0
T43	0	29	0	0
T44	0	15	0	0
T47	510588	0	0	0
T48	22370	0	0	0
T53	0	31	0	0
T55	1200	0	0	0
T66	0	31	0	0
T81	1628	0	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3308	0	0
T21	477085	9	0	0
T22	658805	11	0	0
T23	0	25	0	0
T25	16456	0	0	0
T26	60875	0	0	0
T29	22370	0	0	0
T30	256348	0	0	0
T35	0	9	0	0
T41	0	22	0	0
T42	0	11	0	0
T43	0	22	0	0
T44	0	9	0	0
T47	510588	0	0	0
T48	22370	0	0	0
T53	0	25	0	0
T55	1200	0	0	0
T66	0	25	0	0
T81	1628	0	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2095	2095	0	0
T19	2243	2243	0	0
T20	220007	220007	0	0
T21	477085	477085	0	0
T24	292742	292742	0	0
T27	389127	389127	0	0
T28	389127	389127	0	0
T29	22370	22370	0	0
T31	788392	788392	0	0
T50	1200	1200	0	0