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LINE 19656
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T36,T54,T57 |
| 1 | 1 | Covered | T36,T54,T57 |
LINE 19656
SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T36,T54,T57 |
| 1 | 1 | Covered | T36,T54,T57 |
LINE 19656
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T1,T14 |
LINE 19656
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[15] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T12 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[21] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T1,T12 |
LINE 19656
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T36,T54,T57 |
LINE 19656
SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T36,T54,T57 |
LINE 19656
SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[59] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[60] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[63] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[64] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[66] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[67] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[70] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T59,T1 |
LINE 19656
SUB-EXPRESSION (addr_hit[75] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T58,T59 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T12,T17,T98 |
| 1 | 1 | Covered | T54,T58,T59 |
LINE 19656
SUB-EXPRESSION (addr_hit[78] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | Covered | T54,T59,T1 |
| 1 | 1 | Covered | T54,T58,T1 |
LINE 19739
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T36,T54,T57 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T36,T54,T57 |
LINE 19762
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T36,T54,T57 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T36,T54,T57 |
LINE 19787
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T36,T54,T57 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T36,T57,T60 |
LINE 19812
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T58,T59 |
LINE 19815
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T54,T59,T1 |
LINE 19826
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T59,T1 |
LINE 19841
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T58,T59 |
LINE 19846
EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T54,T58,T59 |
LINE 19847
EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T54,T58,T59 |
LINE 19848
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T58,T59 |
LINE 19851
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T54,T59,T1 |
LINE 19854
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T59,T1 |
LINE 19859
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T59,T1 |
LINE 19864
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T36,T54,T57 |
| 1 | 0 | 1 | Covered | T54,T58,T59 |
| 1 | 1 | 0 | Covered | T5,T8,T82 |
| 1 | 1 | 1 | Covered | T54,T59,T1 |