Go
back
LINE 21096
EXPRESSION (addr_hit[76] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 21097
EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T7 |
| 1 | 0 | 1 | Covered | T1,T2,T9 |
| 1 | 1 | 0 | Covered | T2,T9,T18 |
| 1 | 1 | 1 | Covered | T30,T42,T46 |
LINE 21100
EXPRESSION (addr_hit[78] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T9 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T4,T5 |