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back
LINE 66
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T2 |
| 1 | 0 | Covered | T87,T106,T139 |
| 1 | 1 | Covered | T1,T2,T5 |
LINE 78
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T4,T2 |
| 0 | 1 | Covered | T109,T110,T111 |
| 1 | 0 | Covered | T87,T106,T139 |
LINE 85
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T4,T2 |
| 0 | 0 | 1 | Covered | T109,T110,T111 |
| 0 | 1 | 0 | Covered | T87,T106,T139 |
| 1 | 0 | 0 | Covered | T87,T106,T139 |
LINE 133
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:8191]}) ? 1'b0 : 1'b1)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T3 |
LINE 171
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T4,T2 |
| 0 | 0 | 1 | Covered | T87,T106,T139 |
| 0 | 1 | 0 | Covered | T141,T142,T144 |
| 1 | 0 | 0 | Covered | T141,T142,T144 |
LINE 171
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T87,T106,T139 |
LINE 19571
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_STATE_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 19572
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_ENABLE_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19573
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTR_TEST_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T83,T80,T81 |
LINE 19574
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ALERT_TEST_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19575
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CONTROL_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19576
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CFG_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19577
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_FIFO_LEVEL_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19578
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T2,T5,T9 |
LINE 19579
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_STATUS_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19580
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_RXF_PTR_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T2,T5,T9 |
LINE 19581
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TXF_PTR_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19582
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_RXF_ADDR_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19583
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TXF_ADDR_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T2,T5 |
LINE 19584
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_INTERCEPT_EN_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19585
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_LAST_READ_ADDR_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19586
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_FLASH_STATUS_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19587
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_CC_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19588
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_JEDEC_ID_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19589
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_READ_THRESHOLD_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19590
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_MAILBOX_ADDR_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19591
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19592
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_STATUS2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19593
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19594
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19595
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19596
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19597
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19598
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19599
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19600
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19601
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19602
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_FILTER_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19603
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_MASK_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19604
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_ADDR_SWAP_DATA_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19605
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19606
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19607
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19608
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19609
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19610
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19611
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19612
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19613
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19614
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19615
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_8_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19616
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_9_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19617
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_10_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19618
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_11_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19619
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19620
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19621
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19622
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19623
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_16_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19624
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_17_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19625
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_18_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19626
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_19_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19627
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_20_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19628
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_21_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19629
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_22_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19630
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_23_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19631
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EN4B_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19632
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_EX4B_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T17,T80,T81 |
LINE 19633
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WREN_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19634
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_CMD_INFO_WRDI_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19635
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CAP_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19636
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CFG_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19637
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STATUS_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19638
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19639
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_ACCESS_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19640
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_STS_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19641
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19642
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_ENABLE_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19643
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_VECTOR_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19644
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_INT_STATUS_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19645
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_DID_VID_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19646
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_RID_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T22,T80,T81 |
LINE 19647
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_CMD_ADDR_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19648
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_READ_FIFO_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19649
EXPRESSION (reg_addr == spi_device_reg_pkg::SPI_DEVICE_TPM_WRITE_FIFO_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T80,T81,T82 |
LINE 19652
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T2 |
| 1 | Covered | T1,T4,T2 |
LINE 19652
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T4,T2 |
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T1,T4,T2 |
LINE 19656
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[64] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T5,T9 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T87,T141,T142 |
LINE 19656
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b0111 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b0111 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) |
44 (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) |
45 (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) |
46 (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) |
47 (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) |
48 (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) |
49 (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) |
50 (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) |
51 (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) |
52 (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) |
53 (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) |
54 (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) |
55 (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) |
56 (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) |
57 (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) |
58 (addr_hit[57] & ((|(4'b1111 & (~reg_be))))) |
59 (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) |
60 (addr_hit[59] & ((|(4'b1111 & (~reg_be))))) |
61 (addr_hit[60] & ((|(4'b1111 & (~reg_be))))) |
62 (addr_hit[61] & ((|(4'b1111 & (~reg_be))))) |
63 (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) |
64 (addr_hit[63] & ((|(4'b1111 & (~reg_be))))) |
65 (addr_hit[64] & ((|(4'b0111 & (~reg_be))))) |
66 (addr_hit[65] & ((|(4'b1 & (~reg_be))))) |
67 (addr_hit[66] & ((|(4'b0111 & (~reg_be))))) |
68 (addr_hit[67] & ((|(4'b1111 & (~reg_be))))) |
69 (addr_hit[68] & ((|(4'b1 & (~reg_be))))) |
70 (addr_hit[69] & ((|(4'b1111 & (~reg_be))))) |
71 (addr_hit[70] & ((|(4'b1111 & (~reg_be))))) |
72 (addr_hit[71] & ((|(4'b1111 & (~reg_be))))) |
73 (addr_hit[72] & ((|(4'b1 & (~reg_be))))) |
74 (addr_hit[73] & ((|(4'b1111 & (~reg_be))))) |
75 (addr_hit[74] & ((|(4'b1111 & (~reg_be))))) |
76 (addr_hit[75] & ((|(4'b1 & (~reg_be))))) |
77 (addr_hit[76] & ((|(4'b1111 & (~reg_be))))) |
78 (addr_hit[77] & ((|(4'b1111 & (~reg_be))))) |
79 (addr_hit[78] & ((|(4'b1 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T1,T4,T2 |
| 79 (addr_hit[78] & ((|(4'... | Covered | T82,T106,T139 |
| 78 (addr_hit[77] & ((|(4'... | Covered | T80,T82,T87 |
| 77 (addr_hit[76] & ((|(4'... | Covered | T80,T82,T87 |
| 76 (addr_hit[75] & ((|(4'... | Covered | T82,T87,T106 |
| 75 (addr_hit[74] & ((|(4'... | Covered | T87,T106,T139 |
| 74 (addr_hit[73] & ((|(4'... | Covered | T82,T87,T106 |
| 73 (addr_hit[72] & ((|(4'... | Covered | T80,T82,T87 |
| 72 (addr_hit[71] & ((|(4'... | Covered | T80,T82,T87 |
| 71 (addr_hit[70] & ((|(4'... | Covered | T82,T87,T106 |
| 70 (addr_hit[69] & ((|(4'... | Covered | T80,T87,T106 |
| 69 (addr_hit[68] & ((|(4'... | Covered | T82,T87,T106 |
| 68 (addr_hit[67] & ((|(4'... | Covered | T80,T82,T87 |
| 67 (addr_hit[66] & ((|(4'... | Covered | T80,T87,T106 |
| 66 (addr_hit[65] & ((|(4'... | Covered | T82,T87,T106 |
| 65 (addr_hit[64] & ((|(4'... | Covered | T87,T106,T139 |
| 64 (addr_hit[63] & ((|(4'... | Covered | T80,T82,T87 |
| 63 (addr_hit[62] & ((|(4'... | Covered | T82,T87,T106 |
| 62 (addr_hit[61] & ((|(4'... | Covered | T82,T87,T106 |
| 61 (addr_hit[60] & ((|(4'... | Covered | T80,T87,T106 |
| 60 (addr_hit[59] & ((|(4'... | Covered | T80,T82,T87 |
| 59 (addr_hit[58] & ((|(4'... | Covered | T80,T82,T87 |
| 58 (addr_hit[57] & ((|(4'... | Covered | T80,T82,T87 |
| 57 (addr_hit[56] & ((|(4'... | Covered | T80,T82,T87 |
| 56 (addr_hit[55] & ((|(4'... | Covered | T80,T87,T106 |
| 55 (addr_hit[54] & ((|(4'... | Covered | T80,T87,T106 |
| 54 (addr_hit[53] & ((|(4'... | Covered | T80,T82,T87 |
| 53 (addr_hit[52] & ((|(4'... | Covered | T87,T106,T139 |
| 52 (addr_hit[51] & ((|(4'... | Covered | T80,T82,T87 |
| 51 (addr_hit[50] & ((|(4'... | Covered | T80,T87,T106 |
| 50 (addr_hit[49] & ((|(4'... | Covered | T80,T87,T106 |
| 49 (addr_hit[48] & ((|(4'... | Covered | T82,T87,T106 |
| 48 (addr_hit[47] & ((|(4'... | Covered | T82,T87,T106 |
| 47 (addr_hit[46] & ((|(4'... | Covered | T82,T87,T106 |
| 46 (addr_hit[45] & ((|(4'... | Covered | T82,T87,T106 |
| 45 (addr_hit[44] & ((|(4'... | Covered | T80,T82,T87 |
| 44 (addr_hit[43] & ((|(4'... | Covered | T80,T82,T87 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T82,T87,T106 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T80,T87,T106 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T82,T87,T106 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T80,T82,T87 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T80,T82,T87 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T80,T82,T87 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T82,T87,T106 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T80,T82,T87 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T80,T82,T87 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T82,T87,T106 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T80,T82,T87 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T80,T82,T87 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T80,T87,T106 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T80,T82,T87 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T80,T82,T87 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T82,T87,T106 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T80,T82,T87 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T80,T82,T87 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T80,T82,T87 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T80,T82,T87 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T82,T87,T106 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T80,T82,T87 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T80,T82,T87 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T82,T87,T106 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T80,T82,T87 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T80,T82,T87 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T80,T82,T87 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T17,T80,T87 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T17,T80,T82 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T80,T87,T106 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T80,T82,T87 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T80,T82,T87 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T2,T5,T9 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T2,T5,T9 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T87,T106,T139 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T2,T5,T9 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T82,T87,T106 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T82,T87,T106 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T82,T87,T106 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T80,T87,T106 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T83,T80,T84 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T83,T84,T82 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T2,T5,T9 |
LINE 19656
SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T4,T2 |
| 1 | 1 | Covered | T2,T5,T9 |
LINE 19656
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T83,T84,T82 |
LINE 19656
SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T83,T81,T84 |
| 1 | 1 | Covered | T83,T80,T84 |
LINE 19656
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T80,T81,T82 |
| 1 | 1 | Covered | T80,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T82,T87 |
| 1 | 1 | Covered | T2,T5,T9 |
LINE 19656
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T87,T106,T139 |
LINE 19656
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T9 |
| 1 | 1 | Covered | T2,T5,T9 |
LINE 19656
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T2,T5,T9 |
LINE 19656
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T5 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T80,T81,T82 |
| 1 | 1 | Covered | T17,T80,T82 |
LINE 19656
SUB-EXPRESSION (addr_hit[15] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T82,T87 |
| 1 | 1 | Covered | T17,T80,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T82,T87 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[21] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T82,T87 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T80,T81,T82 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T82,T87 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T80,T81 |
| 1 | 1 | Covered | T82,T87,T106 |
LINE 19656
SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |
LINE 19656
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T17,T81,T82 |
| 1 | 1 | Covered | T80,T82,T87 |