Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7439342	1			T4	23		T5	1		T1	2
all_values[1]	7439342	1			T4	23		T5	1		T1	2
all_values[2]	7439342	1			T4	23		T5	1		T1	2
all_values[3]	7439342	1			T4	23		T5	1		T1	2
all_values[4]	7439342	1			T4	23		T5	1		T1	2
all_values[5]	7439342	1			T4	23		T5	1		T1	2
all_values[6]	7439342	1			T4	23		T5	1		T1	2
all_values[7]	7439342	1			T4	23		T5	1		T1	2
all_values[8]	7439342	1			T4	23		T5	1		T1	2
all_values[9]	7439342	1			T4	23		T5	1		T1	2
all_values[10]	7439342	1			T4	23		T5	1		T1	2
all_values[11]	7439342	1			T4	23		T5	1		T1	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86089080

1

T4

276

T5

12

T1

8

auto[1]

3183024

1

T1

16

T2

10

T8

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89209013

1

T4

274

T5

12

T1

24

auto[1]

63091

1

T4

2

T3

515

T15

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7156875	1			T4	23		T5	1		T3	252025
all_values[0]	auto[0]	auto[1]	78	1			T65	1		T66	3		T83	3
all_values[0]	auto[1]	auto[0]	282272	1			T1	2		T2	2		T65	2
all_values[0]	auto[1]	auto[1]	117	1			T65	5		T66	3		T67	3
all_values[1]	auto[0]	auto[0]	7306781	1			T4	23		T5	1		T1	2
all_values[1]	auto[0]	auto[1]	109	1			T65	5		T66	1		T67	2
all_values[1]	auto[1]	auto[0]	132342	1			T2	2		T8	2		T65	1
all_values[1]	auto[1]	auto[1]	110	1			T65	3		T66	5		T67	3
all_values[2]	auto[0]	auto[0]	7359823	1			T4	23		T5	1		T2	2
all_values[2]	auto[0]	auto[1]	96	1			T65	5		T66	4		T67	4
all_values[2]	auto[1]	auto[0]	79311	1			T1	2		T8	2		T65	2
all_values[2]	auto[1]	auto[1]	112	1			T65	3		T66	4		T67	5
all_values[3]	auto[0]	auto[0]	7091357	1			T4	23		T5	1		T2	2
all_values[3]	auto[0]	auto[1]	90	1			T65	4		T66	2		T67	1
all_values[3]	auto[1]	auto[0]	347787	1			T1	2		T8	2		T34	2
all_values[3]	auto[1]	auto[1]	108	1			T65	3		T83	3		T130	2
all_values[4]	auto[0]	auto[0]	7405562	1			T4	23		T5	1		T3	252025
all_values[4]	auto[0]	auto[1]	107	1			T65	5		T66	2		T67	4
all_values[4]	auto[1]	auto[0]	33565	1			T1	2		T2	2		T8	2
all_values[4]	auto[1]	auto[1]	108	1			T65	3		T66	3		T67	2
all_values[5]	auto[0]	auto[0]	7111820	1			T4	23		T5	1		T1	2
all_values[5]	auto[0]	auto[1]	113	1			T65	3		T66	5		T67	6
all_values[5]	auto[1]	auto[0]	327315	1			T8	2		T34	2		T66	4
all_values[5]	auto[1]	auto[1]	94	1			T65	4		T66	1		T83	1
all_values[6]	auto[0]	auto[0]	7243095	1			T4	23		T5	1		T2	2
all_values[6]	auto[0]	auto[1]	36259	1			T3	348		T6	304		T65	3
all_values[6]	auto[1]	auto[0]	158888	1			T1	2		T34	2		T65	1
all_values[6]	auto[1]	auto[1]	1100	1			T65	6		T67	3		T83	5
all_values[7]	auto[0]	auto[0]	6992607	1			T4	23		T5	1		T1	2
all_values[7]	auto[0]	auto[1]	16384	1			T3	101		T6	91		T66	3
all_values[7]	auto[1]	auto[0]	429359	1			T65	4		T66	3		T67	3
all_values[7]	auto[1]	auto[1]	992	1			T65	1		T66	1		T67	4
all_values[8]	auto[0]	auto[0]	7006025	1			T4	23		T5	1		T1	2
all_values[8]	auto[0]	auto[1]	6003	1			T3	66		T6	29		T65	1
all_values[8]	auto[1]	auto[0]	427063	1			T2	2		T34	2		T65	3
all_values[8]	auto[1]	auto[1]	251	1			T65	3		T66	1		T67	2
all_values[9]	auto[0]	auto[0]	6961103	1			T4	23		T5	1		T2	2
all_values[9]	auto[0]	auto[1]	117	1			T65	5		T66	2		T67	2
all_values[9]	auto[1]	auto[0]	478008	1			T1	2		T8	2		T34	2
all_values[9]	auto[1]	auto[1]	114	1			T65	3		T66	1		T67	7
all_values[10]	auto[0]	auto[0]	7409561	1			T4	23		T5	1		T2	2
all_values[10]	auto[0]	auto[1]	106	1			T65	4		T66	4		T67	2
all_values[10]	auto[1]	auto[0]	29564	1			T1	2		T65	1		T67	2
all_values[10]	auto[1]	auto[1]	111	1			T65	4		T66	5		T67	3
all_values[11]	auto[0]	auto[0]	6984698	1			T4	21		T5	1		T3	252025
all_values[11]	auto[0]	auto[1]	311	1			T4	2		T15	6		T65	1
all_values[11]	auto[1]	auto[0]	454232	1			T1	2		T2	2		T8	2
all_values[11]	auto[1]	auto[1]	101	1			T65	4		T66	3		T67	1