Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3413222

1

T2

103

T9

33

T10

8712

auto[1]

3846579

1

T9

34

T10

5271

T13

1626

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3724328

1

T9

21

T10

8712

T45

6541

auto[1]

3535473

1

T2

103

T9

46

T10

5271

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4115417

1

T2

103

T9

38

T10

5271

auto[1]

3144384

1

T9

29

T10

8712

T13

1626

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3653788

1

T2

103

T9

42

T10

13983

auto[1]

3606013

1

T9

25

T13

1043

T33

21611

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3653788

1

T2

103

T9

42

T10

13983

auto[1]

3606013

1

T9

25

T13

1043

T33

21611

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3413222

1

T2

103

T9

33

T10

8712

auto[1]

3846579

1

T9

34

T10

5271

T13

1626

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

575675

1

T9

6

T61

65

T62

299

auto[0]

auto[0]

auto[0]

auto[1]

453829

1

T2

103

T9

9

T163

339

auto[0]

auto[0]

auto[1]

auto[0]

392987

1

T10

8712

T45

6541

T47

69

auto[0]

auto[0]

auto[1]

auto[1]

368865

1

T9

5

T33

45539

T198

5938

auto[0]

auto[1]

auto[0]

auto[0]

519217

1

T9

3

T111

12550

T199

7

auto[0]

auto[1]

auto[0]

auto[1]

454598

1

T9

4

T39

53

T40

7326

auto[0]

auto[1]

auto[1]

auto[0]

308877

1

T9

1

T200

1216

T199

5

auto[0]

auto[1]

auto[1]

auto[1]

339174

1

T9

5

T33

21611

T7

6787

auto[1]

auto[0]

auto[0]

auto[0]

702276

1

T9

2

T7

6517

T201

1091

auto[1]

auto[0]

auto[0]

auto[1]

376897

1

T9

3

T10

5271

T45

8064

auto[1]

auto[0]

auto[1]

auto[0]

347129

1

T9

9

T40

4423

T201

4256

auto[1]

auto[0]

auto[1]

auto[1]

436130

1

T9

8

T13

583

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

482351

1

T199

8

T52

573

T202

10

auto[1]

auto[1]

auto[0]

auto[1]

550574

1

T9

11

T48

4417

T62

697

auto[1]

auto[1]

auto[1]

auto[0]

395816

1

T199

7

T52

540

T72

12

auto[1]

auto[1]

auto[1]

auto[1]

555406

1

T9

1

T13

1043

T203

6321