Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37618	1			T3	166		T6	366		T12	12
auto[SpiFlashAddrCfg]	8063	1			T3	85		T6	70		T16	4
auto[SpiFlashAddr3b]	9908	1			T3	98		T6	74		T16	8
auto[SpiFlashAddr4b]	8274	1			T3	68		T11	11		T6	83

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37361

1

T3

264

T11

11

T6

329

auto[1]

26502

1

T3

153

T6

264

T16

30

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33937

1

T3

215

T11

7

T6

389

auto[1]

29926

1

T3

202

T11

4

T6

204

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42702	1			T3	212		T6	418		T12	12
values[1]	1228	1			T3	18		T6	19		T7	1
values[2]	1603	1			T3	20		T6	11		T7	5
values[3]	1538	1			T3	28		T6	18		T16	4
values[4]	1488	1			T3	19		T6	12		T7	3
values[5]	1576	1			T3	10		T11	1		T6	9
values[6]	1515	1			T3	16		T6	9		T7	7
values[7]	1546	1			T3	12		T6	18		T7	1
values[8]	10667	1			T3	82		T11	10		T6	79

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30258

1

T3

417

T12

12

T16

30

auto[1]

33605

1

T11

11

T6

593

T7

145

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

61583

1

T3

402

T11

11

T6

574

write

2280

1

T3

15

T6

19

T7

9

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

21127

1

T3

185

T11

10

T6

178

valids[0x1]

42736

1

T3

232

T11

1

T6

415

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1748	1			T3	16		T6	15		T7	4
internal_process_ops[0x5a]	1709	1			T3	19		T6	16		T7	5
internal_process_ops[0x05]	22801	1			T3	46		T6	233		T7	30
internal_process_ops[0x35]	1674	1			T3	14		T6	14		T7	5
internal_process_ops[0x15]	1621	1			T3	15		T6	13		T7	5
internal_process_ops[0x03]	1212	1			T3	13		T11	1		T6	5
internal_process_ops[0x0b]	1157	1			T3	15		T6	11		T7	3
internal_process_ops[0x3b]	1198	1			T3	15		T11	4		T6	7
internal_process_ops[0x6b]	1164	1			T3	17		T11	6		T6	4
internal_process_ops[0xbb]	1176	1			T3	12		T6	8		T7	3
internal_process_ops[0xeb]	1194	1			T3	11		T6	8		T38	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62727

1

T3

407

T11

11

T6

578

auto[1]

1136

1

T3

10

T6

15

T7

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61708

1

T3

403

T11

11

T6

571

auto[1]

2155

1

T3

14

T6

22

T7

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10720

1

T3

116

T12

12

T17

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5460

1

T3

46

T16

14

T18

70

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2177

1

T3

52

T18

30

T21

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1823

1

T3

29

T16

4

T18

26

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2640

1

T3

53

T17

4

T18

39

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2296

1

T3

41

T16

8

T18

49

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2199

1

T3

35

T18

20

T22

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1905

1

T3

30

T16

4

T18

23

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T18

1

T19

1

T20

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

62

1

T3

2

T18

1

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

58

1

T187

5

T29

2

T188

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T3

2

T23

3

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

65

1

T3

2

T18

1

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T3

1

T18

3

T30

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T20

3

T26

2

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T3

1

T23

6

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

67

1

T18

1

T23

2

T189

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

54

1

T3

1

T27

2

T29

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

60

1

T3

2

T23

1

T128

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

64

1

T3

1

T18

2

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T3

1

T18

1

T27

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

41

1

T3

1

T18

1

T23

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

63

1

T18

1

T23

2

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

62

1

T3

1

T18

2

T26

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12555

1

T6

213

T7

60

T38

211

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8316

1

T6

147

T7

16

T38

112

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1819

1

T6

43

T7

6

T38

52

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1688

1

T6

23

T7

11

T38

51

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2231

1

T6

33

T7

9

T38

43

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2174

1

T6

33

T7

15

T38

40

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1860

1

T11

11

T6

36

T7

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1720

1

T6

46

T7

14

T38

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

84

1

T38

1

T26

1

T190

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T6

2

T7

2

T38

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

62

1

T6

1

T38

3

T55

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T6

3

T46

1

T191

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

57

1

T192

1

T55

1

T193

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

79

1

T38

2

T26

5

T27

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

86

1

T6

1

T38

2

T46

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

69

1

T6

3

T38

2

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

69

1

T6

1

T46

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

72

1

T6

1

T46

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T6

1

T46

2

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T6

5

T7

2

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

78

1

T7

1

T46

2

T26

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T7

1

T38

4

T46

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T38

1

T26

2

T27

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T6

1

T7

3

T26

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4150	1			T3	64		T12	12		T18	77
auto[0]	values[0]	valids[0x1]	14883	1			T3	148		T16	8		T17	12
auto[0]	values[1]	valids[0x1]	608	1			T3	18		T18	12		T19	3
auto[0]	values[2]	valids[0x0]	584	1			T3	14		T18	5		T20	1
auto[0]	values[2]	valids[0x1]	263	1			T3	6		T18	6		T19	1
auto[0]	values[3]	valids[0x0]	555	1			T3	23		T18	14		T22	2
auto[0]	values[3]	valids[0x1]	295	1			T3	5		T16	4		T18	6
auto[0]	values[4]	valids[0x0]	509	1			T3	8		T18	8		T19	4
auto[0]	values[4]	valids[0x1]	296	1			T3	11		T18	6		T19	4
auto[0]	values[5]	valids[0x0]	575	1			T18	5		T19	9		T20	3
auto[0]	values[5]	valids[0x1]	319	1			T3	10		T18	3		T19	1
auto[0]	values[6]	valids[0x0]	520	1			T3	12		T18	2		T19	3
auto[0]	values[6]	valids[0x1]	288	1			T3	4		T18	6		T20	2
auto[0]	values[7]	valids[0x0]	524	1			T3	5		T18	5		T19	1
auto[0]	values[7]	valids[0x1]	267	1			T3	7		T18	10		T20	1
auto[0]	values[8]	valids[0x0]	3580	1			T3	59		T16	12		T18	51
auto[0]	values[8]	valids[0x1]	2042	1			T3	23		T16	6		T18	27
auto[1]	values[0]	valids[0x0]	4650	1			T6	85		T7	33		T38	84
auto[1]	values[0]	valids[0x1]	19019	1			T6	333		T7	67		T38	305
auto[1]	values[1]	valids[0x1]	620	1			T6	19		T7	1		T38	7
auto[1]	values[2]	valids[0x0]	438	1			T6	6		T7	3		T38	3
auto[1]	values[2]	valids[0x1]	318	1			T6	5		T7	2		T38	14
auto[1]	values[3]	valids[0x0]	433	1			T6	7		T7	1		T38	7
auto[1]	values[3]	valids[0x1]	255	1			T6	11		T38	8		T32	8
auto[1]	values[4]	valids[0x0]	419	1			T6	10		T7	3		T38	10
auto[1]	values[4]	valids[0x1]	264	1			T6	2		T38	4		T46	4
auto[1]	values[5]	valids[0x0]	404	1			T6	4		T7	1		T38	9
auto[1]	values[5]	valids[0x1]	278	1			T11	1		T6	5		T38	2
auto[1]	values[6]	valids[0x0]	423	1			T6	4		T7	5		T38	10
auto[1]	values[6]	valids[0x1]	284	1			T6	5		T7	2		T38	4
auto[1]	values[7]	valids[0x0]	426	1			T6	14		T7	1		T38	11
auto[1]	values[7]	valids[0x1]	329	1			T6	4		T38	4		T46	3
auto[1]	values[8]	valids[0x0]	2937	1			T11	10		T6	48		T7	18
auto[1]	values[8]	valids[0x1]	2108	1			T6	31		T7	8		T38	40