Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19266

1

T5

1

T3

145

T11

11

auto[1]

21065

1

T3

37

T6

213

T7

25

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14545

1

T5

1

T3

107

T11

11

auto[1]

25786

1

T3

75

T6

260

T7

40

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	5958	1			T5	1		T3	24		T11	1
auto[524288:1048575]	4904	1			T3	21		T11	5		T6	32
auto[1048576:1572863]	4717	1			T3	10		T6	59		T12	4
auto[1572864:2097151]	4586	1			T3	19		T6	51		T12	1
auto[2097152:2621439]	4807	1			T3	19		T6	51		T12	1
auto[2621440:3145727]	5463	1			T3	37		T6	33		T7	22
auto[3145728:3670015]	5238	1			T3	17		T11	3		T6	108
auto[3670016:4194303]	4658	1			T3	35		T11	2		T6	11

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39706

1

T5

1

T3

181

T11

11

auto[1]

625

1

T3

1

T6

14

T38

11

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21716

1

T5

1

T3

90

T11

2

auto[1]

18615

1

T3

92

T11

9

T6

232

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1289	1			T5	1		T3	2		T11	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	717	1			T3	1		T6	1		T7	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	807	1			T3	8		T6	5		T12	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	420	1			T3	7		T6	2		T38	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	779	1			T3	4		T6	5		T12	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	388	1			T3	1		T6	3		T38	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	698	1			T3	12		T6	8		T12	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	421	1			T3	5		T6	6		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	792	1			T3	8		T6	1		T7	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	446	1			T3	2		T7	3		T38	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	734	1			T3	11		T6	4		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	411	1			T3	4		T6	6		T7	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	784	1			T3	4		T6	9		T7	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	442	1			T3	1		T6	9		T7	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	767	1			T3	4		T11	1		T6	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	462	1			T3	2		T6	2		T7	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	687	1			T3	11		T6	5		T7	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	392	1			T3	8		T6	3		T38	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	698	1			T11	5		T6	6		T38	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	415	1			T3	1		T6	2		T38	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	733	1			T3	1		T6	15		T12	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	399	1			T6	10		T38	1		T18	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	753	1			T6	3		T38	15		T18	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	391	1			T6	4		T38	7		T18	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	691	1			T3	4		T6	14		T12	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	349	1			T3	3		T6	7		T7	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	760	1			T3	10		T6	8		T7	7
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	447	1			T3	7		T6	6		T7	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	727	1			T3	4		T11	3		T6	8
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	376	1			T3	3		T6	7		T38	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	691	1			T3	10		T11	1		T6	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	400	1			T3	7		T6	1		T38	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	177	1			T6	1		T7	1		T38	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1733	1			T6	2		T7	3		T38	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	143	1			T3	2		T38	1		T18	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1083	1			T3	3		T38	2		T18	49
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	133	1			T3	1		T6	1		T18	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1221	1			T3	3		T6	21		T18	20
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	124	1			T3	1		T6	2		T7	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1043	1			T3	1		T6	26		T7	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	156	1			T7	1		T38	3		T18	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1272	1			T7	2		T38	48		T18	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	132	1			T7	1		T20	4		T23	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1318	1			T7	1		T20	53		T23	36
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	166	1			T3	1		T6	2		T7	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1327	1			T3	2		T6	29		T7	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	140	1			T38	1		T18	2		T19	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1191	1			T38	1		T18	4		T19	23
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T3	1		T6	1		T38	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	860	1			T3	1		T6	21		T38	21
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	132	1			T6	2		T38	1		T18	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1206	1			T6	15		T38	3		T18	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	134	1			T6	2		T18	1		T46	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	930	1			T6	2		T18	8		T46	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	116	1			T6	1		T38	6		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1040	1			T6	1		T38	48		T18	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	102	1			T3	1		T6	3		T7	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	999	1			T3	1		T6	26		T7	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	147	1			T3	2		T6	1		T7	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1514	1			T3	3		T6	8		T7	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	134	1			T3	1		T6	5		T18	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1282	1			T3	1		T6	39		T18	20
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	116	1			T3	4		T6	1		T38	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	891	1			T3	8		T6	1		T38	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	10258	1			T5	1		T3	76		T11	2
auto[0]	auto[0]	auto[1]	99	1			T6	1		T38	1		T18	1
auto[0]	auto[1]	auto[0]	8829	1			T3	69		T11	9		T6	100
auto[0]	auto[1]	auto[1]	80	1			T6	3		T38	1		T18	1
auto[1]	auto[0]	auto[0]	11118	1			T3	13		T6	81		T7	18
auto[1]	auto[0]	auto[1]	241	1			T3	1		T6	3		T38	2
auto[1]	auto[1]	auto[0]	9501	1			T3	23		T6	122		T7	7
auto[1]	auto[1]	auto[1]	205	1			T6	7		T38	7		T18	5