Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_rx_fifo_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_rx_size	8	1	7	87.50	100	1	1	0

Summary for Variable cp_rx_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_rx_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
specific_sizes[4092]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
specific_sizes[4]	64425	1			T13	1627		T176	2497		T177	3228
specific_sizes[2048]	1	1			T178	1		-	-		-	-
sizes[0]	86525	1			T13	1627		T40	441		T48	5
sizes[1]	6203	1			T59	50		T111	263		T53	330
sizes[2]	1910	1			T179	7		T180	158		T54	97
sizes[3]	420	1			T181	19		T182	28		T183	42
sizes[4]	324	1			T33	78		T184	22		T185	49