Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18281

1

T3

264

T12

12

T17

12

auto[1]

11977

1

T3

153

T16

30

T18

173

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3649	1			T3	42		T18	113		T19	20
values[1]	4074	1			T3	23		T18	76		T19	81
values[2]	4034	1			T3	42		T18	20		T19	20
values[3]	3661	1			T3	106		T17	12		T18	45
values[4]	3758	1			T3	31		T18	66		T21	2
values[5]	3674	1			T3	62		T18	176		T20	77
values[6]	3880	1			T3	64		T16	30		T19	20
values[7]	3528	1			T3	47		T12	12		T18	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4010	1			T3	22		T18	24		T21	2
values[1]	3638	1			T3	157		T18	72		T19	40
values[2]	3867	1			T3	22		T17	12		T18	86
values[3]	3426	1			T3	65		T18	45		T19	81
values[4]	3417	1			T3	66		T18	33		T19	20
values[5]	3960	1			T3	43		T12	12		T18	80
values[6]	3871	1			T3	20		T16	30		T18	138
values[7]	4069	1			T3	22		T18	41		T23	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	335	1			T187	11		T211	11		T238	10
auto[0]	values[0]	values[1]	335	1			T3	19		T18	40		T19	13
auto[0]	values[0]	values[2]	371	1			T3	12		T18	13		T23	9
auto[0]	values[0]	values[3]	246	1			T30	49		T232	48		T206	40
auto[0]	values[0]	values[4]	157	1			T232	13		T127	8		T206	5
auto[0]	values[0]	values[5]	311	1			T187	13		T266	18		T267	10
auto[0]	values[0]	values[6]	179	1			T18	15		T26	11		T188	10
auto[0]	values[0]	values[7]	272	1			T187	15		T30	24		T128	24
auto[0]	values[1]	values[0]	172	1			T20	10		T128	8		T220	10
auto[0]	values[1]	values[1]	376	1			T3	12		T27	18		T128	9
auto[0]	values[1]	values[2]	294	1			T27	12		T223	12		T232	52
auto[0]	values[1]	values[3]	315	1			T19	73		T206	11		T220	6
auto[0]	values[1]	values[4]	240	1			T232	35		T211	6		T268	14
auto[0]	values[1]	values[5]	164	1			T235	6		T269	4		T270	9
auto[0]	values[1]	values[6]	419	1			T18	69		T23	170		T271	2
auto[0]	values[1]	values[7]	270	1			T23	25		T27	15		T30	31
auto[0]	values[2]	values[0]	373	1			T23	117		T30	64		T236	25
auto[0]	values[2]	values[1]	158	1			T19	12		T23	48		T127	11
auto[0]	values[2]	values[2]	306	1			T20	15		T224	18		T127	36
auto[0]	values[2]	values[3]	198	1			T249	12		T187	15		T29	10
auto[0]	values[2]	values[4]	145	1			T3	12		T235	11		T238	11
auto[0]	values[2]	values[5]	527	1			T128	25		T212	29		T188	174
auto[0]	values[2]	values[6]	509	1			T3	10		T18	11		T272	131
auto[0]	values[2]	values[7]	258	1			T273	28		T232	16		T188	13
auto[0]	values[3]	values[0]	361	1			T19	15		T27	74		T212	15
auto[0]	values[3]	values[1]	240	1			T3	30		T23	7		T206	29
auto[0]	values[3]	values[2]	298	1			T17	12		T18	31		T20	63
auto[0]	values[3]	values[3]	346	1			T3	13		T20	11		T29	28
auto[0]	values[3]	values[4]	275	1			T23	11		T27	12		T189	16
auto[0]	values[3]	values[5]	242	1			T3	22		T20	10		T115	30
auto[0]	values[3]	values[6]	268	1			T27	11		T30	45		T128	12
auto[0]	values[3]	values[7]	237	1			T128	14		T207	12		T231	28
auto[0]	values[4]	values[0]	406	1			T18	15		T21	2		T23	10
auto[0]	values[4]	values[1]	304	1			T3	23		T18	12		T20	13
auto[0]	values[4]	values[2]	248	1			T23	6		T27	11		T128	11
auto[0]	values[4]	values[3]	256	1			T240	26		T27	52		T219	18
auto[0]	values[4]	values[4]	276	1			T19	6		T23	9		T128	12
auto[0]	values[4]	values[5]	226	1			T29	10		T128	10		T212	15
auto[0]	values[4]	values[6]	264	1			T18	16		T22	6		T274	22
auto[0]	values[4]	values[7]	284	1			T275	22		T29	16		T235	10
auto[0]	values[5]	values[0]	239	1			T27	11		T276	4		T212	9
auto[0]	values[5]	values[1]	215	1			T3	17		T20	8		T26	6
auto[0]	values[5]	values[2]	463	1			T210	10		T30	128		T128	11
auto[0]	values[5]	values[3]	149	1			T3	26		T18	14		T187	15
auto[0]	values[5]	values[4]	285	1			T18	9		T277	4		T206	7
auto[0]	values[5]	values[5]	339	1			T18	60		T278	8		T30	11
auto[0]	values[5]	values[6]	283	1			T207	19		T279	20		T222	62
auto[0]	values[5]	values[7]	245	1			T18	31		T27	10		T30	10
auto[0]	values[6]	values[0]	467	1			T3	13		T114	14		T280	14
auto[0]	values[6]	values[1]	257	1			T30	13		T128	12		T207	27
auto[0]	values[6]	values[2]	221	1			T27	12		T281	26		T128	11
auto[0]	values[6]	values[3]	219	1			T127	13		T206	12		T236	15
auto[0]	values[6]	values[4]	254	1			T3	16		T239	20		T128	10
auto[0]	values[6]	values[5]	354	1			T19	13		T29	16		T127	11
auto[0]	values[6]	values[6]	272	1			T187	17		T282	8		T254	19
auto[0]	values[6]	values[7]	407	1			T3	10		T283	10		T284	4
auto[0]	values[7]	values[0]	248	1			T27	8		T188	29		T235	39
auto[0]	values[7]	values[1]	252	1			T3	16		T285	4		T286	26
auto[0]	values[7]	values[2]	175	1			T29	6		T287	22		T242	13
auto[0]	values[7]	values[3]	276	1			T18	10		T23	11		T29	11
auto[0]	values[7]	values[4]	198	1			T3	13		T27	12		T288	4
auto[0]	values[7]	values[5]	503	1			T12	12		T23	11		T204	22
auto[0]	values[7]	values[6]	224	1			T28	14		T211	16		T289	4
auto[0]	values[7]	values[7]	275	1			T236	9		T220	11		T235	37
auto[1]	values[0]	values[0]	217	1			T187	9		T211	15		T238	10
auto[1]	values[0]	values[1]	118	1			T3	1		T18	12		T19	7
auto[1]	values[0]	values[2]	379	1			T3	10		T18	28		T23	11
auto[1]	values[0]	values[3]	215	1			T30	19		T232	6		T206	19
auto[1]	values[0]	values[4]	142	1			T232	7		T127	30		T206	15
auto[1]	values[0]	values[5]	103	1			T187	9		T212	14		T127	15
auto[1]	values[0]	values[6]	89	1			T18	5		T26	9		T188	10
auto[1]	values[0]	values[7]	180	1			T187	5		T30	7		T128	26
auto[1]	values[1]	values[0]	280	1			T20	10		T128	12		T290	14
auto[1]	values[1]	values[1]	314	1			T3	11		T27	2		T128	11
auto[1]	values[1]	values[2]	142	1			T27	29		T232	16		T220	4
auto[1]	values[1]	values[3]	296	1			T19	8		T25	16		T291	8
auto[1]	values[1]	values[4]	155	1			T232	7		T211	18		T268	6
auto[1]	values[1]	values[5]	89	1			T235	19		T292	2		T270	11
auto[1]	values[1]	values[6]	315	1			T18	7		T23	9		T188	20
auto[1]	values[1]	values[7]	233	1			T23	15		T27	26		T30	8
auto[1]	values[2]	values[0]	143	1			T23	4		T30	3		T236	5
auto[1]	values[2]	values[1]	131	1			T19	8		T23	9		T127	13
auto[1]	values[2]	values[2]	117	1			T20	5		T127	9		T220	25
auto[1]	values[2]	values[3]	188	1			T187	10		T29	17		T30	43
auto[1]	values[2]	values[4]	354	1			T3	10		T235	9		T238	9
auto[1]	values[2]	values[5]	185	1			T128	21		T212	6		T188	23
auto[1]	values[2]	values[6]	227	1			T3	10		T18	9		T188	9
auto[1]	values[2]	values[7]	215	1			T232	4		T188	19		T127	31
auto[1]	values[3]	values[0]	100	1			T19	5		T27	5		T212	5
auto[1]	values[3]	values[1]	139	1			T3	10		T23	13		T206	8
auto[1]	values[3]	values[2]	190	1			T18	14		T20	10		T128	13
auto[1]	values[3]	values[3]	192	1			T3	10		T20	9		T29	5
auto[1]	values[3]	values[4]	238	1			T23	64		T27	8		T128	28
auto[1]	values[3]	values[5]	168	1			T3	21		T20	10		T128	15
auto[1]	values[3]	values[6]	183	1			T27	12		T30	11		T128	12
auto[1]	values[3]	values[7]	184	1			T128	8		T207	8		T231	25
auto[1]	values[4]	values[0]	231	1			T18	9		T23	10		T247	34
auto[1]	values[4]	values[1]	241	1			T3	8		T18	8		T20	13
auto[1]	values[4]	values[2]	217	1			T23	14		T27	20		T128	9
auto[1]	values[4]	values[3]	86	1			T27	10		T212	10		T220	9
auto[1]	values[4]	values[4]	207	1			T19	14		T23	11		T128	15
auto[1]	values[4]	values[5]	182	1			T29	15		T128	15		T212	5
auto[1]	values[4]	values[6]	143	1			T18	6		T30	10		T206	12
auto[1]	values[4]	values[7]	187	1			T24	6		T29	9		T235	10
auto[1]	values[5]	values[0]	196	1			T27	66		T212	11		T127	7
auto[1]	values[5]	values[1]	274	1			T3	3		T20	69		T26	19
auto[1]	values[5]	values[2]	253	1			T30	7		T128	9		T212	10
auto[1]	values[5]	values[3]	151	1			T3	16		T18	8		T187	5
auto[1]	values[5]	values[4]	114	1			T18	24		T206	13		T293	14
auto[1]	values[5]	values[5]	171	1			T18	20		T30	9		T188	29
auto[1]	values[5]	values[6]	158	1			T207	7		T222	7		T270	8
auto[1]	values[5]	values[7]	139	1			T18	10		T27	10		T30	50
auto[1]	values[6]	values[0]	129	1			T3	9		T128	18		T242	12
auto[1]	values[6]	values[1]	115	1			T30	7		T128	8		T207	7
auto[1]	values[6]	values[2]	77	1			T27	8		T128	9		T232	7
auto[1]	values[6]	values[3]	155	1			T127	7		T206	8		T236	11
auto[1]	values[6]	values[4]	267	1			T3	4		T128	10		T188	72
auto[1]	values[6]	values[5]	188	1			T19	7		T294	10		T29	7
auto[1]	values[6]	values[6]	137	1			T16	30		T187	3		T254	8
auto[1]	values[6]	values[7]	361	1			T3	12		T232	11		T207	23
auto[1]	values[7]	values[0]	113	1			T27	12		T188	8		T235	7
auto[1]	values[7]	values[1]	169	1			T3	7		T220	26		T238	11
auto[1]	values[7]	values[2]	116	1			T29	14		T295	34		T242	7
auto[1]	values[7]	values[3]	138	1			T18	13		T23	9		T29	13
auto[1]	values[7]	values[4]	110	1			T3	11		T27	8		T127	12
auto[1]	values[7]	values[5]	208	1			T23	9		T187	10		T127	6
auto[1]	values[7]	values[6]	201	1			T28	11		T211	10		T188	6
auto[1]	values[7]	values[7]	322	1			T236	68		T220	9		T235	5