Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7439342	1			T4	23		T5	1		T1	2
all_pins[1]	7439342	1			T4	23		T5	1		T1	2
all_pins[2]	7439342	1			T4	23		T5	1		T1	2
all_pins[3]	7439342	1			T4	23		T5	1		T1	2
all_pins[4]	7439342	1			T4	23		T5	1		T1	2
all_pins[5]	7439342	1			T4	23		T5	1		T1	2
all_pins[6]	7439342	1			T4	23		T5	1		T1	2
all_pins[7]	7439342	1			T4	23		T5	1		T1	2
all_pins[8]	7439342	1			T4	23		T5	1		T1	2
all_pins[9]	7439342	1			T4	23		T5	1		T1	2
all_pins[10]	7439342	1			T4	23		T5	1		T1	2
all_pins[11]	7439342	1			T4	23		T5	1		T1	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	89171499	1			T4	276		T5	12		T1	23
values[0x1]	100605	1			T1	1		T8	1		T65	42
transitions[0x0=>0x1]	99098	1			T1	1		T8	1		T65	28
transitions[0x1=>0x0]	99109	1			T1	1		T8	1		T65	28

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7416981	1			T4	23		T5	1		T1	2
all_pins[0]	values[0x1]	22361	1			T65	5		T66	3		T67	3
all_pins[0]	transitions[0x0=>0x1]	22150	1			T65	4		T66	2		T67	2
all_pins[0]	transitions[0x1=>0x0]	63633	1			T65	2		T66	4		T67	2
all_pins[1]	values[0x0]	7375498	1			T4	23		T5	1		T1	2
all_pins[1]	values[0x1]	63844	1			T65	3		T66	5		T67	3
all_pins[1]	transitions[0x0=>0x1]	63715	1			T65	2		T66	3		T67	1
all_pins[1]	transitions[0x1=>0x0]	422	1			T1	1		T8	1		T65	2
all_pins[2]	values[0x0]	7438791	1			T4	23		T5	1		T1	1
all_pins[2]	values[0x1]	551	1			T1	1		T8	1		T65	3
all_pins[2]	transitions[0x0=>0x1]	527	1			T1	1		T8	1		T65	2
all_pins[2]	transitions[0x1=>0x0]	84	1			T65	2		T83	2		T130	1
all_pins[3]	values[0x0]	7439234	1			T4	23		T5	1		T1	2
all_pins[3]	values[0x1]	108	1			T65	3		T83	3		T130	2
all_pins[3]	transitions[0x0=>0x1]	85	1			T65	2		T83	2		T130	2
all_pins[3]	transitions[0x1=>0x0]	393	1			T65	2		T66	3		T67	2
all_pins[4]	values[0x0]	7438926	1			T4	23		T5	1		T1	2
all_pins[4]	values[0x1]	416	1			T65	3		T66	3		T67	2
all_pins[4]	transitions[0x0=>0x1]	249	1			T65	2		T66	3		T67	2
all_pins[4]	transitions[0x1=>0x0]	1558	1			T65	3		T66	1		T83	1
all_pins[5]	values[0x0]	7437617	1			T4	23		T5	1		T1	2
all_pins[5]	values[0x1]	1725	1			T65	4		T66	1		T83	1
all_pins[5]	transitions[0x0=>0x1]	1701	1			T65	1		T66	1		T83	1
all_pins[5]	transitions[0x1=>0x0]	1124	1			T65	3		T67	3		T83	5
all_pins[6]	values[0x0]	7438194	1			T4	23		T5	1		T1	2
all_pins[6]	values[0x1]	1148	1			T65	6		T67	3		T83	5
all_pins[6]	transitions[0x0=>0x1]	600	1			T65	5		T67	2		T83	4
all_pins[6]	transitions[0x1=>0x0]	488	1			T66	1		T67	3		T83	2
all_pins[7]	values[0x0]	7438306	1			T4	23		T5	1		T1	2
all_pins[7]	values[0x1]	1036	1			T65	1		T66	1		T67	4
all_pins[7]	transitions[0x0=>0x1]	893	1			T66	1		T67	3		T83	1
all_pins[7]	transitions[0x1=>0x0]	114	1			T65	2		T66	1		T67	1
all_pins[8]	values[0x0]	7439085	1			T4	23		T5	1		T1	2
all_pins[8]	values[0x1]	257	1			T65	3		T66	1		T67	2
all_pins[8]	transitions[0x0=>0x1]	230	1			T65	2		T66	1		T67	1
all_pins[8]	transitions[0x1=>0x0]	87	1			T65	2		T66	1		T67	6
all_pins[9]	values[0x0]	7439228	1			T4	23		T5	1		T1	2
all_pins[9]	values[0x1]	114	1			T65	3		T66	1		T67	7
all_pins[9]	transitions[0x0=>0x1]	84	1			T65	2		T67	5		T130	1
all_pins[9]	transitions[0x1=>0x0]	81	1			T65	3		T66	4		T67	1
all_pins[10]	values[0x0]	7439231	1			T4	23		T5	1		T1	2
all_pins[10]	values[0x1]	111	1			T65	4		T66	5		T67	3
all_pins[10]	transitions[0x0=>0x1]	91	1			T65	3		T66	5		T67	3
all_pins[10]	transitions[0x1=>0x0]	8914	1			T65	3		T66	3		T67	1
all_pins[11]	values[0x0]	7430408	1			T4	23		T5	1		T1	2
all_pins[11]	values[0x1]	8934	1			T65	4		T66	3		T67	1
all_pins[11]	transitions[0x0=>0x1]	8773	1			T65	3		T66	3		T67	1
all_pins[11]	transitions[0x1=>0x0]	22211	1			T65	4		T66	3		T67	3