Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	385	1			T3	5		T18	6		T19	4
auto[ReadAddrCrossIntoMailbox]	299	1			T3	3		T18	5		T20	4
auto[ReadAddrCrossOutOfMailbox]	334	1			T3	2		T18	8		T19	5
auto[ReadAddrCrossAllMailbox]	246	1			T3	4		T18	5		T19	2
auto[ReadAddrOutsideMailbox]	3709	1			T3	69		T16	12		T18	45

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2548

1

T3

51

T16

6

T18

42

auto[1]

2425

1

T3

32

T16

6

T18

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	833	1			T3	13		T16	4		T18	9
read_ops[0x0b]	802	1			T3	15		T18	12		T19	3
read_ops[0x3b]	845	1			T3	15		T16	4		T18	11
read_ops[0x6b]	842	1			T3	17		T16	4		T18	12
read_ops[0xbb]	816	1			T3	12		T18	9		T19	7
read_ops[0xeb]	835	1			T3	11		T18	16		T19	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T3	1		T18	1		T23	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T3	1		T27	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T3	1		T18	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T27	1		T212	2		T188	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T18	1		T23	1		T26	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T20	1		T27	3		T188	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T29	1		T128	2		T232	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T19	1		T212	1		T244	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T3	9		T16	2		T18	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T3	1		T16	2		T18	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T3	1		T20	1		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T18	1		T187	1		T246	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T23	2		T30	1		T128	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T20	1		T187	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T20	1		T23	1		T27	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T18	1		T128	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T3	1		T18	1		T26	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T3	1		T18	1		T279	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T3	8		T18	1		T19	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T3	4		T18	7		T19	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T3	1		T19	1		T26	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T23	1		T27	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T18	2		T30	1		T232	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T20	1		T27	1		T128	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	39	1			T18	1		T19	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T20	1		T23	1		T187	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T3	2		T23	1		T27	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T23	1		T29	1		T30	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T3	6		T16	2		T18	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T3	6		T16	2		T18	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T19	1		T114	4		T27	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T18	1		T19	1		T114	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T30	1		T188	2		T206	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T3	2		T18	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T3	1		T19	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T26	1		T27	1		T188	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T18	2		T29	1		T128	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T19	1		T23	1		T277	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T3	6		T16	2		T18	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T3	8		T16	2		T18	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T19	1		T20	1		T232	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T18	1		T20	1		T23	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T127	2		T244	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T23	1		T27	1		T187	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T18	1		T19	1		T26	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T3	1		T19	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T187	1		T232	1		T244	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T128	1		T244	1		T206	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T3	6		T18	3		T19	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T3	5		T18	4		T20	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T18	2		T114	1		T187	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T3	1		T23	1		T114	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T23	1		T187	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T18	1		T20	1		T212	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T18	4		T19	1		T23	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T20	1		T187	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T18	1		T212	1		T232	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T187	1		T128	2		T212	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T3	8		T18	7		T19	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T3	2		T18	1		T20	1