Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3480	1			T18	22		T19	20		T20	26
values[1]	3358	1			T3	23		T18	40		T20	20
values[2]	4330	1			T3	42		T18	20		T19	81
values[3]	3443	1			T3	45		T18	95		T19	20
values[4]	3601	1			T3	86		T12	12		T18	76
values[5]	4337	1			T3	93		T16	30		T17	12
values[6]	4194	1			T3	65		T18	130		T19	20
values[7]	3515	1			T3	63		T18	24		T23	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3750	1			T3	65		T16	30		T18	102
values[1]	3943	1			T3	20		T17	12		T18	44
values[2]	3159	1			T3	64		T18	22		T19	20
values[3]	3538	1			T3	73		T18	23		T23	20
values[4]	3368	1			T18	20		T20	26		T23	40
values[5]	3821	1			T3	40		T12	12		T18	148
values[6]	4684	1			T3	45		T18	109		T19	20
values[7]	3995	1			T3	110		T18	51		T23	192

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29781

1

T3

407

T12

12

T16

30

auto[1]

477

1

T3

10

T18

9

T20

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	425	1			T30	53		T211	20		T236	46
auto[0]	values[0]	values[1]	448	1			T27	23		T210	10		T29	33
auto[0]	values[0]	values[2]	320	1			T278	8		T283	10		T296	10
auto[0]	values[0]	values[3]	290	1			T244	20		T297	20		T254	24
auto[0]	values[0]	values[4]	400	1			T20	25		T24	6		T209	76
auto[0]	values[0]	values[5]	262	1			T19	20		T187	22		T29	23
auto[0]	values[0]	values[6]	817	1			T23	175		T188	143		T127	39
auto[0]	values[0]	values[7]	457	1			T18	20		T23	94		T128	22
auto[0]	values[1]	values[0]	425	1			T3	22		T18	20		T23	20
auto[0]	values[1]	values[1]	306	1			T20	20		T232	20		T282	8
auto[0]	values[1]	values[2]	582	1			T187	18		T220	21		T279	20
auto[0]	values[1]	values[3]	463	1			T27	77		T30	60		T298	25
auto[0]	values[1]	values[4]	457	1			T26	29		T30	67		T128	26
auto[0]	values[1]	values[5]	360	1			T18	20		T187	20		T211	20
auto[0]	values[1]	values[6]	459	1			T26	24		T187	42		T232	53
auto[0]	values[1]	values[7]	233	1			T114	14		T26	18		T128	20
auto[0]	values[2]	values[0]	505	1			T27	20		T232	20		T127	20
auto[0]	values[2]	values[1]	615	1			T3	20		T232	20		T251	20
auto[0]	values[2]	values[2]	385	1			T239	20		T224	18		T255	4
auto[0]	values[2]	values[3]	397	1			T30	47		T128	22		T212	24
auto[0]	values[2]	values[4]	531	1			T18	20		T237	22		T29	22
auto[0]	values[2]	values[5]	570	1			T19	81		T27	97		T266	18
auto[0]	values[2]	values[6]	597	1			T205	30		T30	20		T212	20
auto[0]	values[2]	values[7]	681	1			T3	21		T294	10		T272	131
auto[0]	values[3]	values[0]	469	1			T18	40		T128	20		T246	14
auto[0]	values[3]	values[1]	561	1			T19	20		T23	20		T128	23
auto[0]	values[3]	values[2]	278	1			T20	20		T29	20		T188	20
auto[0]	values[3]	values[3]	561	1			T3	21		T128	40		T276	4
auto[0]	values[3]	values[4]	293	1			T128	19		T299	2		T188	37
auto[0]	values[3]	values[5]	285	1			T18	23		T29	26		T128	24
auto[0]	values[3]	values[6]	324	1			T295	30		T235	17		T297	30
auto[0]	values[3]	values[7]	614	1			T3	22		T18	29		T23	75
auto[0]	values[4]	values[0]	340	1			T209	29		T300	20		T301	4
auto[0]	values[4]	values[1]	451	1			T20	40		T95	16		T128	19
auto[0]	values[4]	values[2]	510	1			T3	24		T247	34		T275	22
auto[0]	values[4]	values[3]	387	1			T29	23		T302	12		T300	25
auto[0]	values[4]	values[4]	437	1			T23	20		T28	24		T127	78
auto[0]	values[4]	values[5]	430	1			T3	19		T12	12		T21	2
auto[0]	values[4]	values[6]	444	1			T18	75		T212	20		T236	20
auto[0]	values[4]	values[7]	548	1			T3	40		T187	25		T212	35
auto[0]	values[5]	values[0]	513	1			T3	41		T16	30		T18	41
auto[0]	values[5]	values[1]	493	1			T17	12		T18	20		T128	23
auto[0]	values[5]	values[2]	349	1			T3	20		T232	47		T293	14
auto[0]	values[5]	values[3]	405	1			T3	31		T285	4		T286	26
auto[0]	values[5]	values[4]	545	1			T23	20		T27	39		T273	28
auto[0]	values[5]	values[5]	950	1			T18	51		T19	20		T288	4
auto[0]	values[5]	values[6]	650	1			T19	20		T23	136		T271	2
auto[0]	values[5]	values[7]	369	1			T128	23		T213	10		T188	20
auto[0]	values[6]	values[0]	515	1			T20	71		T280	14		T128	22
auto[0]	values[6]	values[1]	579	1			T27	20		T232	47		T188	19
auto[0]	values[6]	values[2]	422	1			T18	22		T19	20		T20	77
auto[0]	values[6]	values[3]	660	1			T3	19		T18	22		T26	30
auto[0]	values[6]	values[4]	364	1			T25	14		T30	133		T211	26
auto[0]	values[6]	values[5]	545	1			T18	51		T300	39		T215	23
auto[0]	values[6]	values[6]	601	1			T3	45		T18	33		T115	30
auto[0]	values[6]	values[7]	440	1			T23	20		T274	22		T267	10
auto[0]	values[7]	values[0]	499	1			T303	28		T304	22		T206	55
auto[0]	values[7]	values[1]	446	1			T18	23		T128	25		T251	20
auto[0]	values[7]	values[2]	259	1			T3	20		T291	8		T29	24
auto[0]	values[7]	values[3]	325	1			T23	20		T27	40		T187	20
auto[0]	values[7]	values[4]	275	1			T127	23		T235	46		T300	19
auto[0]	values[7]	values[5]	367	1			T3	19		T30	20		T289	4
auto[0]	values[7]	values[6]	709	1			T204	22		T27	59		T219	18
auto[0]	values[7]	values[7]	584	1			T3	23		T187	20		T223	12
auto[1]	values[0]	values[0]	6	1			T305	2		T306	3		T307	1
auto[1]	values[0]	values[1]	5	1			T128	2		T206	1		T226	1
auto[1]	values[0]	values[2]	7	1			T235	1		T300	1		T242	3
auto[1]	values[0]	values[3]	8	1			T254	3		T104	3		T308	1
auto[1]	values[0]	values[4]	10	1			T20	1		T209	1		T300	5
auto[1]	values[0]	values[5]	3	1			T128	2		T309	1		-	-
auto[1]	values[0]	values[6]	14	1			T23	4		T127	2		T215	1
auto[1]	values[0]	values[7]	8	1			T18	2		T23	1		T128	1
auto[1]	values[1]	values[0]	8	1			T3	1		T206	1		T222	3
auto[1]	values[1]	values[1]	4	1			T207	1		T226	1		T309	2
auto[1]	values[1]	values[2]	16	1			T187	2		T220	2		T231	2
auto[1]	values[1]	values[3]	6	1			T27	2		T253	2		T228	1
auto[1]	values[1]	values[4]	9	1			T26	1		T235	2		T209	2
auto[1]	values[1]	values[5]	12	1			T235	1		T310	8		T311	1
auto[1]	values[1]	values[6]	9	1			T26	1		T232	1		T188	3
auto[1]	values[1]	values[7]	9	1			T26	2		T212	1		T215	1
auto[1]	values[2]	values[0]	7	1			T256	1		T216	1		T309	2
auto[1]	values[2]	values[1]	3	1			T312	2		T313	1		-	-
auto[1]	values[2]	values[2]	8	1			T314	6		T315	1		T312	1
auto[1]	values[2]	values[3]	9	1			T30	1		T235	1		T103	3
auto[1]	values[2]	values[4]	10	1			T29	2		T127	1		T227	1
auto[1]	values[2]	values[5]	4	1			T211	2		T306	1		T316	1
auto[1]	values[2]	values[6]	3	1			T309	2		T307	1		-	-
auto[1]	values[2]	values[7]	5	1			T3	1		T188	1		T105	1
auto[1]	values[3]	values[0]	4	1			T18	1		T206	1		T253	1
auto[1]	values[3]	values[1]	2	1			T128	1		T317	1		-	-
auto[1]	values[3]	values[2]	2	1			T236	1		T309	1		-	-
auto[1]	values[3]	values[3]	6	1			T3	1		T127	1		T206	1
auto[1]	values[3]	values[4]	7	1			T128	1		T227	1		T318	1
auto[1]	values[3]	values[5]	5	1			T18	2		T29	1		T128	1
auto[1]	values[3]	values[6]	15	1			T295	4		T235	3		T311	1
auto[1]	values[3]	values[7]	17	1			T3	1		T23	2		T27	3
auto[1]	values[4]	values[0]	4	1			T305	4		-	-		-	-
auto[1]	values[4]	values[1]	10	1			T128	1		T188	1		T206	3
auto[1]	values[4]	values[2]	4	1			T319	1		T320	3		-	-
auto[1]	values[4]	values[3]	5	1			T29	2		T300	1		T311	1
auto[1]	values[4]	values[4]	6	1			T28	1		T127	1		T105	1
auto[1]	values[4]	values[5]	6	1			T3	1		T236	1		T209	2
auto[1]	values[4]	values[6]	11	1			T18	1		T220	1		T209	1
auto[1]	values[4]	values[7]	8	1			T3	2		T236	1		T235	1
auto[1]	values[5]	values[0]	10	1			T3	1		T319	2		T321	2
auto[1]	values[5]	values[1]	7	1			T127	1		T103	2		T215	1
auto[1]	values[5]	values[2]	10	1			T232	2		T309	2		T322	5
auto[1]	values[5]	values[3]	2	1			T242	1		T323	1		-	-
auto[1]	values[5]	values[4]	10	1			T27	1		T236	5		T231	1
auto[1]	values[5]	values[5]	8	1			T128	4		T232	1		T242	2
auto[1]	values[5]	values[6]	9	1			T23	5		T227	1		T324	2
auto[1]	values[5]	values[7]	7	1			T325	2		T326	1		T327	1
auto[1]	values[6]	values[0]	8	1			T20	2		T251	2		T270	1
auto[1]	values[6]	values[1]	8	1			T232	1		T188	1		T209	1
auto[1]	values[6]	values[2]	4	1			T232	2		T242	1		T243	1
auto[1]	values[6]	values[3]	13	1			T3	1		T18	1		T30	1
auto[1]	values[6]	values[4]	10	1			T25	2		T30	2		T242	4
auto[1]	values[6]	values[5]	6	1			T18	1		T215	2		T328	1
auto[1]	values[6]	values[6]	11	1			T27	2		T30	2		T235	1
auto[1]	values[6]	values[7]	8	1			T270	1		T329	1		T321	1
auto[1]	values[7]	values[0]	12	1			T206	2		T300	4		T228	2
auto[1]	values[7]	values[1]	5	1			T18	1		T222	2		T105	2
auto[1]	values[7]	values[2]	3	1			T29	1		T328	1		T306	1
auto[1]	values[7]	values[3]	1	1			T27	1		-	-		-	-
auto[1]	values[7]	values[4]	4	1			T300	1		T226	2		T330	1
auto[1]	values[7]	values[5]	8	1			T3	1		T188	1		T206	1
auto[1]	values[7]	values[6]	11	1			T27	2		T128	1		T243	2
auto[1]	values[7]	values[7]	7	1			T231	1		T228	2		T311	2