Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2554

1

T3

12

T6

1

T7

7

auto[1]

2404

1

T3

13

T6

1

T7

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2629

1

T3

20

T6

2

T7

9

auto[1]

2329

1

T3

5

T38

3

T99

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3969

1

T3

21

T6

2

T7

3

auto[1]

989

1

T3

4

T7

6

T38

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	997	1			T3	5		T7	2		T38	2
valid[1]	978	1			T3	7		T38	3		T99	2
valid[2]	984	1			T3	4		T7	3		T38	1
valid[3]	1015	1			T3	5		T7	1		T38	2
valid[4]	984	1			T3	4		T6	2		T7	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	166	1			T7	1		T38	1		T18	1
auto[0]	auto[0]	valid[0]	auto[1]	216	1			T3	1		T99	2		T46	3
auto[0]	auto[0]	valid[1]	auto[0]	166	1			T3	3		T38	1		T46	2
auto[0]	auto[0]	valid[1]	auto[1]	249	1			T101	1		T106	2		T46	1
auto[0]	auto[0]	valid[2]	auto[0]	193	1			T3	1		T7	1		T18	2
auto[0]	auto[0]	valid[2]	auto[1]	221	1			T38	1		T99	2		T101	1
auto[0]	auto[0]	valid[3]	auto[0]	182	1			T3	3		T7	1		T38	1
auto[0]	auto[0]	valid[3]	auto[1]	251	1			T3	1		T46	2		T26	2
auto[0]	auto[0]	valid[4]	auto[0]	185	1			T3	2		T6	1		T46	1
auto[0]	auto[0]	valid[4]	auto[1]	234	1			T106	2		T46	3		T102	6
auto[0]	auto[1]	valid[0]	auto[0]	153	1			T3	3		T46	2		T26	1
auto[0]	auto[1]	valid[0]	auto[1]	236	1			T3	1		T38	1		T99	1
auto[0]	auto[1]	valid[1]	auto[0]	132	1			T3	1		T46	1		T107	2
auto[0]	auto[1]	valid[1]	auto[1]	227	1			T3	1		T38	1		T99	2
auto[0]	auto[1]	valid[2]	auto[0]	167	1			T3	1		T46	1		T107	1
auto[0]	auto[1]	valid[2]	auto[1]	229	1			T106	2		T46	3		T26	2
auto[0]	auto[1]	valid[3]	auto[0]	171	1			T3	1		T46	1		T107	1
auto[0]	auto[1]	valid[3]	auto[1]	210	1			T46	1		T26	2		T102	2
auto[0]	auto[1]	valid[4]	auto[0]	125	1			T3	1		T6	1		T107	1
auto[0]	auto[1]	valid[4]	auto[1]	256	1			T3	1		T106	2		T26	1
auto[1]	auto[0]	valid[0]	auto[0]	117	1			T7	1		T46	1		T342	2
auto[1]	auto[0]	valid[1]	auto[0]	111	1			T3	1		T46	3		T26	2
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T7	2		T46	1		T26	2
auto[1]	auto[0]	valid[3]	auto[0]	94	1			T23	1		T345	1		T342	1
auto[1]	auto[0]	valid[4]	auto[0]	85	1			T7	1		T38	1		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	109	1			T46	1		T23	1		T27	1
auto[1]	auto[1]	valid[1]	auto[0]	93	1			T3	1		T38	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	90	1			T3	2		T46	2		T26	2
auto[1]	auto[1]	valid[3]	auto[0]	107	1			T38	1		T46	1		T107	1
auto[1]	auto[1]	valid[4]	auto[0]	99	1			T7	2		T107	2		T342	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal