Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	72	2	70	97.22

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	72	2	70	97.22	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	430	1			T65	10		T66	10		T67	10
all_values[1]	430	1			T65	10		T66	10		T67	10
all_values[2]	430	1			T65	10		T66	10		T67	10
all_values[3]	430	1			T65	10		T66	10		T67	10
all_values[4]	430	1			T65	10		T66	10		T67	10
all_values[5]	430	1			T65	10		T66	10		T67	10
all_values[6]	430	1			T65	10		T66	10		T67	10
all_values[7]	430	1			T65	10		T66	10		T67	10
all_values[8]	430	1			T65	10		T66	10		T67	10
all_values[9]	430	1			T65	10		T66	10		T67	10
all_values[10]	430	1			T65	10		T66	10		T67	10
all_values[11]	430	1			T65	10		T66	10		T67	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2771

1

T65

65

T66

61

T67

59

auto[1]

2389

1

T65

55

T66

59

T67

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1959

1

T65

32

T66

43

T67

33

auto[1]

3201

1

T65

88

T66

77

T67

87

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2901

1

T65

61

T66

68

T67

56

auto[1]

2259

1

T65

59

T66

52

T67

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	2	70	97.22	2
Automatically Generated Cross Bins	72	2	70	97.22	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[11]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	92	1			T65	4		T66	2		T67	3
all_values[0]	auto[0]	auto[0]	auto[1]	29	1			T83	1		T142	2		T186	3
all_values[0]	auto[0]	auto[1]	auto[0]	78	1			T66	1		T67	3		T83	1
all_values[0]	auto[0]	auto[1]	auto[1]	49	1			T65	2		T66	2		T67	2
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T65	2		T66	4		T83	3
all_values[0]	auto[1]	auto[1]	auto[1]	86	1			T65	2		T66	1		T67	2
all_values[1]	auto[0]	auto[0]	auto[0]	79	1			T65	1		T66	1		T67	1
all_values[1]	auto[0]	auto[0]	auto[1]	44	1			T65	2		T66	2		T67	1
all_values[1]	auto[0]	auto[1]	auto[0]	72	1			T66	2		T67	2		T83	3
all_values[1]	auto[0]	auto[1]	auto[1]	40	1			T65	1		T66	1		T67	1
all_values[1]	auto[1]	auto[0]	auto[1]	112	1			T65	4		T67	2		T83	3
all_values[1]	auto[1]	auto[1]	auto[1]	83	1			T65	2		T66	4		T67	3
all_values[2]	auto[0]	auto[0]	auto[0]	91	1			T66	1		T131	5		T133	3
all_values[2]	auto[0]	auto[0]	auto[1]	37	1			T65	2		T66	1		T67	3
all_values[2]	auto[0]	auto[1]	auto[0]	71	1			T83	2		T130	3		T133	1
all_values[2]	auto[0]	auto[1]	auto[1]	39	1			T65	1		T66	3		T67	1
all_values[2]	auto[1]	auto[0]	auto[1]	106	1			T65	5		T66	4		T67	3
all_values[2]	auto[1]	auto[1]	auto[1]	86	1			T65	2		T66	1		T67	3
all_values[3]	auto[0]	auto[0]	auto[0]	108	1			T65	1		T66	2		T67	3
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T65	2		T66	1		T67	1
all_values[3]	auto[0]	auto[1]	auto[0]	68	1			T65	2		T66	3		T67	3
all_values[3]	auto[0]	auto[1]	auto[1]	41	1			T65	1		T83	1		T130	1
all_values[3]	auto[1]	auto[0]	auto[1]	92	1			T65	3		T66	4		T67	1
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T65	1		T67	2		T83	2
all_values[4]	auto[0]	auto[0]	auto[0]	77	1			T65	2		T66	2		T67	1
all_values[4]	auto[0]	auto[0]	auto[1]	49	1			T65	3		T66	2		T67	1
all_values[4]	auto[0]	auto[1]	auto[0]	70	1			T66	1		T83	1		T131	2
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T65	2		T66	2		T67	1
all_values[4]	auto[1]	auto[0]	auto[1]	111	1			T65	2		T66	2		T67	5
all_values[4]	auto[1]	auto[1]	auto[1]	75	1			T65	1		T66	1		T67	2
all_values[5]	auto[0]	auto[0]	auto[0]	76	1			T65	2		T83	5		T130	1
all_values[5]	auto[0]	auto[0]	auto[1]	44	1			T65	1		T66	2		T67	2
all_values[5]	auto[0]	auto[1]	auto[0]	87	1			T66	4		T67	1		T83	2
all_values[5]	auto[0]	auto[1]	auto[1]	42	1			T65	1		T67	1		T130	2
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T65	2		T66	2		T67	5
all_values[5]	auto[1]	auto[1]	auto[1]	69	1			T65	4		T66	2		T67	1
all_values[6]	auto[0]	auto[0]	auto[0]	78	1			T65	1		T66	1		T67	2
all_values[6]	auto[0]	auto[0]	auto[1]	44	1			T66	1		T131	2		T135	1
all_values[6]	auto[0]	auto[1]	auto[0]	60	1			T66	2		T67	1		T131	2
all_values[6]	auto[0]	auto[1]	auto[1]	32	1			T65	3		T67	1		T83	2
all_values[6]	auto[1]	auto[0]	auto[1]	118	1			T65	2		T66	4		T67	2
all_values[6]	auto[1]	auto[1]	auto[1]	98	1			T65	4		T66	2		T67	4
all_values[7]	auto[0]	auto[0]	auto[0]	84	1			T65	5		T66	3		T83	3
all_values[7]	auto[0]	auto[0]	auto[1]	39	1			T66	2		T67	2		T131	3
all_values[7]	auto[0]	auto[1]	auto[0]	74	1			T65	3		T66	1		T67	1
all_values[7]	auto[0]	auto[1]	auto[1]	51	1			T65	1		T67	1		T130	1
all_values[7]	auto[1]	auto[0]	auto[1]	97	1			T66	2		T67	4		T83	5
all_values[7]	auto[1]	auto[1]	auto[1]	85	1			T65	1		T66	2		T67	2
all_values[8]	auto[0]	auto[0]	auto[0]	88	1			T65	3		T66	4		T130	5
all_values[8]	auto[0]	auto[0]	auto[1]	51	1			T66	1		T83	1		T142	1
all_values[8]	auto[0]	auto[1]	auto[0]	76	1			T65	1		T66	2		T67	4
all_values[8]	auto[0]	auto[1]	auto[1]	36	1			T65	1		T67	1		T83	1
all_values[8]	auto[1]	auto[0]	auto[1]	96	1			T65	2		T67	1		T83	5
all_values[8]	auto[1]	auto[1]	auto[1]	83	1			T65	3		T66	3		T67	4
all_values[9]	auto[0]	auto[0]	auto[0]	72	1			T67	1		T83	3		T130	2
all_values[9]	auto[0]	auto[0]	auto[1]	52	1			T65	2		T131	3		T133	1
all_values[9]	auto[0]	auto[1]	auto[0]	72	1			T65	1		T66	6		T83	2
all_values[9]	auto[0]	auto[1]	auto[1]	47	1			T65	1		T66	2		T67	3
all_values[9]	auto[1]	auto[0]	auto[1]	104	1			T65	4		T66	2		T67	3
all_values[9]	auto[1]	auto[1]	auto[1]	83	1			T65	2		T67	3		T83	2
all_values[10]	auto[0]	auto[0]	auto[0]	90	1			T65	1		T67	3		T83	2
all_values[10]	auto[0]	auto[0]	auto[1]	43	1			T65	1		T66	3		T83	1
all_values[10]	auto[0]	auto[1]	auto[0]	72	1			T83	1		T130	1		T131	2
all_values[10]	auto[0]	auto[1]	auto[1]	47	1			T65	2		T67	1		T130	2
all_values[10]	auto[1]	auto[0]	auto[1]	97	1			T65	4		T66	2		T67	3
all_values[10]	auto[1]	auto[1]	auto[1]	81	1			T65	2		T66	5		T67	3
all_values[11]	auto[0]	auto[0]	auto[0]	117	1			T65	1		T66	2		T67	2
all_values[11]	auto[0]	auto[1]	auto[0]	107	1			T65	4		T66	3		T67	2
all_values[11]	auto[1]	auto[0]	auto[1]	108	1			T65	1		T66	2		T67	4
all_values[11]	auto[1]	auto[1]	auto[1]	98	1			T65	4		T66	3		T67	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal