Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66220

1

T4

2

T3

503

T15

10

auto[1]

24067

1

T3

55

T7

31

T38

84

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66213

1

T4

2

T3

376

T15

5

auto[1]

24074

1

T3

182

T15

5

T6

27

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	46453	1			T4	1		T3	267		T15	6
others[1]	7594	1			T4	1		T3	48		T15	1
others[2]	7692	1			T3	63		T15	3		T6	8
others[3]	8568	1			T3	57		T6	10		T7	24
interest[1]	4986	1			T3	30		T6	6		T7	14
interest[4]	30453	1			T4	1		T3	181		T15	4
interest[64]	14994	1			T3	93		T6	11		T7	46

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	21447	1			T4	1		T3	156		T15	2
auto[0]	auto[0]	others[1]	3557	1			T4	1		T3	26		T15	1
auto[0]	auto[0]	others[2]	3641	1			T3	32		T15	2		T6	7
auto[0]	auto[0]	others[3]	4058	1			T3	36		T6	7		T7	12
auto[0]	auto[0]	interest[1]	2286	1			T3	20		T6	5		T7	8
auto[0]	auto[0]	interest[4]	14024	1			T4	1		T3	106		T15	1
auto[0]	auto[0]	interest[64]	7157	1			T3	51		T6	8		T7	27
auto[0]	auto[1]	others[0]	12638	1			T3	23		T7	18		T38	50
auto[0]	auto[1]	others[1]	1950	1			T3	7		T7	1		T38	7
auto[0]	auto[1]	others[2]	1981	1			T3	6		T7	3		T38	7
auto[0]	auto[1]	others[3]	2271	1			T3	7		T7	3		T38	7
auto[0]	auto[1]	interest[1]	1319	1			T3	1		T7	1		T46	3
auto[0]	auto[1]	interest[4]	8470	1			T3	16		T7	12		T38	33
auto[0]	auto[1]	interest[64]	3908	1			T3	11		T7	5		T38	13
auto[1]	auto[0]	others[0]	12368	1			T3	88		T15	4		T6	19
auto[1]	auto[0]	others[1]	2087	1			T3	15		T7	2		T38	13
auto[1]	auto[0]	others[2]	2070	1			T3	25		T15	1		T6	1
auto[1]	auto[0]	others[3]	2239	1			T3	14		T6	3		T7	9
auto[1]	auto[0]	interest[1]	1381	1			T3	9		T6	1		T7	5
auto[1]	auto[0]	interest[4]	7959	1			T3	59		T15	3		T6	13
auto[1]	auto[0]	interest[64]	3929	1			T3	31		T6	3		T7	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal