Summary for Variable cp_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for cp_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[GenericMode] |
7259801 |
1 |
|
|
T2 |
103 |
|
T9 |
67 |
|
T10 |
13983 |
auto[FlashMode] |
98363 |
1 |
|
|
T4 |
2 |
|
T11 |
29 |
|
T15 |
10 |
auto[PassthroughMode] |
58492 |
1 |
|
|
T5 |
2 |
|
T3 |
975 |
|
T12 |
30 |
Summary for Variable cp_tpm_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_tpm_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7024329 |
1 |
|
|
T5 |
2 |
|
T2 |
103 |
|
T11 |
29 |
auto[1] |
392327 |
1 |
|
|
T4 |
2 |
|
T3 |
975 |
|
T15 |
10 |
Summary for Cross cr_all
Samples crossed: cp_mode cp_tpm_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
5 |
0 |
5 |
100.00 |
|
Automatically Generated Cross Bins |
5 |
0 |
5 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_all
Bins
cp_mode | cp_tpm_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[GenericMode] |
auto[0] |
6999152 |
1 |
|
|
T2 |
103 |
|
T9 |
67 |
|
T10 |
13983 |
auto[FlashMode] |
auto[0] |
10836 |
1 |
|
|
T11 |
29 |
|
T32 |
29 |
|
T164 |
26 |
auto[FlashMode] |
auto[1] |
87527 |
1 |
|
|
T4 |
2 |
|
T15 |
10 |
|
T6 |
682 |
auto[PassthroughMode] |
auto[0] |
14341 |
1 |
|
|
T5 |
2 |
|
T12 |
30 |
|
T16 |
40 |
auto[PassthroughMode] |
auto[1] |
44151 |
1 |
|
|
T3 |
975 |
|
T18 |
686 |
|
T23 |
687 |
User Defined Cross Bins for cr_all
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |