Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 5 0 5 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 5 0 5 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GenericMode] 7259801 1 T2 103 T9 67 T10 13983
auto[FlashMode] 98363 1 T4 2 T11 29 T15 10
auto[PassthroughMode] 58492 1 T5 2 T3 975 T12 30



Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7024329 1 T5 2 T2 103 T11 29
auto[1] 392327 1 T4 2 T3 975 T15 10



Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_all

Bins
cp_modecp_tpm_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GenericMode] auto[0] 6999152 1 T2 103 T9 67 T10 13983
auto[FlashMode] auto[0] 10836 1 T11 29 T32 29 T164 26
auto[FlashMode] auto[1] 87527 1 T4 2 T15 10 T6 682
auto[PassthroughMode] auto[0] 14341 1 T5 2 T12 30 T16 40
auto[PassthroughMode] auto[1] 44151 1 T3 975 T18 686 T23 687


User Defined Cross Bins for cr_all

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%