Unified Coverage Report :: Module Instance :: tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.25	100.00	75.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	98.25	100.00		100.00	87.50	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	98.25	100.00		100.00	87.50	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.30	90.91	42.31			60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.72	85.00	42.31			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00

Module Instance : tb.dut.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.89	95.00	69.23			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.03	100.00	76.47			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.12	95.00	76.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T9,T10
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T9,T10
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T5,T1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T1
0	0	Covered	T2,T9,T10

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T5,T1,T2
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1616209412	4513624	0	0
DepthKnown_A	1616209412	1576184653	0	0
RvalidKnown_A	1616209412	1576184653	0	0
WreadyKnown_A	1616209412	1576184653	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1616209412	4513624	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	4513624	0	0
T1	909	2	0	0
T2	38509	103	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	67	0	0
T10	0	13983	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	1626	0	0
T14	0	2	0	0
T15	4103	0	0	0
T33	0	20197	0	0
T34	792	2	0	0
T45	0	14605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	4513624	0	0
T1	909	2	0	0
T2	38509	103	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	67	0	0
T10	0	13983	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	1626	0	0
T14	0	2	0	0
T15	4103	0	0	0
T33	0	20197	0	0
T34	792	2	0	0
T45	0	14605	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	32	24	75.00
Logical	32	24	75.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T5,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T11,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T6
1	0	Covered	T3,T11,T6
1	1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T6
0	1	Covered	T4,T5,T1
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T5,T2,T3
0	0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T6
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410997401	23344664	0	0
DepthKnown_A	410997401	359562642	0	0
RvalidKnown_A	410997401	359562642	0	0
WreadyKnown_A	410997401	359562642	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	410997401	23344664	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	23344664	0	0
T3	175606	261841	0	0
T6	694998	104365	0	0
T7	0	17010	0	0
T11	92864	10816	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T16	201847	36556	0	0
T17	0	23845	0	0
T18	0	238425	0	0
T21	0	3988	0	0
T37	25826	24689	0	0
T38	0	111947	0	0
T39	1697	0	0	0
T40	120179	0	0	0
T41	8208	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	23344664	0	0
T3	175606	261841	0	0
T6	694998	104365	0	0
T7	0	17010	0	0
T11	92864	10816	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T16	201847	36556	0	0
T17	0	23845	0	0
T18	0	238425	0	0
T21	0	3988	0	0
T37	25826	24689	0	0
T38	0	111947	0	0
T39	1697	0	0	0
T40	120179	0	0	0
T41	8208	0	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	32	28	87.50
Logical	32	28	87.50
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T6
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T2,T3
1	0	1	Covered	T3,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T11,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T5,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Not Covered
1	1	Covered	T3,T11,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T11,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T6
1	0	Covered	T3,T11,T6
1	1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T11,T6
0	1	Covered	T4,T5,T1
0	0	Covered	T3,T11,T6

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T5,T2,T3
0	0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T6
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410997401	24566802	0	0
DepthKnown_A	410997401	359562642	0	0
RvalidKnown_A	410997401	359562642	0	0
WreadyKnown_A	410997401	359562642	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	410997401	24566802	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	24566802	0	0
T3	175606	275581	0	0
T6	694998	108474	0	0
T7	0	17849	0	0
T11	92864	12025	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T16	201847	38728	0	0
T17	0	24608	0	0
T18	0	250993	0	0
T21	0	4112	0	0
T37	25826	25562	0	0
T38	0	116215	0	0
T39	1697	0	0	0
T40	120179	0	0	0
T41	8208	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	24566802	0	0
T3	175606	275581	0	0
T6	694998	108474	0	0
T7	0	17849	0	0
T11	92864	12025	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T16	201847	38728	0	0
T17	0	24608	0	0
T18	0	250993	0	0
T21	0	4112	0	0
T37	25826	25562	0	0
T38	0	116215	0	0
T39	1697	0	0	0
T40	120179	0	0	0
T41	8208	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	1	50.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	0	1
			MISSING_ELSE
175	0	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	11	42.31
Logical	26	11	42.31
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T5,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	88	3	1	33.33
TERNARY	180	2	1	50.00
IF	70	3	3	100.00
IF	165	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T5,T1
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T5,T2,T3
0	0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410997401	0	0	0
DepthKnown_A	410997401	359562642	0	0
RvalidKnown_A	410997401	359562642	0	0
WreadyKnown_A	410997401	359562642	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	410997401	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T2

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T1,T2

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T11,T8,T34
1	1	0	Not Covered
1	1	1	Covered	T5,T1,T2

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T5,T1,T2

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T2

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T1,T2
0	1	Covered	T4,T5,T1
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2010348469	22039577	0	0
DepthKnown_A	2010348469	2010212750	0	0
RvalidKnown_A	2010348469	2010212750	0	0
WreadyKnown_A	2010348469	2010212750	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2010348469	22039577	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	22039577	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19617	0	0
T5	38636	1024	0	0
T6	362548	19727	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	22039577	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19617	0	0
T5	38636	1024	0	0
T6	362548	19727	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T4,T5,T1
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2010348469	4768938	0	0
DepthKnown_A	2010348469	2010212750	0	0
RvalidKnown_A	2010348469	2010212750	0	0
WreadyKnown_A	2010348469	2010212750	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2010348469	4768938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	4768938	0	0
T2	38590	103	0	0
T3	122489	161	0	0
T6	362548	271	0	0
T8	1383	0	0	0
T9	0	67	0	0
T10	0	13983	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T13	0	1626	0	0
T15	2769	0	0	0
T33	0	22939	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T39	0	53	0	0
T40	0	12140	0	0
T45	0	14605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	4768938	0	0
T2	38590	103	0	0
T3	122489	161	0	0
T6	362548	271	0	0
T8	1383	0	0	0
T9	0	67	0	0
T10	0	13983	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T13	0	1626	0	0
T15	2769	0	0	0
T33	0	22939	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T39	0	53	0	0
T40	0	12140	0	0
T45	0	14605	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	34	26	76.47
Logical	34	26	76.47
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T47,T48

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T13,T33
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T47,T48
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T47,T48

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T3,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T33,T47,T48
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T5,T1

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T4,T5,T1

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T47,T48
0	1	Covered	T4,T5,T1
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2010348469	9370987	0	0
DepthKnown_A	2010348469	2010212750	0	0
RvalidKnown_A	2010348469	2010212750	0	0
WreadyKnown_A	2010348469	2010212750	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2010348469	9370987	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	9370987	0	0
T2	38590	103	0	0
T3	122489	161	0	0
T6	362548	271	0	0
T8	1383	0	0	0
T9	0	67	0	0
T10	0	13983	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T13	0	1626	0	0
T15	2769	0	0	0
T33	0	105317	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T39	0	53	0	0
T40	0	12140	0	0
T45	0	14605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	9370987	0	0
T2	38590	103	0	0
T3	122489	161	0	0
T6	362548	271	0	0
T8	1383	0	0	0
T9	0	67	0	0
T10	0	13983	0	0
T11	298159	0	0	0
T12	53035	0	0	0
T13	0	1626	0	0
T15	2769	0	0	0
T33	0	105317	0	0
T34	910	0	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T39	0	53	0	0
T40	0	12140	0	0
T45	0	14605	0	0