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Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_242.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_242


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_243.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_243


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_244.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_244


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_245.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_245


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_246.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_246


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_247.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_247


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_248.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_248


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_249.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_249


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_250.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_250


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_251.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_251


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_252.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_252


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_253.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_253


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_254.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_254


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_filter_7_filter_255.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_filter_7_filter_255


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_addr_swap_mask.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_addr_swap_mask


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_addr_swap_data.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_addr_swap_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_payload_swap_mask.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_payload_swap_mask


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_payload_swap_data.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_payload_swap_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_0_opcode_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_0_opcode_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_cmd_filter_7_filter_242.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_243.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_244.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_245.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_246.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_247.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_248.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_249.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_250.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_251.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_252.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_253.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_254.wr_en_data_arb
tb.dut.u_reg.u_cmd_filter_7_filter_255.wr_en_data_arb
tb.dut.u_reg.u_addr_swap_mask.wr_en_data_arb
tb.dut.u_reg.u_addr_swap_data.wr_en_data_arb
tb.dut.u_reg.u_payload_swap_mask.wr_en_data_arb
tb.dut.u_reg.u_payload_swap_data.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_0_opcode_0.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_242.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_242.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_242.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_243.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_243.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_243.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_244.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_244.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_244.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_245.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_245.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_245.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_246.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_246.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_246.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_247.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_247.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_247.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_248.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_248.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_248.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_249.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_249.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_249.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_250.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_250.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_250.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_251.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_251.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_251.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_252.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_252.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_252.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_253.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_253.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_253.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_254.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_254.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_254.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_255.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_255.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_255.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_addr_swap_mask.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_addr_swap_mask.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_addr_swap_mask.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_addr_swap_data.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_addr_swap_data.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_addr_swap_data.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_payload_swap_mask.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_payload_swap_mask.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_payload_swap_mask.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_payload_swap_data.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_payload_swap_data.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_payload_swap_data.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_0_opcode_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_0_opcode_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT5,T3,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT5,T3,T11
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_0_opcode_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T5,T3,T11
0 Covered T4,T5,T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%