Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.33	98.63	92.06	98.05	95.86	99.76

Total test records in report: 1753

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html

T1751	/workspace/coverage/default/47.spi_device_bit_transfer.191402586			Jan 07 01:25:06 PM PST 24	Jan 07 01:25:21 PM PST 24	1274309237 ps
T1752	/workspace/coverage/default/6.spi_device_intercept.2122622703			Jan 07 01:19:50 PM PST 24	Jan 07 01:20:04 PM PST 24	52938117 ps
T1753	/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3104741354			Jan 07 01:19:36 PM PST 24	Jan 07 01:21:05 PM PST 24	6784607015 ps

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm.1611348222
Short name	T3
Test name
Test status
Simulation time	489958519754 ps
CPU time	931.5 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:38:23 PM PST 24
Peak memory	273668 kb
Host	smart-dfde549e-0fd7-4bfe-990f-22bc5ff3af8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611348222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1611348222
Directory	/workspace/30.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/3.spi_device_abort.501184567
Short name	T8
Test name
Test status
Simulation time	14737210 ps
CPU time	0.77 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:15 PM PST 24
Peak memory	206592 kb
Host	smart-31005976-0860-4fa2-ac4e-61dbd4fa8179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501184567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_abort.501184567
Directory	/workspace/3.spi_device_abort/latest

Test location	/workspace/coverage/default/17.spi_device_stress_all.1682883023
Short name	T128
Test name
Test status
Simulation time	509463606740 ps
CPU time	924.9 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:36:24 PM PST 24
Peak memory	285628 kb
Host	smart-d645658d-77fb-4543-a363-0e4697b24a98
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682883023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre ss_all.1682883023
Directory	/workspace/17.spi_device_stress_all/latest

Test location	/workspace/coverage/default/19.spi_device_stress_all.2228430762
Short name	T7
Test name
Test status
Simulation time	105685777663 ps
CPU time	648.66 seconds
Started	Jan 07 01:21:29 PM PST 24
Finished	Jan 07 01:32:20 PM PST 24
Peak memory	318136 kb
Host	smart-ca182c3e-b6d0-4119-96c1-149223622221
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228430762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre ss_all.2228430762
Directory	/workspace/19.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3433045870
Short name	T82
Test name
Test status
Simulation time	1114409605 ps
CPU time	23.45 seconds
Started	Jan 07 12:36:28 PM PST 24
Finished	Jan 07 12:38:08 PM PST 24
Peak memory	215696 kb
Host	smart-4c028d49-b523-44a7-8463-3dded69b0acb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433045870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic e_tl_intg_err.3433045870
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3204416904
Short name	T133
Test name
Test status
Simulation time	84741596 ps
CPU time	0.74 seconds
Started	Jan 07 12:33:51 PM PST 24
Finished	Jan 07 12:35:22 PM PST 24
Peak memory	204768 kb
Host	smart-2e60e916-758a-49c2-af10-1fa38f43502f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204416904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 3204416904
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.826583648
Short name	T46
Test name
Test status
Simulation time	18743512218 ps
CPU time	109.01 seconds
Started	Jan 07 01:25:26 PM PST 24
Finished	Jan 07 01:27:25 PM PST 24
Peak memory	255100 kb
Host	smart-ad0b2348-5bf1-440d-95b2-13c616f039f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826583648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle .826583648
Directory	/workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/1.spi_device_ram_cfg.3226629207
Short name	T667
Test name
Test status
Simulation time	24218695 ps
CPU time	0.73 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	216768 kb
Host	smart-5c2798c7-c478-4c3d-b3ef-104022090abc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226629207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3226629207
Directory	/workspace/1.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2426574738
Short name	T18
Test name
Test status
Simulation time	115582562984 ps
CPU time	374.62 seconds
Started	Jan 07 01:23:04 PM PST 24
Finished	Jan 07 01:29:20 PM PST 24
Peak memory	267868 kb
Host	smart-4cfbd4d4-4900-40ff-8e50-63afd2a47780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426574738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl e.2426574738
Directory	/workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/16.spi_device_flash_mode.1591583246
Short name	T11
Test name
Test status
Simulation time	2981615355 ps
CPU time	20.24 seconds
Started	Jan 07 01:20:45 PM PST 24
Finished	Jan 07 01:21:13 PM PST 24
Peak memory	238356 kb
Host	smart-8077a25f-25db-4d4d-88a7-c7ffd3d4874d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591583246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1591583246
Directory	/workspace/16.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1431543982
Short name	T235
Test name
Test status
Simulation time	93999871565 ps
CPU time	540.95 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:30:01 PM PST 24
Peak memory	273848 kb
Host	smart-52ea95bd-e8fe-42f0-ac27-93d591402c4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431543982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl e.1431543982
Directory	/workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/17.spi_device_rx_timeout.816842936
Short name	T2
Test name
Test status
Simulation time	803956148 ps
CPU time	4.63 seconds
Started	Jan 07 01:20:47 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	216736 kb
Host	smart-613aba20-039a-432b-87cb-d5c87465f1f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816842936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_timeout.816842936
Directory	/workspace/17.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/36.spi_device_stress_all.177056733
Short name	T127
Test name
Test status
Simulation time	92229973340 ps
CPU time	343.02 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:29:57 PM PST 24
Peak memory	356424 kb
Host	smart-294c3562-8ff2-4790-ae97-ceafd4135685
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177056733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres s_all.177056733
Directory	/workspace/36.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2994056074
Short name	T118
Test name
Test status
Simulation time	229873175 ps
CPU time	5.24 seconds
Started	Jan 07 12:33:13 PM PST 24
Finished	Jan 07 12:35:10 PM PST 24
Peak memory	215824 kb
Host	smart-87d5f940-035c-41dd-bda2-c15f3c14b608
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994056074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2 994056074
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/44.spi_device_stress_all.3897938987
Short name	T27
Test name
Test status
Simulation time	277669837151 ps
CPU time	491.06 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:33:29 PM PST 24
Peak memory	315360 kb
Host	smart-1a6f6fda-450e-44ed-b7f3-f7fc2574cea6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897938987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre ss_all.3897938987
Directory	/workspace/44.spi_device_stress_all/latest

Test location	/workspace/coverage/default/3.spi_device_fifo_underflow_overflow.2254288025
Short name	T40
Test name
Test status
Simulation time	562284984175 ps
CPU time	330.14 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	405140 kb
Host	smart-ca9d89a3-c0ea-484e-a8a2-201b52ab81b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254288025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_underflow_overfl ow.2254288025
Directory	/workspace/3.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3240969179
Short name	T131
Test name
Test status
Simulation time	33371642 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:39 PM PST 24
Finished	Jan 07 12:34:57 PM PST 24
Peak memory	204748 kb
Host	smart-d82296d2-ee53-4cbb-a4de-cb6df227e0e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240969179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 3240969179
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/default/15.spi_device_stress_all.3292559200
Short name	T309
Test name
Test status
Simulation time	439284902724 ps
CPU time	2538.78 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 02:03:08 PM PST 24
Peak memory	379980 kb
Host	smart-98c8bb38-2f87-4c7a-be88-3e8689d9cfbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292559200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre ss_all.3292559200
Directory	/workspace/15.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1207368640
Short name	T139
Test name
Test status
Simulation time	105635721 ps
CPU time	1.77 seconds
Started	Jan 07 12:33:38 PM PST 24
Finished	Jan 07 12:35:13 PM PST 24
Peak memory	215744 kb
Host	smart-65a45f5e-87f5-42e4-9b40-dbe5780a4dbc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207368640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1 207368640
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm.1932558451
Short name	T232
Test name
Test status
Simulation time	21550365212 ps
CPU time	122.69 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:24:53 PM PST 24
Peak memory	252492 kb
Host	smart-72033be1-75f2-440c-b5f8-4f44d4040434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932558451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1932558451
Directory	/workspace/27.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/35.spi_device_flash_all.1499666816
Short name	T300
Test name
Test status
Simulation time	329528893777 ps
CPU time	394.25 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:30:35 PM PST 24
Peak memory	268812 kb
Host	smart-97fbe1e6-34ad-418b-adbe-dcd8dcb05ac4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499666816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1499666816
Directory	/workspace/35.spi_device_flash_all/latest

Test location	/workspace/coverage/default/1.spi_device_sec_cm.757935059
Short name	T87
Test name
Test status
Simulation time	118955075 ps
CPU time	1.06 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:41 PM PST 24
Peak memory	238120 kb
Host	smart-021f981e-7422-4b35-9a6e-a37a33faefb8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757935059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.757935059
Directory	/workspace/1.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/47.spi_device_stress_all.2739242836
Short name	T57
Test name
Test status
Simulation time	255377954078 ps
CPU time	622.13 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:35:40 PM PST 24
Peak memory	558332 kb
Host	smart-64b1ea7a-c625-4939-bba6-251fa3cb8ba5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739242836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre ss_all.2739242836
Directory	/workspace/47.spi_device_stress_all/latest

Test location	/workspace/coverage/default/12.spi_device_stress_all.4200891769
Short name	T242
Test name
Test status
Simulation time	102782875321 ps
CPU time	755.38 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:33:03 PM PST 24
Peak memory	273656 kb
Host	smart-c08c6dce-ec04-42b4-b244-f9c65a7aa2eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200891769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre ss_all.4200891769
Directory	/workspace/12.spi_device_stress_all/latest

Test location	/workspace/coverage/default/2.spi_device_bit_transfer.396832240
Short name	T9
Test name
Test status
Simulation time	86256008 ps
CPU time	1.95 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:41 PM PST 24
Peak memory	216676 kb
Host	smart-71812471-99b2-479b-9d0f-b677c4eb3b7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396832240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_bit_transfer.396832240
Directory	/workspace/2.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4290677713
Short name	T206
Test name
Test status
Simulation time	34331602659 ps
CPU time	154.58 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:26:28 PM PST 24
Peak memory	274424 kb
Host	smart-4a239799-fc23-4762-8f3a-2ff2e10cc4e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290677713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl e.4290677713
Directory	/workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3233977748
Short name	T194
Test name
Test status
Simulation time	2298713925 ps
CPU time	23.5 seconds
Started	Jan 07 12:33:10 PM PST 24
Finished	Jan 07 12:35:32 PM PST 24
Peak memory	215792 kb
Host	smart-031de4d8-b6b1-487b-bfd4-e4d299850756
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233977748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.3233977748
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm.2542419485
Short name	T227
Test name
Test status
Simulation time	80847028738 ps
CPU time	157.67 seconds
Started	Jan 07 01:20:57 PM PST 24
Finished	Jan 07 01:23:42 PM PST 24
Peak memory	257896 kb
Host	smart-7704e1f8-9daf-4572-a3e5-fcda49bfd3db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542419485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2542419485
Directory	/workspace/18.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/4.spi_device_flash_mode.313538852
Short name	T682
Test name
Test status
Simulation time	8626733710 ps
CPU time	52.83 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:20:07 PM PST 24
Peak memory	234452 kb
Host	smart-a2c883fa-f6a7-46ea-bdb2-dbfffd45ee2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313538852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.313538852
Directory	/workspace/4.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/0.spi_device_mem_parity.4088723101
Short name	T721
Test name
Test status
Simulation time	182345823 ps
CPU time	1.08 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:21 PM PST 24
Peak memory	218780 kb
Host	smart-719ddbfa-de4e-4832-af1a-62355bcc0be4
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088723101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.spi_device_mem_parity.4088723101
Directory	/workspace/0.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/3.spi_device_stress_all.2371114173
Short name	T105
Test name
Test status
Simulation time	415081181268 ps
CPU time	980.48 seconds
Started	Jan 07 01:19:09 PM PST 24
Finished	Jan 07 01:35:32 PM PST 24
Peak memory	294284 kb
Host	smart-996ecdb4-1f74-47b6-a7aa-191c45f83d68
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371114173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres s_all.2371114173
Directory	/workspace/3.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.2759153090
Short name	T142
Test name
Test status
Simulation time	11867935 ps
CPU time	0.7 seconds
Started	Jan 07 12:33:56 PM PST 24
Finished	Jan 07 12:35:22 PM PST 24
Peak memory	204800 kb
Host	smart-f39ff224-cee1-4307-a3c1-99672f3f0c17
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759153090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 2759153090
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm.1161679630
Short name	T316
Test name
Test status
Simulation time	77800441176 ps
CPU time	526.79 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:30:24 PM PST 24
Peak memory	274172 kb
Host	smart-c20ec282-e18e-4981-8b8e-04ea1c49e92b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161679630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1161679630
Directory	/workspace/20.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/35.spi_device_stress_all.811835721
Short name	T26
Test name
Test status
Simulation time	28670244996 ps
CPU time	288.69 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:28:41 PM PST 24
Peak memory	284328 kb
Host	smart-b5dab94b-a905-4a90-bc77-dc7608a23539
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811835721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres s_all.811835721
Directory	/workspace/35.spi_device_stress_all/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2925485562
Short name	T312
Test name
Test status
Simulation time	10486514651 ps
CPU time	123.35 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:22:01 PM PST 24
Peak memory	267996 kb
Host	smart-a1394d96-1b1d-4d95-ba85-5310e7e3a4bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925485562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle .2925485562
Directory	/workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/7.spi_device_flash_mode.249121701
Short name	T32
Test name
Test status
Simulation time	802396972 ps
CPU time	10.05 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:19:48 PM PST 24
Peak memory	235196 kb
Host	smart-0a9efd4b-6ee0-44f8-b33b-3f469279ab08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249121701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.249121701
Directory	/workspace/7.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/2.spi_device_extreme_fifo_size.640625284
Short name	T13
Test name
Test status
Simulation time	84930546224 ps
CPU time	649.1 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:29:22 PM PST 24
Peak memory	218496 kb
Host	smart-88c2d410-6fcc-473d-9c1c-89a22ae08ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640625284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_extreme_fifo_size.640625284
Directory	/workspace/2.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm.2375239506
Short name	T212
Test name
Test status
Simulation time	54298643643 ps
CPU time	319.37 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:23:43 PM PST 24
Peak memory	256736 kb
Host	smart-4ef4a4db-7045-440c-ac25-c95698a7fac5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375239506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2375239506
Directory	/workspace/0.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4264576094
Short name	T225
Test name
Test status
Simulation time	50162134744 ps
CPU time	190.5 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:24:51 PM PST 24
Peak memory	274260 kb
Host	smart-36c7c5a5-e5ad-4146-955b-2faf1371a843
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264576094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl e.4264576094
Directory	/workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/27.spi_device_flash_all.2862806904
Short name	T320
Test name
Test status
Simulation time	1587110665 ps
CPU time	24.56 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:23:11 PM PST 24
Peak memory	249472 kb
Host	smart-82f86a58-4a9a-4508-83bc-2e372e4991de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862806904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2862806904
Directory	/workspace/27.spi_device_flash_all/latest

Test location	/workspace/coverage/default/39.spi_device_stress_all.3238739530
Short name	T306
Test name
Test status
Simulation time	135242036690 ps
CPU time	449.89 seconds
Started	Jan 07 01:23:59 PM PST 24
Finished	Jan 07 01:31:35 PM PST 24
Peak memory	560480 kb
Host	smart-24990982-1a7e-4040-a2a6-bc6117b3c9e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238739530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre ss_all.3238739530
Directory	/workspace/39.spi_device_stress_all/latest

Test location	/workspace/coverage/default/4.spi_device_extreme_fifo_size.604967707
Short name	T52
Test name
Test status
Simulation time	24840609739 ps
CPU time	1126.48 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:38:15 PM PST 24
Peak memory	224444 kb
Host	smart-febf984e-4125-4590-aee4-21ff2490e508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604967707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_extreme_fifo_size.604967707
Directory	/workspace/4.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/37.spi_device_mailbox.2091575903
Short name	T17
Test name
Test status
Simulation time	932877076 ps
CPU time	6.21 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:06 PM PST 24
Peak memory	224932 kb
Host	smart-34a7a4f6-b979-4abe-84ff-d0ad3b0ad352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091575903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2091575903
Directory	/workspace/37.spi_device_mailbox/latest

Test location	/workspace/coverage/default/20.spi_device_fifo_underflow_overflow.3749083745
Short name	T184
Test name
Test status
Simulation time	501088043793 ps
CPU time	1252.98 seconds
Started	Jan 07 01:21:17 PM PST 24
Finished	Jan 07 01:42:12 PM PST 24
Peak memory	724940 kb
Host	smart-ec86798e-3c17-4165-a044-dc1caf2b2e68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749083745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_underflow_overf low.3749083745
Directory	/workspace/20.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2058888098
Short name	T78
Test name
Test status
Simulation time	127412293 ps
CPU time	1.84 seconds
Started	Jan 07 12:33:51 PM PST 24
Finished	Jan 07 12:35:12 PM PST 24
Peak memory	218624 kb
Host	smart-6e48b1ac-37d5-45fc-bb5b-aa1796935f5e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058888098 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2058888098
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/41.spi_device_stress_all.2799117266
Short name	T162
Test name
Test status
Simulation time	69367548942 ps
CPU time	460.93 seconds
Started	Jan 07 01:24:28 PM PST 24
Finished	Jan 07 01:32:33 PM PST 24
Peak memory	460056 kb
Host	smart-39c60df9-51d8-4c87-b15a-1e020af6c62e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799117266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre ss_all.2799117266
Directory	/workspace/41.spi_device_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.118521314
Short name	T370
Test name
Test status
Simulation time	776364167 ps
CPU time	6.66 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:35:37 PM PST 24
Peak memory	215760 kb
Host	smart-cef591f4-3c22-43ec-a8e7-96da5a08c0be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118521314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device _tl_intg_err.118521314
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/10.spi_device_fifo_underflow_overflow.457257757
Short name	T182
Test name
Test status
Simulation time	373069478644 ps
CPU time	605.32 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:30:01 PM PST 24
Peak memory	379236 kb
Host	smart-9986d3e2-5159-47e4-8c04-602951829531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457257757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_underflow_overfl ow.457257757
Directory	/workspace/10.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/12.spi_device_extreme_fifo_size.1321056873
Short name	T262
Test name
Test status
Simulation time	81711895618 ps
CPU time	1381.44 seconds
Started	Jan 07 01:20:02 PM PST 24
Finished	Jan 07 01:43:14 PM PST 24
Peak memory	220972 kb
Host	smart-98066c44-09e2-4c5c-a395-a7a5111f3982
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321056873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_extreme_fifo_size.1321056873
Directory	/workspace/12.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/13.spi_device_dummy_item_extra_dly.550969263
Short name	T265
Test name
Test status
Simulation time	154287597397 ps
CPU time	191.88 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:23:39 PM PST 24
Peak memory	256832 kb
Host	smart-f554bcde-04ac-4c01-9879-6343bed1c7f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550969263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_dummy_item_extra_dly.550969263
Directory	/workspace/13.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/18.spi_device_dummy_item_extra_dly.1277977242
Short name	T457
Test name
Test status
Simulation time	156134775769 ps
CPU time	168.3 seconds
Started	Jan 07 01:20:57 PM PST 24
Finished	Jan 07 01:23:52 PM PST 24
Peak memory	281752 kb
Host	smart-34cef670-b254-4453-a881-71581469f608
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277977242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_dummy_item_extra_dly.1277977242
Directory	/workspace/18.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/27.spi_device_extreme_fifo_size.925158979
Short name	T178
Test name
Test status
Simulation time	65196819541 ps
CPU time	41.48 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:23:17 PM PST 24
Peak memory	235460 kb
Host	smart-51d134f8-87b8-4f78-a3a0-1f737ea6f465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925158979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_extreme_fifo_size.925158979
Directory	/workspace/27.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.945631497
Short name	T305
Test name
Test status
Simulation time	50198877985 ps
CPU time	437.69 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:26:46 PM PST 24
Peak memory	271060 kb
Host	smart-ce4f47f3-67ab-4852-9280-7024ef0425a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945631497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle. 945631497
Directory	/workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4256405593
Short name	T418
Test name
Test status
Simulation time	61347174 ps
CPU time	1.67 seconds
Started	Jan 07 12:33:41 PM PST 24
Finished	Jan 07 12:35:30 PM PST 24
Peak memory	215860 kb
Host	smart-c89d6882-4921-4cf3-8237-8e356f709736
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256405593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4 256405593
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/12.spi_device_alert_test.1406925543
Short name	T485
Test name
Test status
Simulation time	29772874 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	206536 kb
Host	smart-5f74e16f-b4da-4c9d-8b24-c1c308bbc9b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406925543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test. 1406925543
Directory	/workspace/12.spi_device_alert_test/latest

Test location	/workspace/coverage/default/12.spi_device_rx_async_fifo_reset.550550199
Short name	T665
Test name
Test status
Simulation time	18284801 ps
CPU time	0.87 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	208464 kb
Host	smart-8a08c67c-a394-4529-bd3a-1b4ff2aa18ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550550199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_async_fifo_reset.550550199
Directory	/workspace/12.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/12.spi_device_tx_async_fifo_reset.1417615159
Short name	T602
Test name
Test status
Simulation time	80942124 ps
CPU time	0.77 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:27 PM PST 24
Peak memory	208484 kb
Host	smart-1bfadf38-6c05-41df-a2f1-108b9b8ba1d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417615159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tx_async_fifo_reset.1417615159
Directory	/workspace/12.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1989615030
Short name	T152
Test name
Test status
Simulation time	362139320 ps
CPU time	23.55 seconds
Started	Jan 07 12:33:28 PM PST 24
Finished	Jan 07 12:34:54 PM PST 24
Peak memory	217052 kb
Host	smart-d3cfe1bb-1f69-4ded-9c8a-df0911ee9f53
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989615030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.1989615030
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4124518079
Short name	T398
Test name
Test status
Simulation time	21514994 ps
CPU time	1.03 seconds
Started	Jan 07 12:32:48 PM PST 24
Finished	Jan 07 12:34:45 PM PST 24
Peak memory	207348 kb
Host	smart-fa756037-0294-462f-b2fe-6c65889cdd64
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124518079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.4124518079
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1215919975
Short name	T132
Test name
Test status
Simulation time	64919493 ps
CPU time	1.76 seconds
Started	Jan 07 12:33:22 PM PST 24
Finished	Jan 07 12:34:28 PM PST 24
Peak memory	217284 kb
Host	smart-5b98ebee-24af-4239-a1eb-d059f06fea04
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215919975 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1215919975
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.4290663123
Short name	T135
Test name
Test status
Simulation time	12489691 ps
CPU time	0.68 seconds
Started	Jan 07 12:33:27 PM PST 24
Finished	Jan 07 12:34:51 PM PST 24
Peak memory	204840 kb
Host	smart-a5224d77-21ef-4c22-8c82-e28a1017d633
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290663123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4 290663123
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3038392657
Short name	T155
Test name
Test status
Simulation time	214986646 ps
CPU time	2.56 seconds
Started	Jan 07 12:32:58 PM PST 24
Finished	Jan 07 12:34:18 PM PST 24
Peak memory	215776 kb
Host	smart-c82979ae-af2f-475f-8614-7131dcfc1632
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038392657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.3038392657
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1186780505
Short name	T401
Test name
Test status
Simulation time	1066959763 ps
CPU time	11.74 seconds
Started	Jan 07 12:33:38 PM PST 24
Finished	Jan 07 12:35:05 PM PST 24
Peak memory	215612 kb
Host	smart-c03ffd75-eedf-4b32-8991-bb581fc21915
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186780505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me m_walk.1186780505
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4156036848
Short name	T389
Test name
Test status
Simulation time	226033118 ps
CPU time	4.33 seconds
Started	Jan 07 12:33:03 PM PST 24
Finished	Jan 07 12:34:32 PM PST 24
Peak memory	215748 kb
Host	smart-7a149def-7809-4656-b826-cfca20f3241c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156036848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.4156036848
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.451936956
Short name	T154
Test name
Test status
Simulation time	3109259479 ps
CPU time	8.78 seconds
Started	Jan 07 12:33:12 PM PST 24
Finished	Jan 07 12:34:44 PM PST 24
Peak memory	207580 kb
Host	smart-e8fff6e3-0c3c-4050-be93-63fdf4d13504
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451936956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _aliasing.451936956
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.200700898
Short name	T153
Test name
Test status
Simulation time	16685397991 ps
CPU time	40.89 seconds
Started	Jan 07 12:33:02 PM PST 24
Finished	Jan 07 12:35:52 PM PST 24
Peak memory	215844 kb
Host	smart-be818542-0a8c-4f02-a34f-f9300b98786d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200700898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _bit_bash.200700898
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2979327765
Short name	T423
Test name
Test status
Simulation time	34128168 ps
CPU time	0.97 seconds
Started	Jan 07 12:33:04 PM PST 24
Finished	Jan 07 12:34:25 PM PST 24
Peak memory	207388 kb
Host	smart-45e66315-c3d0-43a5-9b91-24f4f176967f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979327765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.2979327765
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1704566230
Short name	T351
Test name
Test status
Simulation time	121484941 ps
CPU time	1.26 seconds
Started	Jan 07 12:33:21 PM PST 24
Finished	Jan 07 12:35:00 PM PST 24
Peak memory	216952 kb
Host	smart-b90bc369-36a6-41a5-b622-f230cd238199
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704566230 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1704566230
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2086692434
Short name	T381
Test name
Test status
Simulation time	121568774 ps
CPU time	1.17 seconds
Started	Jan 07 12:33:18 PM PST 24
Finished	Jan 07 12:34:31 PM PST 24
Peak memory	215672 kb
Host	smart-7dc51451-edbd-41f6-9348-ebc307d9f690
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086692434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2 086692434
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.3323184323
Short name	T186
Test name
Test status
Simulation time	30290989 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:30 PM PST 24
Finished	Jan 07 12:35:38 PM PST 24
Peak memory	204768 kb
Host	smart-e6ccba36-3a7b-48e8-9e1a-c8a1b1ef709c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323184323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3 323184323
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1733318308
Short name	T148
Test name
Test status
Simulation time	91464816 ps
CPU time	2.34 seconds
Started	Jan 07 12:33:11 PM PST 24
Finished	Jan 07 12:34:28 PM PST 24
Peak memory	215720 kb
Host	smart-968b0add-c9ab-40d1-b26b-d92fb6402f71
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733318308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.1733318308
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3027438228
Short name	T408
Test name
Test status
Simulation time	392369631 ps
CPU time	13.78 seconds
Started	Jan 07 12:33:07 PM PST 24
Finished	Jan 07 12:35:13 PM PST 24
Peak memory	215756 kb
Host	smart-f7ac0f54-62e8-4744-b39b-dfbcf7374179
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027438228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.3027438228
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2119849030
Short name	T390
Test name
Test status
Simulation time	222579954 ps
CPU time	2.94 seconds
Started	Jan 07 12:33:02 PM PST 24
Finished	Jan 07 12:34:39 PM PST 24
Peak memory	215748 kb
Host	smart-1dc43e89-f831-4904-a227-af2f71432a2b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119849030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.2119849030
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3102765401
Short name	T420
Test name
Test status
Simulation time	752587046 ps
CPU time	12.34 seconds
Started	Jan 07 12:33:04 PM PST 24
Finished	Jan 07 12:34:30 PM PST 24
Peak memory	215680 kb
Host	smart-80faa459-e5d2-444c-a089-b142aec767e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102765401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.3102765401
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3426091564
Short name	T376
Test name
Test status
Simulation time	67860860 ps
CPU time	1.75 seconds
Started	Jan 07 12:33:52 PM PST 24
Finished	Jan 07 12:35:06 PM PST 24
Peak memory	217836 kb
Host	smart-0638016c-85f6-47bb-b22d-e13945975051
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426091564 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3426091564
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2554677146
Short name	T387
Test name
Test status
Simulation time	14352210 ps
CPU time	0.78 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:35:31 PM PST 24
Peak memory	204788 kb
Host	smart-979d52ea-2b05-43b8-8f82-b223a1cc0664
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554677146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 2554677146
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1288822786
Short name	T399
Test name
Test status
Simulation time	96995345 ps
CPU time	1.48 seconds
Started	Jan 07 12:36:48 PM PST 24
Finished	Jan 07 12:37:55 PM PST 24
Peak memory	215896 kb
Host	smart-92e797d7-6931-49f8-880a-2800b6e3fff0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288822786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 1288822786
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.174237376
Short name	T129
Test name
Test status
Simulation time	922361740 ps
CPU time	7.42 seconds
Started	Jan 07 12:33:42 PM PST 24
Finished	Jan 07 12:34:54 PM PST 24
Peak memory	215776 kb
Host	smart-361e532e-46f4-417e-a8b4-ffee00b21ef3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174237376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device _tl_intg_err.174237376
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.735025425
Short name	T355
Test name
Test status
Simulation time	36210330 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:31 PM PST 24
Finished	Jan 07 12:35:10 PM PST 24
Peak memory	204772 kb
Host	smart-9804cf32-3ac9-4a17-95d6-d32544da4861
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735025425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.735025425
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2776324983
Short name	T417
Test name
Test status
Simulation time	157049307 ps
CPU time	3.22 seconds
Started	Jan 07 12:33:23 PM PST 24
Finished	Jan 07 12:35:04 PM PST 24
Peak memory	215616 kb
Host	smart-ef4cb996-1856-4d0c-b906-b77659be087a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776324983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.2776324983
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3934194938
Short name	T122
Test name
Test status
Simulation time	27759948 ps
CPU time	1.6 seconds
Started	Jan 07 12:33:15 PM PST 24
Finished	Jan 07 12:34:26 PM PST 24
Peak memory	215872 kb
Host	smart-dd5c093f-e12e-4ce4-8a35-3f1dd63927a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934194938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors. 3934194938
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2816622276
Short name	T140
Test name
Test status
Simulation time	77320224 ps
CPU time	1.83 seconds
Started	Jan 07 12:33:51 PM PST 24
Finished	Jan 07 12:35:11 PM PST 24
Peak memory	215584 kb
Host	smart-58317b3b-1469-4029-8db7-4cb77fafe612
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816622276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 2816622276
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2959196167
Short name	T130
Test name
Test status
Simulation time	50242629 ps
CPU time	0.71 seconds
Started	Jan 07 12:33:27 PM PST 24
Finished	Jan 07 12:34:44 PM PST 24
Peak memory	204740 kb
Host	smart-f0867c6b-8f15-475f-af38-cafa6acf2919
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959196167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 2959196167
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3061305822
Short name	T409
Test name
Test status
Simulation time	178231759 ps
CPU time	4.32 seconds
Started	Jan 07 12:33:44 PM PST 24
Finished	Jan 07 12:35:14 PM PST 24
Peak memory	215644 kb
Host	smart-0284f3a8-ac38-4818-888e-0022167e1ae7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061305822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.3061305822
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3914584092
Short name	T120
Test name
Test status
Simulation time	48272314 ps
CPU time	1.74 seconds
Started	Jan 07 12:33:40 PM PST 24
Finished	Jan 07 12:34:42 PM PST 24
Peak memory	215864 kb
Host	smart-d744a9a1-4c82-4cc5-a404-29cc123c97a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914584092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 3914584092
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2586198918
Short name	T366
Test name
Test status
Simulation time	1699924719 ps
CPU time	13.81 seconds
Started	Jan 07 12:33:42 PM PST 24
Finished	Jan 07 12:34:53 PM PST 24
Peak memory	215796 kb
Host	smart-a4a8cfb9-8b5f-4d15-8652-0bfb8c9bd2fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586198918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.2586198918
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4241964328
Short name	T373
Test name
Test status
Simulation time	155351083 ps
CPU time	2.29 seconds
Started	Jan 07 12:33:22 PM PST 24
Finished	Jan 07 12:34:52 PM PST 24
Peak memory	219792 kb
Host	smart-6e57be89-5fb1-4f28-bba0-a01bfda135e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241964328 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4241964328
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3489156985
Short name	T416
Test name
Test status
Simulation time	157344872 ps
CPU time	1.96 seconds
Started	Jan 07 12:33:57 PM PST 24
Finished	Jan 07 12:35:42 PM PST 24
Peak memory	215672 kb
Host	smart-1ba69137-b580-42b8-8fab-b2c8b3f74d6b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489156985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 3489156985
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3117282403
Short name	T369
Test name
Test status
Simulation time	342802700 ps
CPU time	3.61 seconds
Started	Jan 07 12:35:19 PM PST 24
Finished	Jan 07 12:36:33 PM PST 24
Peak memory	215372 kb
Host	smart-5287e6c1-f07e-4536-a9a1-08ecfd33021b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117282403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.3117282403
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3054800468
Short name	T383
Test name
Test status
Simulation time	248578548 ps
CPU time	1.93 seconds
Started	Jan 07 12:33:15 PM PST 24
Finished	Jan 07 12:34:20 PM PST 24
Peak memory	215836 kb
Host	smart-05391c2e-1c44-40e7-bc65-88fc55448df5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054800468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 3054800468
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2195828315
Short name	T195
Test name
Test status
Simulation time	1771974897 ps
CPU time	13.33 seconds
Started	Jan 07 12:33:51 PM PST 24
Finished	Jan 07 12:35:32 PM PST 24
Peak memory	215728 kb
Host	smart-2cc42684-403c-4d97-bd5a-9d993685def6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195828315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.2195828315
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1768095366
Short name	T141
Test name
Test status
Simulation time	109144276 ps
CPU time	1.22 seconds
Started	Jan 07 12:33:50 PM PST 24
Finished	Jan 07 12:35:06 PM PST 24
Peak memory	215624 kb
Host	smart-daf7e4f6-499f-4dc6-b698-33678ec11bf1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768095366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 1768095366
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.1627801947
Short name	T374
Test name
Test status
Simulation time	14496213 ps
CPU time	0.7 seconds
Started	Jan 07 12:35:11 PM PST 24
Finished	Jan 07 12:36:29 PM PST 24
Peak memory	204540 kb
Host	smart-3dd4f2f9-6e8b-447c-bd84-c0481df986ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627801947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 1627801947
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2331389599
Short name	T415
Test name
Test status
Simulation time	651856703 ps
CPU time	3.19 seconds
Started	Jan 07 12:33:33 PM PST 24
Finished	Jan 07 12:35:20 PM PST 24
Peak memory	215576 kb
Host	smart-275b558a-7bb1-4231-8c99-cd782f9f9c6d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331389599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.2331389599
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.757476057
Short name	T380
Test name
Test status
Simulation time	111617213 ps
CPU time	2.56 seconds
Started	Jan 07 12:33:44 PM PST 24
Finished	Jan 07 12:34:44 PM PST 24
Peak memory	215812 kb
Host	smart-8e178ed7-3425-4cab-a429-dbde9483887f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757476057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.757476057
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.216642247
Short name	T358
Test name
Test status
Simulation time	148956777 ps
CPU time	2.1 seconds
Started	Jan 07 12:35:10 PM PST 24
Finished	Jan 07 12:36:58 PM PST 24
Peak memory	218048 kb
Host	smart-2712f6b4-442b-4f99-96f7-d55eb71c3460
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216642247 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.216642247
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2019546434
Short name	T151
Test name
Test status
Simulation time	23347334 ps
CPU time	1.26 seconds
Started	Jan 07 12:35:47 PM PST 24
Finished	Jan 07 12:37:52 PM PST 24
Peak memory	215392 kb
Host	smart-ba57b708-96b3-4798-8496-99c934fa85af
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019546434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 2019546434
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.540774371
Short name	T384
Test name
Test status
Simulation time	20482109 ps
CPU time	0.67 seconds
Started	Jan 07 12:35:04 PM PST 24
Finished	Jan 07 12:36:48 PM PST 24
Peak memory	204564 kb
Host	smart-3a9c65f5-2f24-48d3-88cd-ca9aa13b937d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540774371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.540774371
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.840438908
Short name	T81
Test name
Test status
Simulation time	60770838 ps
CPU time	3.61 seconds
Started	Jan 07 12:33:55 PM PST 24
Finished	Jan 07 12:35:03 PM PST 24
Peak memory	215612 kb
Host	smart-6185a87e-91c1-4bdf-8de9-2251cf969544
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840438908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s pi_device_same_csr_outstanding.840438908
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.291624285
Short name	T157
Test name
Test status
Simulation time	2233879234 ps
CPU time	2.63 seconds
Started	Jan 07 12:35:33 PM PST 24
Finished	Jan 07 12:36:41 PM PST 24
Peak memory	215472 kb
Host	smart-59ea4af2-2c4e-4588-a381-2edacd22dd74
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291624285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.291624285
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.645674726
Short name	T396
Test name
Test status
Simulation time	30731093 ps
CPU time	0.65 seconds
Started	Jan 07 12:35:47 PM PST 24
Finished	Jan 07 12:37:08 PM PST 24
Peak memory	204564 kb
Host	smart-6d8eda36-ad2b-48f9-82d8-6e1bd2bf5f30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645674726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.645674726
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3232996325
Short name	T400
Test name
Test status
Simulation time	28898560 ps
CPU time	1.82 seconds
Started	Jan 07 12:33:31 PM PST 24
Finished	Jan 07 12:35:21 PM PST 24
Peak memory	215612 kb
Host	smart-fe25dbd2-e40f-41b9-8563-5e24539a5ef6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232996325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.3232996325
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1146131825
Short name	T112
Test name
Test status
Simulation time	765429062 ps
CPU time	2.28 seconds
Started	Jan 07 12:33:54 PM PST 24
Finished	Jan 07 12:35:41 PM PST 24
Peak memory	215968 kb
Host	smart-aaf50908-a47c-4a8e-b35f-be273b96d574
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146131825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 1146131825
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.411243260
Short name	T197
Test name
Test status
Simulation time	302562531 ps
CPU time	16.88 seconds
Started	Jan 07 12:34:39 PM PST 24
Finished	Jan 07 12:36:13 PM PST 24
Peak memory	214900 kb
Host	smart-599da593-402e-4cc1-b49b-81a051480048
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411243260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device _tl_intg_err.411243260
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2341752381
Short name	T171
Test name
Test status
Simulation time	120954953 ps
CPU time	1.77 seconds
Started	Jan 07 12:35:47 PM PST 24
Finished	Jan 07 12:37:23 PM PST 24
Peak memory	217256 kb
Host	smart-aab3d6a8-7eae-4f04-86b6-ef3f09d09fba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341752381 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2341752381
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2950429597
Short name	T427
Test name
Test status
Simulation time	74369903 ps
CPU time	2.36 seconds
Started	Jan 07 12:35:11 PM PST 24
Finished	Jan 07 12:36:22 PM PST 24
Peak memory	206816 kb
Host	smart-e8bf8525-64e8-4c5e-b22b-ad3e3352a8c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950429597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw. 2950429597
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3441419581
Short name	T123
Test name
Test status
Simulation time	61331173 ps
CPU time	1.71 seconds
Started	Jan 07 12:35:40 PM PST 24
Finished	Jan 07 12:37:08 PM PST 24
Peak memory	215688 kb
Host	smart-be6e612b-f2a6-43e1-b95c-250bc6b947df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441419581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors. 3441419581
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1315957488
Short name	T359
Test name
Test status
Simulation time	84452818 ps
CPU time	2.2 seconds
Started	Jan 07 12:33:52 PM PST 24
Finished	Jan 07 12:35:19 PM PST 24
Peak memory	218236 kb
Host	smart-af3d341f-2ac7-4e16-98e5-9aca3ad84f12
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315957488 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1315957488
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2358190827
Short name	T353
Test name
Test status
Simulation time	14088522 ps
CPU time	0.67 seconds
Started	Jan 07 12:35:26 PM PST 24
Finished	Jan 07 12:36:44 PM PST 24
Peak memory	204564 kb
Host	smart-c40d80a6-9a3b-46b9-8742-93cb1bd69d9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358190827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 2358190827
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3648897940
Short name	T411
Test name
Test status
Simulation time	177249594 ps
CPU time	2.61 seconds
Started	Jan 07 12:34:56 PM PST 24
Finished	Jan 07 12:36:32 PM PST 24
Peak memory	215388 kb
Host	smart-4936a46b-e218-4bb3-99bd-ebd1502cbd37
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648897940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.3648897940
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3061233513
Short name	T368
Test name
Test status
Simulation time	781484947 ps
CPU time	3.64 seconds
Started	Jan 07 12:33:49 PM PST 24
Finished	Jan 07 12:36:03 PM PST 24
Peak memory	215944 kb
Host	smart-ef20049d-5ade-4fa1-a011-d03861bad5ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061233513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 3061233513
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3633539447
Short name	T393
Test name
Test status
Simulation time	59228006 ps
CPU time	1.73 seconds
Started	Jan 07 12:33:24 PM PST 24
Finished	Jan 07 12:34:33 PM PST 24
Peak memory	215672 kb
Host	smart-7092a0c2-83cc-487b-a91a-d7e34b1a242b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633539447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 3633539447
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3642984293
Short name	T363
Test name
Test status
Simulation time	68072160 ps
CPU time	3.99 seconds
Started	Jan 07 12:34:00 PM PST 24
Finished	Jan 07 12:35:41 PM PST 24
Peak memory	216672 kb
Host	smart-05aa4406-ddb3-4aa4-9fb8-91b0b96f3c7d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642984293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.3642984293
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1612645818
Short name	T121
Test name
Test status
Simulation time	572060310 ps
CPU time	5.25 seconds
Started	Jan 07 12:33:36 PM PST 24
Finished	Jan 07 12:34:40 PM PST 24
Peak memory	215828 kb
Host	smart-a1b72a97-f0f1-44d2-902f-0981b8b4bd7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612645818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 1612645818
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3768907571
Short name	T137
Test name
Test status
Simulation time	567620859 ps
CPU time	7.29 seconds
Started	Jan 07 12:33:06 PM PST 24
Finished	Jan 07 12:34:23 PM PST 24
Peak memory	216508 kb
Host	smart-f6ff78a1-02e8-40f0-a3be-867883c4db9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768907571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.3768907571
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3405200106
Short name	T173
Test name
Test status
Simulation time	862844153 ps
CPU time	16.68 seconds
Started	Jan 07 12:33:31 PM PST 24
Finished	Jan 07 12:35:35 PM PST 24
Peak memory	216680 kb
Host	smart-82f4b371-55bc-48d7-9c1f-e3c8201a28f8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405200106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.3405200106
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3692403692
Short name	T405
Test name
Test status
Simulation time	46313190 ps
CPU time	0.95 seconds
Started	Jan 07 12:33:47 PM PST 24
Finished	Jan 07 12:35:25 PM PST 24
Peak memory	207428 kb
Host	smart-5fac2565-2a29-4ccb-a0c2-577d8b22cd3f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692403692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.3692403692
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.468670576
Short name	T421
Test name
Test status
Simulation time	138562077 ps
CPU time	2.18 seconds
Started	Jan 07 12:33:28 PM PST 24
Finished	Jan 07 12:34:33 PM PST 24
Peak memory	218516 kb
Host	smart-5174e331-5165-493e-a6d0-30b4af6d8265
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468670576 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.468670576
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3272771027
Short name	T386
Test name
Test status
Simulation time	182814614 ps
CPU time	1.32 seconds
Started	Jan 07 12:33:16 PM PST 24
Finished	Jan 07 12:35:00 PM PST 24
Peak memory	215680 kb
Host	smart-f4f84cb4-2541-470f-8c4b-4f2843b55bfd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272771027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3 272771027
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1636643705
Short name	T382
Test name
Test status
Simulation time	23898562 ps
CPU time	0.67 seconds
Started	Jan 07 12:33:04 PM PST 24
Finished	Jan 07 12:34:17 PM PST 24
Peak memory	204796 kb
Host	smart-4d3d482d-3856-4101-b846-0f326ffe4b0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636643705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1 636643705
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1402612568
Short name	T156
Test name
Test status
Simulation time	150394909 ps
CPU time	2.46 seconds
Started	Jan 07 12:33:45 PM PST 24
Finished	Jan 07 12:35:07 PM PST 24
Peak memory	215764 kb
Host	smart-9f18f7a9-f983-4835-bc9c-29e97a21c9df
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402612568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.1402612568
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3959635171
Short name	T145
Test name
Test status
Simulation time	65641153 ps
CPU time	3.82 seconds
Started	Jan 07 12:33:25 PM PST 24
Finished	Jan 07 12:34:53 PM PST 24
Peak memory	215656 kb
Host	smart-63c7909a-99b4-4157-92c0-2aa16dc73a8c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959635171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3959635171
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1305515030
Short name	T113
Test name
Test status
Simulation time	331216717 ps
CPU time	3.64 seconds
Started	Jan 07 12:32:46 PM PST 24
Finished	Jan 07 12:34:12 PM PST 24
Peak memory	215784 kb
Host	smart-453b6e29-5610-42b5-8e97-71ce7fb5031e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305515030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1 305515030
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3814252639
Short name	T172
Test name
Test status
Simulation time	334330160 ps
CPU time	7.23 seconds
Started	Jan 07 12:33:23 PM PST 24
Finished	Jan 07 12:34:33 PM PST 24
Peak memory	215684 kb
Host	smart-7e9ecfe4-47bd-4a5a-bf14-8fb2d60aae8f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814252639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device _tl_intg_err.3814252639
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.24797137
Short name	T66
Test name
Test status
Simulation time	40787924 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:36:01 PM PST 24
Peak memory	204812 kb
Host	smart-26a396e4-9c2b-4cea-857d-29a0be3807c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24797137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.24797137
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2058035844
Short name	T352
Test name
Test status
Simulation time	11853445 ps
CPU time	0.66 seconds
Started	Jan 07 12:33:13 PM PST 24
Finished	Jan 07 12:34:29 PM PST 24
Peak memory	204740 kb
Host	smart-e4348661-6b19-45f7-8f81-83d76d7c4a5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058035844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 2058035844
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.913937955
Short name	T392
Test name
Test status
Simulation time	13431189 ps
CPU time	0.7 seconds
Started	Jan 07 12:33:16 PM PST 24
Finished	Jan 07 12:34:51 PM PST 24
Peak memory	204732 kb
Host	smart-c680e79c-04b5-49ab-9dc9-1bf6430f4573
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913937955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.913937955
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.428117229
Short name	T356
Test name
Test status
Simulation time	16087609 ps
CPU time	0.73 seconds
Started	Jan 07 12:33:51 PM PST 24
Finished	Jan 07 12:35:20 PM PST 24
Peak memory	204732 kb
Host	smart-bd70d4d8-e89b-4337-96b6-1507f9d67180
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428117229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.428117229
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2284042821
Short name	T375
Test name
Test status
Simulation time	34413119 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:50 PM PST 24
Finished	Jan 07 12:35:28 PM PST 24
Peak memory	204764 kb
Host	smart-38078a9c-ce77-4366-abfa-53f56a001a75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284042821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 2284042821
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2715332846
Short name	T83
Test name
Test status
Simulation time	13394067 ps
CPU time	0.73 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:36:56 PM PST 24
Peak memory	204764 kb
Host	smart-4063432b-f336-45e3-9c79-a45bc472e6b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715332846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 2715332846
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2121532523
Short name	T68
Test name
Test status
Simulation time	506078217 ps
CPU time	15.62 seconds
Started	Jan 07 12:33:18 PM PST 24
Finished	Jan 07 12:34:46 PM PST 24
Peak memory	207468 kb
Host	smart-4bb06ed4-2970-49bd-a34c-5711ad2d3817
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121532523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.2121532523
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4142652168
Short name	T424
Test name
Test status
Simulation time	3049454096 ps
CPU time	40.2 seconds
Started	Jan 07 12:33:05 PM PST 24
Finished	Jan 07 12:35:18 PM PST 24
Peak memory	215656 kb
Host	smart-2e49e7ec-67d5-48a5-a230-3f6652753d3d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142652168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.4142652168
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2196663390
Short name	T147
Test name
Test status
Simulation time	193260459 ps
CPU time	1.46 seconds
Started	Jan 07 12:33:52 PM PST 24
Finished	Jan 07 12:35:01 PM PST 24
Peak memory	207480 kb
Host	smart-a49aa233-e27c-4402-8a37-2367c99b54cb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196663390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.2196663390
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2785557101
Short name	T406
Test name
Test status
Simulation time	60135696 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:32 PM PST 24
Finished	Jan 07 12:34:32 PM PST 24
Peak memory	204780 kb
Host	smart-ad5e75ba-0db8-4183-a945-8d878eaac580
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785557101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2 785557101
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3149774049
Short name	T149
Test name
Test status
Simulation time	146207957 ps
CPU time	4.69 seconds
Started	Jan 07 12:33:13 PM PST 24
Finished	Jan 07 12:36:43 PM PST 24
Peak memory	215756 kb
Host	smart-199426b0-a94c-4d98-840b-6425fa2acaec
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149774049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.3149774049
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.381308262
Short name	T379
Test name
Test status
Simulation time	195962612 ps
CPU time	11.99 seconds
Started	Jan 07 12:33:18 PM PST 24
Finished	Jan 07 12:34:45 PM PST 24
Peak memory	215720 kb
Host	smart-93d195b7-33ca-4361-a2e9-8ea24800be6b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381308262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem _walk.381308262
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4185138177
Short name	T394
Test name
Test status
Simulation time	45294437 ps
CPU time	2.57 seconds
Started	Jan 07 12:33:25 PM PST 24
Finished	Jan 07 12:34:30 PM PST 24
Peak memory	215588 kb
Host	smart-8804cc0f-7963-43e9-a54d-df28de161f3c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185138177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s pi_device_same_csr_outstanding.4185138177
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.601442020
Short name	T116
Test name
Test status
Simulation time	1002877828 ps
CPU time	21.72 seconds
Started	Jan 07 12:33:30 PM PST 24
Finished	Jan 07 12:35:51 PM PST 24
Peak memory	216000 kb
Host	smart-a3d98de1-a61e-4361-96ff-db17547e47c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601442020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_ tl_intg_err.601442020
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.3241933556
Short name	T357
Test name
Test status
Simulation time	14631518 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:31 PM PST 24
Finished	Jan 07 12:35:20 PM PST 24
Peak memory	204780 kb
Host	smart-bb4ab354-0686-48e0-8c3b-24603dc58b05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241933556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 3241933556
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.382473840
Short name	T65
Test name
Test status
Simulation time	83111065 ps
CPU time	0.69 seconds
Started	Jan 07 12:35:19 PM PST 24
Finished	Jan 07 12:36:45 PM PST 24
Peak memory	204540 kb
Host	smart-66647394-e108-4a4f-9c6b-3771b201e535
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382473840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.382473840
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.3480630019
Short name	T385
Test name
Test status
Simulation time	45479409 ps
CPU time	0.7 seconds
Started	Jan 07 12:33:52 PM PST 24
Finished	Jan 07 12:35:16 PM PST 24
Peak memory	204768 kb
Host	smart-27d46f79-3cae-4b1f-a86a-91bf81e2fb39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480630019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test. 3480630019
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1494346541
Short name	T67
Test name
Test status
Simulation time	16040033 ps
CPU time	0.74 seconds
Started	Jan 07 12:35:11 PM PST 24
Finished	Jan 07 12:36:22 PM PST 24
Peak memory	204540 kb
Host	smart-4395c118-3213-416c-ab91-403a92bf0175
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494346541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 1494346541
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3337223621
Short name	T422
Test name
Test status
Simulation time	15694580 ps
CPU time	0.79 seconds
Started	Jan 07 12:34:52 PM PST 24
Finished	Jan 07 12:36:12 PM PST 24
Peak memory	204060 kb
Host	smart-2945de62-ec08-42f0-bca2-e29c97ecb9b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337223621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 3337223621
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1506590210
Short name	T425
Test name
Test status
Simulation time	19905350 ps
CPU time	0.75 seconds
Started	Jan 07 12:33:44 PM PST 24
Finished	Jan 07 12:35:16 PM PST 24
Peak memory	204724 kb
Host	smart-4d4ed607-8ef7-4993-af72-a285fb7b42a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506590210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 1506590210
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.954790668
Short name	T402
Test name
Test status
Simulation time	20701826 ps
CPU time	0.67 seconds
Started	Jan 07 12:35:58 PM PST 24
Finished	Jan 07 12:37:33 PM PST 24
Peak memory	204548 kb
Host	smart-7f557dbf-be43-499c-91b3-521ca4fad0bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954790668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.954790668
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2078231359
Short name	T377
Test name
Test status
Simulation time	55031142 ps
CPU time	0.73 seconds
Started	Jan 07 12:33:45 PM PST 24
Finished	Jan 07 12:35:09 PM PST 24
Peak memory	204720 kb
Host	smart-28fb0802-588c-4b4e-8e34-ed36ed497491
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078231359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 2078231359
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2182644309
Short name	T371
Test name
Test status
Simulation time	204242209 ps
CPU time	12.57 seconds
Started	Jan 07 12:33:01 PM PST 24
Finished	Jan 07 12:34:29 PM PST 24
Peak memory	215664 kb
Host	smart-f04a1451-7f7f-42aa-b76f-3bf54def7f12
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182644309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_bit_bash.2182644309
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2331950930
Short name	T407
Test name
Test status
Simulation time	19283120 ps
CPU time	1.15 seconds
Started	Jan 07 12:33:21 PM PST 24
Finished	Jan 07 12:35:58 PM PST 24
Peak memory	207412 kb
Host	smart-6b491fb8-b1b4-4d67-803b-03eb926f287c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331950930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.2331950930
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.14367017
Short name	T64
Test name
Test status
Simulation time	18077100 ps
CPU time	1.15 seconds
Started	Jan 07 12:33:34 PM PST 24
Finished	Jan 07 12:34:47 PM PST 24
Peak memory	216924 kb
Host	smart-70a10b71-f7b5-486f-8b4a-61b8b62eabb0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367017 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.14367017
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.2001067418
Short name	T360
Test name
Test status
Simulation time	11521227 ps
CPU time	0.67 seconds
Started	Jan 07 12:33:02 PM PST 24
Finished	Jan 07 12:34:40 PM PST 24
Peak memory	204692 kb
Host	smart-52b4aeba-6417-4ab8-8ed8-eae99e8c7a65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001067418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2 001067418
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1942198962
Short name	T150
Test name
Test status
Simulation time	692053473 ps
CPU time	5.13 seconds
Started	Jan 07 12:33:21 PM PST 24
Finished	Jan 07 12:34:31 PM PST 24
Peak memory	215656 kb
Host	smart-65724d57-5d5e-4fb1-8ba5-ae9729ee7a0d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942198962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.1942198962
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2679314898
Short name	T146
Test name
Test status
Simulation time	74975582 ps
CPU time	4.82 seconds
Started	Jan 07 12:33:42 PM PST 24
Finished	Jan 07 12:35:20 PM PST 24
Peak memory	215716 kb
Host	smart-40e57c78-7568-4048-886e-3880f90d9c49
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679314898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.2679314898
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3099694166
Short name	T158
Test name
Test status
Simulation time	630933507 ps
CPU time	3.01 seconds
Started	Jan 07 12:32:52 PM PST 24
Finished	Jan 07 12:34:52 PM PST 24
Peak memory	215764 kb
Host	smart-32ab48b0-7309-4e32-a404-7d84de227276
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099694166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.3099694166
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4264409173
Short name	T426
Test name
Test status
Simulation time	514449328 ps
CPU time	4.74 seconds
Started	Jan 07 12:32:58 PM PST 24
Finished	Jan 07 12:34:34 PM PST 24
Peak memory	215728 kb
Host	smart-6c1955d3-f2b8-40e4-b59f-06586c13c2f7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264409173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4 264409173
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1594533857
Short name	T196
Test name
Test status
Simulation time	4137782643 ps
CPU time	14.58 seconds
Started	Jan 07 12:33:23 PM PST 24
Finished	Jan 07 12:34:59 PM PST 24
Peak memory	216916 kb
Host	smart-6e8c6690-935c-448f-94ce-2c515089d9d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594533857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.1594533857
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.2074586530
Short name	T354
Test name
Test status
Simulation time	28994441 ps
CPU time	0.67 seconds
Started	Jan 07 12:33:55 PM PST 24
Finished	Jan 07 12:35:05 PM PST 24
Peak memory	204724 kb
Host	smart-de1bd950-586d-44ba-9271-47b918c38d18
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074586530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 2074586530
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.1581003027
Short name	T413
Test name
Test status
Simulation time	15735260 ps
CPU time	0.7 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:34:56 PM PST 24
Peak memory	204772 kb
Host	smart-0d3bd216-d293-4c58-8db0-11feed7ed7b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581003027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 1581003027
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.654651405
Short name	T412
Test name
Test status
Simulation time	22195793 ps
CPU time	0.7 seconds
Started	Jan 07 12:35:15 PM PST 24
Finished	Jan 07 12:36:33 PM PST 24
Peak memory	204248 kb
Host	smart-aa48f4a2-c858-4ccd-8fc5-8954bebd4083
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654651405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.654651405
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.61307542
Short name	T378
Test name
Test status
Simulation time	16279132 ps
CPU time	0.73 seconds
Started	Jan 07 12:35:03 PM PST 24
Finished	Jan 07 12:36:43 PM PST 24
Peak memory	204564 kb
Host	smart-2df91851-51ee-49ac-9dae-23aab56c9983
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61307542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.61307542
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2835514243
Short name	T403
Test name
Test status
Simulation time	12489177 ps
CPU time	0.71 seconds
Started	Jan 07 12:36:13 PM PST 24
Finished	Jan 07 12:37:29 PM PST 24
Peak memory	204556 kb
Host	smart-3348e363-c4a5-4016-83cc-69af8512248f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835514243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 2835514243
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.115157157
Short name	T144
Test name
Test status
Simulation time	24900979 ps
CPU time	0.69 seconds
Started	Jan 07 12:33:22 PM PST 24
Finished	Jan 07 12:34:31 PM PST 24
Peak memory	204712 kb
Host	smart-3a30cf8f-14a8-4123-be6f-facd9289538c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115157157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.115157157
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1714861418
Short name	T364
Test name
Test status
Simulation time	53710574 ps
CPU time	0.71 seconds
Started	Jan 07 12:36:00 PM PST 24
Finished	Jan 07 12:37:12 PM PST 24
Peak memory	204604 kb
Host	smart-da1794a9-f969-46bf-8b09-efa27dfe8d46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714861418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 1714861418
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2453520314
Short name	T395
Test name
Test status
Simulation time	794849351 ps
CPU time	2.29 seconds
Started	Jan 07 12:33:16 PM PST 24
Finished	Jan 07 12:35:21 PM PST 24
Peak memory	218060 kb
Host	smart-36472714-920f-4dde-a497-d59166369cc5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453520314 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2453520314
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1237779114
Short name	T79
Test name
Test status
Simulation time	69251951 ps
CPU time	1.87 seconds
Started	Jan 07 12:33:17 PM PST 24
Finished	Jan 07 12:34:51 PM PST 24
Peak memory	215720 kb
Host	smart-dafce110-d354-4973-b212-be4f865c1963
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237779114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1 237779114
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.80101790
Short name	T365
Test name
Test status
Simulation time	647242745 ps
CPU time	4.05 seconds
Started	Jan 07 12:32:51 PM PST 24
Finished	Jan 07 12:34:25 PM PST 24
Peak memory	215704 kb
Host	smart-360fa422-b71a-458b-b70b-c8a06f6025b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80101790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi _device_same_csr_outstanding.80101790
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3154949356
Short name	T397
Test name
Test status
Simulation time	302342497 ps
CPU time	4.45 seconds
Started	Jan 07 12:33:32 PM PST 24
Finished	Jan 07 12:35:20 PM PST 24
Peak memory	215868 kb
Host	smart-2afedf4e-7ddd-4505-afbe-2990172fb65e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154949356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3 154949356
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.403308106
Short name	T414
Test name
Test status
Simulation time	273954629 ps
CPU time	6.04 seconds
Started	Jan 07 12:33:19 PM PST 24
Finished	Jan 07 12:34:51 PM PST 24
Peak memory	215708 kb
Host	smart-b2dfb254-9841-46be-8001-f5bd7945cfaf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403308106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_ tl_intg_err.403308106
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3191630938
Short name	T69
Test name
Test status
Simulation time	70314658 ps
CPU time	2.68 seconds
Started	Jan 07 12:32:46 PM PST 24
Finished	Jan 07 12:34:12 PM PST 24
Peak memory	218080 kb
Host	smart-b15f3f9d-46c0-4b1b-bd34-fe512d29dfeb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191630938 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3191630938
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2445579385
Short name	T410
Test name
Test status
Simulation time	99377006 ps
CPU time	1.06 seconds
Started	Jan 07 12:33:24 PM PST 24
Finished	Jan 07 12:34:35 PM PST 24
Peak memory	215780 kb
Host	smart-00f1e46b-2def-4280-bbd1-f5e8a84b0d11
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445579385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2 445579385
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2548417866
Short name	T143
Test name
Test status
Simulation time	15331561 ps
CPU time	0.74 seconds
Started	Jan 07 12:33:15 PM PST 24
Finished	Jan 07 12:34:23 PM PST 24
Peak memory	204816 kb
Host	smart-0f86f0ce-e5dd-4896-9363-e6c677600b4d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548417866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2 548417866
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1609443513
Short name	T367
Test name
Test status
Simulation time	319817843 ps
CPU time	3.97 seconds
Started	Jan 07 12:33:01 PM PST 24
Finished	Jan 07 12:34:19 PM PST 24
Peak memory	215652 kb
Host	smart-00e058d1-fcfe-4021-a27f-610c33d65ae4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609443513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s pi_device_same_csr_outstanding.1609443513
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2966872017
Short name	T119
Test name
Test status
Simulation time	770936375 ps
CPU time	5.29 seconds
Started	Jan 07 12:33:12 PM PST 24
Finished	Jan 07 12:34:44 PM PST 24
Peak memory	215920 kb
Host	smart-4d146198-f2c3-44c6-ac36-96475616e606
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966872017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2 966872017
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1895357930
Short name	T134
Test name
Test status
Simulation time	883325563 ps
CPU time	21.05 seconds
Started	Jan 07 12:32:47 PM PST 24
Finished	Jan 07 12:34:30 PM PST 24
Peak memory	216012 kb
Host	smart-4c5d75be-a55e-46c1-ae0f-33d3b472e737
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895357930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.1895357930
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2277139850
Short name	T80
Test name
Test status
Simulation time	23745390 ps
CPU time	1.66 seconds
Started	Jan 07 12:32:54 PM PST 24
Finished	Jan 07 12:34:05 PM PST 24
Peak memory	217376 kb
Host	smart-6980b036-5a99-4385-8b77-4dfccd6d8022
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277139850 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2277139850
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.38028852
Short name	T175
Test name
Test status
Simulation time	763004088 ps
CPU time	1.27 seconds
Started	Jan 07 12:33:45 PM PST 24
Finished	Jan 07 12:34:55 PM PST 24
Peak memory	215652 kb
Host	smart-331ed328-bf2f-47e5-985c-3f8b916d8712
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38028852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.38028852
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.4008807971
Short name	T362
Test name
Test status
Simulation time	34186773 ps
CPU time	0.67 seconds
Started	Jan 07 12:33:23 PM PST 24
Finished	Jan 07 12:35:12 PM PST 24
Peak memory	204800 kb
Host	smart-4330e2c7-43e3-4099-af68-ee3e8000d6d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008807971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4 008807971
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2489882900
Short name	T372
Test name
Test status
Simulation time	681383393 ps
CPU time	3.22 seconds
Started	Jan 07 12:32:36 PM PST 24
Finished	Jan 07 12:34:56 PM PST 24
Peak memory	215688 kb
Host	smart-9a1339c5-af22-4c71-8e39-0eccee2ec7a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489882900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2 489882900
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.168407913
Short name	T136
Test name
Test status
Simulation time	194621621 ps
CPU time	5.61 seconds
Started	Jan 07 12:33:27 PM PST 24
Finished	Jan 07 12:35:05 PM PST 24
Peak memory	215836 kb
Host	smart-38be3d2d-4f7a-43b9-ae56-c7f2d1d6b046
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168407913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_ tl_intg_err.168407913
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.60905727
Short name	T159
Test name
Test status
Simulation time	71039943 ps
CPU time	1.19 seconds
Started	Jan 07 12:33:38 PM PST 24
Finished	Jan 07 12:34:54 PM PST 24
Peak memory	207576 kb
Host	smart-1bd2d3a0-e74f-4563-b1c3-9c7dea3260c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60905727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.60905727
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.2221850604
Short name	T361
Test name
Test status
Simulation time	16773013 ps
CPU time	0.74 seconds
Started	Jan 07 12:33:50 PM PST 24
Finished	Jan 07 12:35:03 PM PST 24
Peak memory	204824 kb
Host	smart-90ee6eee-9b0e-4da8-b421-aaf4df6a917e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221850604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2 221850604
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1254674264
Short name	T174
Test name
Test status
Simulation time	78467800 ps
CPU time	1.87 seconds
Started	Jan 07 12:33:50 PM PST 24
Finished	Jan 07 12:35:04 PM PST 24
Peak memory	215684 kb
Host	smart-e1fc28cc-580a-4b24-97b8-e6581eb773d2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254674264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.1254674264
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3984380067
Short name	T404
Test name
Test status
Simulation time	687160186 ps
CPU time	12.11 seconds
Started	Jan 07 12:33:24 PM PST 24
Finished	Jan 07 12:34:55 PM PST 24
Peak memory	216300 kb
Host	smart-177758f5-d924-40b1-a423-df2095771403
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984380067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.3984380067
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1880102289
Short name	T391
Test name
Test status
Simulation time	95597162 ps
CPU time	1.4 seconds
Started	Jan 07 12:35:55 PM PST 24
Finished	Jan 07 12:37:49 PM PST 24
Peak memory	216904 kb
Host	smart-f5dfb602-1b2d-4dcb-b737-408569a95405
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880102289 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1880102289
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.990698356
Short name	T138
Test name
Test status
Simulation time	191588151 ps
CPU time	1.27 seconds
Started	Jan 07 12:33:53 PM PST 24
Finished	Jan 07 12:35:25 PM PST 24
Peak memory	215724 kb
Host	smart-10032504-53e0-46e0-b629-7b838c51d420
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990698356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.990698356
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.374402991
Short name	T419
Test name
Test status
Simulation time	14772454 ps
CPU time	0.72 seconds
Started	Jan 07 12:33:35 PM PST 24
Finished	Jan 07 12:35:12 PM PST 24
Peak memory	204816 kb
Host	smart-dbee1958-153e-4300-b5f0-7c2dfebf389c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374402991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.374402991
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3702345290
Short name	T388
Test name
Test status
Simulation time	28989661 ps
CPU time	1.68 seconds
Started	Jan 07 12:35:15 PM PST 24
Finished	Jan 07 12:36:39 PM PST 24
Peak memory	215412 kb
Host	smart-1cc23f12-f7eb-4c4e-89ed-e564230bb77e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702345290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.3702345290
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2334229853
Short name	T117
Test name
Test status
Simulation time	4230562679 ps
CPU time	19 seconds
Started	Jan 07 12:33:45 PM PST 24
Finished	Jan 07 12:35:15 PM PST 24
Peak memory	215876 kb
Host	smart-1fdda595-1c9e-4a37-b9bc-9f33a936eb5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334229853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.2334229853
Directory	/workspace/9.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/0.spi_device_abort.1095188156
Short name	T1558
Test name
Test status
Simulation time	44353607 ps
CPU time	0.74 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	206548 kb
Host	smart-ad5a12d5-7890-495d-9e36-a1cc7d1d0171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095188156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_abort.1095188156
Directory	/workspace/0.spi_device_abort/latest

Test location	/workspace/coverage/default/0.spi_device_alert_test.4013200169
Short name	T1011
Test name
Test status
Simulation time	37760986 ps
CPU time	0.72 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:18:26 PM PST 24
Peak memory	206420 kb
Host	smart-2a60e05d-5e46-4772-840c-0707a635523c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013200169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4 013200169
Directory	/workspace/0.spi_device_alert_test/latest

Test location	/workspace/coverage/default/0.spi_device_bit_transfer.4164614529
Short name	T1492
Test name
Test status
Simulation time	125487164 ps
CPU time	2.37 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:21 PM PST 24
Peak memory	216824 kb
Host	smart-eafdd2a3-bae4-430a-a8bb-de3147501617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164614529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_bit_transfer.4164614529
Directory	/workspace/0.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/0.spi_device_byte_transfer.1679634952
Short name	T1367
Test name
Test status
Simulation time	216646821 ps
CPU time	2.77 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:27 PM PST 24
Peak memory	216704 kb
Host	smart-4833547b-385c-4c33-afa1-15fe6d8547f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679634952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_byte_transfer.1679634952
Directory	/workspace/0.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/0.spi_device_cfg_cmd.2786513319
Short name	T1485
Test name
Test status
Simulation time	145908420 ps
CPU time	2.72 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:25 PM PST 24
Peak memory	224952 kb
Host	smart-8aa53e6e-3f8f-49df-9dcc-5d192d8e8191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786513319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2786513319
Directory	/workspace/0.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/0.spi_device_csb_read.2399835494
Short name	T716
Test name
Test status
Simulation time	30297569 ps
CPU time	0.77 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	207484 kb
Host	smart-2aade306-9824-4344-b606-063598a5cafe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399835494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2399835494
Directory	/workspace/0.spi_device_csb_read/latest

Test location	/workspace/coverage/default/0.spi_device_dummy_item_extra_dly.1897919641
Short name	T1223
Test name
Test status
Simulation time	21365199671 ps
CPU time	180.69 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:21:21 PM PST 24
Peak memory	267200 kb
Host	smart-bd496ac1-1be2-4daa-9f00-c6c1df2a8bbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897919641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_dummy_item_extra_dly.1897919641
Directory	/workspace/0.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/0.spi_device_extreme_fifo_size.2345265256
Short name	T962
Test name
Test status
Simulation time	3519444551 ps
CPU time	57.53 seconds
Started	Jan 07 01:18:16 PM PST 24
Finished	Jan 07 01:19:15 PM PST 24
Peak memory	220548 kb
Host	smart-460c1b3d-d99f-4fc3-a841-2811847f3cb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345265256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_extreme_fifo_size.2345265256
Directory	/workspace/0.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/0.spi_device_fifo_full.2262177544
Short name	T599
Test name
Test status
Simulation time	120752408139 ps
CPU time	474.72 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:26:17 PM PST 24
Peak memory	264408 kb
Host	smart-3d1f8ca7-522f-4453-89cc-aaee3900ad67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262177544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_full.2262177544
Directory	/workspace/0.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/0.spi_device_fifo_underflow_overflow.3291983779
Short name	T1567
Test name
Test status
Simulation time	610198046379 ps
CPU time	1401.11 seconds
Started	Jan 07 01:18:21 PM PST 24
Finished	Jan 07 01:41:47 PM PST 24
Peak memory	884816 kb
Host	smart-d2f4cb48-a6a7-49da-b221-0da345c4e74c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291983779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_fifo_underflow_overfl ow.3291983779
Directory	/workspace/0.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/0.spi_device_flash_all.633519540
Short name	T584
Test name
Test status
Simulation time	3585444849 ps
CPU time	42.73 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:19:08 PM PST 24
Peak memory	249852 kb
Host	smart-31494101-1029-47e8-a743-750df7c763c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633519540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.633519540
Directory	/workspace/0.spi_device_flash_all/latest

Test location	/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1608054408
Short name	T307
Test name
Test status
Simulation time	66786946891 ps
CPU time	482.25 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:26:24 PM PST 24
Peak memory	269192 kb
Host	smart-ff416ef6-bda5-4239-bee5-2c96c785e21b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608054408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle .1608054408
Directory	/workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/0.spi_device_flash_mode.1291231816
Short name	T1079
Test name
Test status
Simulation time	17468416416 ps
CPU time	23.85 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:47 PM PST 24
Peak memory	233224 kb
Host	smart-c72d6616-c71c-4a33-9254-b3e3b524a435
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291231816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1291231816
Directory	/workspace/0.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/0.spi_device_intercept.411362263
Short name	T1224
Test name
Test status
Simulation time	3303735941 ps
CPU time	4.47 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	218492 kb
Host	smart-7be69756-942a-4563-bc64-be4f3c68e66d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411362263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.411362263
Directory	/workspace/0.spi_device_intercept/latest

Test location	/workspace/coverage/default/0.spi_device_intr.2439838094
Short name	T972
Test name
Test status
Simulation time	29348183685 ps
CPU time	41.23 seconds
Started	Jan 07 01:18:21 PM PST 24
Finished	Jan 07 01:19:07 PM PST 24
Peak memory	236208 kb
Host	smart-5075574c-936d-4d05-8a95-0adf00ab4787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439838094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intr.2439838094
Directory	/workspace/0.spi_device_intr/latest

Test location	/workspace/coverage/default/0.spi_device_mailbox.3533037600
Short name	T1585
Test name
Test status
Simulation time	2680746982 ps
CPU time	5.87 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:24 PM PST 24
Peak memory	234300 kb
Host	smart-043c6894-638e-4697-8ced-53213106ed05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533037600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3533037600
Directory	/workspace/0.spi_device_mailbox/latest

Test location	/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3812481289
Short name	T1375
Test name
Test status
Simulation time	3629777329 ps
CPU time	14.11 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:33 PM PST 24
Peak memory	241480 kb
Host	smart-cd454b54-3e6c-455c-9398-59b1580638e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812481289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .3812481289
Directory	/workspace/0.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/0.spi_device_pass_cmd_filtering.138569676
Short name	T835
Test name
Test status
Simulation time	4420892773 ps
CPU time	20.96 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:40 PM PST 24
Peak memory	249712 kb
Host	smart-697eb3f8-1a03-4f27-b283-461b1a2ebf08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138569676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.138569676
Directory	/workspace/0.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/0.spi_device_perf.2744169799
Short name	T964
Test name
Test status
Simulation time	19440787192 ps
CPU time	295.17 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	275392 kb
Host	smart-ebaac01f-fb70-4e97-9f8b-dc06928c579d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744169799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_perf.2744169799
Directory	/workspace/0.spi_device_perf/latest

Test location	/workspace/coverage/default/0.spi_device_ram_cfg.1298385124
Short name	T1737
Test name
Test status
Simulation time	26749163 ps
CPU time	0.76 seconds
Started	Jan 07 01:18:16 PM PST 24
Finished	Jan 07 01:18:18 PM PST 24
Peak memory	216668 kb
Host	smart-a0acad65-e2f4-4788-b3d7-5bfb4ecad367
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298385124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1298385124
Directory	/workspace/0.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/0.spi_device_read_buffer_direct.1719502813
Short name	T1636
Test name
Test status
Simulation time	634296347 ps
CPU time	4.54 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:29 PM PST 24
Peak memory	234276 kb
Host	smart-546fe548-b90c-40f8-a35a-51d9ad8a6766
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1719502813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire ct.1719502813
Directory	/workspace/0.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/0.spi_device_rx_async_fifo_reset.426414957
Short name	T1611
Test name
Test status
Simulation time	86921069 ps
CPU time	0.89 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:21 PM PST 24
Peak memory	208420 kb
Host	smart-4cbc3b50-0f97-44ac-a316-ab8da82522e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426414957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_async_fifo_reset.426414957
Directory	/workspace/0.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/0.spi_device_rx_timeout.3651017682
Short name	T1340
Test name
Test status
Simulation time	2597296207 ps
CPU time	5.63 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:27 PM PST 24
Peak memory	216748 kb
Host	smart-17ddcc97-1d4f-4f4d-a435-949a5de29b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651017682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_rx_timeout.3651017682
Directory	/workspace/0.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/0.spi_device_sec_cm.3685431553
Short name	T89
Test name
Test status
Simulation time	103175416 ps
CPU time	1.17 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:26 PM PST 24
Peak memory	239140 kb
Host	smart-42a637e9-130b-4d40-8e1d-c7ccd734624d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685431553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3685431553
Directory	/workspace/0.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/0.spi_device_smoke.1461594826
Short name	T723
Test name
Test status
Simulation time	127815844 ps
CPU time	1.08 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:20 PM PST 24
Peak memory	216476 kb
Host	smart-4d94fddf-fd1f-4611-a6fe-7409f9d03782
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461594826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_smoke.1461594826
Directory	/workspace/0.spi_device_smoke/latest

Test location	/workspace/coverage/default/0.spi_device_stress_all.3971585357
Short name	T1100
Test name
Test status
Simulation time	152468424235 ps
CPU time	4624.29 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 02:35:30 PM PST 24
Peak memory	300976 kb
Host	smart-2fba5a28-6af7-40bb-8976-bdc90f998c3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971585357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres s_all.3971585357
Directory	/workspace/0.spi_device_stress_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_all.2376452620
Short name	T883
Test name
Test status
Simulation time	222858161 ps
CPU time	1.84 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:24 PM PST 24
Peak memory	217084 kb
Host	smart-b297c8e5-1881-4e4a-b73e-48c1e325f464
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376452620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2376452620
Directory	/workspace/0.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2458426305
Short name	T1090
Test name
Test status
Simulation time	6220561381 ps
CPU time	11.52 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:34 PM PST 24
Peak memory	216700 kb
Host	smart-2f63abdd-1cd2-425c-9d74-a7d03b73e1ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458426305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2458426305
Directory	/workspace/0.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_rw.226351267
Short name	T1692
Test name
Test status
Simulation time	320245304 ps
CPU time	2.41 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:18:22 PM PST 24
Peak memory	216884 kb
Host	smart-4f5ca073-b25a-4d08-8ed4-5f36bc7d3346
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226351267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.226351267
Directory	/workspace/0.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_sts_read.1467794570
Short name	T926
Test name
Test status
Simulation time	65167742 ps
CPU time	0.8 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:18:26 PM PST 24
Peak memory	206704 kb
Host	smart-7104e083-cb35-4668-8a80-8eecafea1218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467794570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1467794570
Directory	/workspace/0.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/0.spi_device_tx_async_fifo_reset.3407016757
Short name	T1058
Test name
Test status
Simulation time	25091156 ps
CPU time	0.78 seconds
Started	Jan 07 01:18:16 PM PST 24
Finished	Jan 07 01:18:17 PM PST 24
Peak memory	208420 kb
Host	smart-aaa724f2-b5e3-4620-878b-64b32e4eb3f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407016757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tx_async_fifo_reset.3407016757
Directory	/workspace/0.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/0.spi_device_txrx.700258587
Short name	T537
Test name
Test status
Simulation time	130995642003 ps
CPU time	245.44 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:22:24 PM PST 24
Peak memory	277748 kb
Host	smart-ce101d21-f1c7-44d9-899e-39e73b5e6119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700258587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_txrx.700258587
Directory	/workspace/0.spi_device_txrx/latest

Test location	/workspace/coverage/default/0.spi_device_upload.2019636577
Short name	T1387
Test name
Test status
Simulation time	122861297315 ps
CPU time	38.75 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:19:00 PM PST 24
Peak memory	249584 kb
Host	smart-615f571e-aa02-40a4-8e3c-3a8ae5e1b8b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019636577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2019636577
Directory	/workspace/0.spi_device_upload/latest

Test location	/workspace/coverage/default/1.spi_device_abort.1693228381
Short name	T1345
Test name
Test status
Simulation time	182048742 ps
CPU time	0.72 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:18:39 PM PST 24
Peak memory	206596 kb
Host	smart-9cdb688e-02a7-4077-8938-1f1f14b70750
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693228381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_abort.1693228381
Directory	/workspace/1.spi_device_abort/latest

Test location	/workspace/coverage/default/1.spi_device_alert_test.3523683610
Short name	T1267
Test name
Test status
Simulation time	22457659 ps
CPU time	0.71 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:18:37 PM PST 24
Peak memory	206468 kb
Host	smart-a1539e15-8077-4edf-8b0d-434bcce01341
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523683610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3 523683610
Directory	/workspace/1.spi_device_alert_test/latest

Test location	/workspace/coverage/default/1.spi_device_bit_transfer.2388961079
Short name	T948
Test name
Test status
Simulation time	1210714098 ps
CPU time	2.67 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:18:35 PM PST 24
Peak memory	216844 kb
Host	smart-a05f5056-d801-4894-885f-4b78eb86e70c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388961079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_bit_transfer.2388961079
Directory	/workspace/1.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/1.spi_device_byte_transfer.2172968880
Short name	T1250
Test name
Test status
Simulation time	342843983 ps
CPU time	2.75 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:25 PM PST 24
Peak memory	216784 kb
Host	smart-cc425637-274b-4f8a-bcbd-5d2004dc3213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172968880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_byte_transfer.2172968880
Directory	/workspace/1.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/1.spi_device_cfg_cmd.1407799693
Short name	T549
Test name
Test status
Simulation time	189233377 ps
CPU time	3.57 seconds
Started	Jan 07 01:18:28 PM PST 24
Finished	Jan 07 01:18:34 PM PST 24
Peak memory	238588 kb
Host	smart-3c8fa234-1619-45ec-8b49-c234478d2de7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407799693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1407799693
Directory	/workspace/1.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/1.spi_device_csb_read.2673986551
Short name	T1526
Test name
Test status
Simulation time	112254664 ps
CPU time	0.76 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	206548 kb
Host	smart-8c12e666-2b01-47d9-aa3a-d6b994b11072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673986551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2673986551
Directory	/workspace/1.spi_device_csb_read/latest

Test location	/workspace/coverage/default/1.spi_device_dummy_item_extra_dly.1592668291
Short name	T822
Test name
Test status
Simulation time	207037564819 ps
CPU time	364.16 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:24:27 PM PST 24
Peak memory	282440 kb
Host	smart-73c508c9-2d9c-4a67-ac83-77aa04430719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592668291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_dummy_item_extra_dly.1592668291
Directory	/workspace/1.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/1.spi_device_extreme_fifo_size.542986592
Short name	T176
Test name
Test status
Simulation time	61941833915 ps
CPU time	2485.19 seconds
Started	Jan 07 01:18:17 PM PST 24
Finished	Jan 07 01:59:44 PM PST 24
Peak memory	220052 kb
Host	smart-d7f3faae-9bd5-4bd7-8c22-230841f91ca9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542986592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_extreme_fifo_size.542986592
Directory	/workspace/1.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/1.spi_device_fifo_full.3078350611
Short name	T877
Test name
Test status
Simulation time	525698888617 ps
CPU time	3189.92 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 02:11:35 PM PST 24
Peak memory	274012 kb
Host	smart-06587c7d-5b5d-4687-a1bb-b92801599f8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078350611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_full.3078350611
Directory	/workspace/1.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/1.spi_device_fifo_underflow_overflow.437535612
Short name	T50
Test name
Test status
Simulation time	216900170721 ps
CPU time	603.46 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:28:29 PM PST 24
Peak memory	609836 kb
Host	smart-33b38b46-1689-426e-a730-8a8d12e9d153
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437535612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_fifo_underflow_overflo w.437535612
Directory	/workspace/1.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/1.spi_device_flash_all.3501688725
Short name	T257
Test name
Test status
Simulation time	21484438378 ps
CPU time	114.19 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:20:27 PM PST 24
Peak memory	250836 kb
Host	smart-d274c818-d502-439a-a31a-4cfd89262c51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501688725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3501688725
Directory	/workspace/1.spi_device_flash_all/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm.2248927606
Short name	T1392
Test name
Test status
Simulation time	5950216203 ps
CPU time	122 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	262312 kb
Host	smart-f2eb96eb-e25a-4260-a617-566562ca7c99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248927606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2248927606
Directory	/workspace/1.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.196356697
Short name	T339
Test name
Test status
Simulation time	566501058664 ps
CPU time	449.9 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:26:09 PM PST 24
Peak memory	255704 kb
Host	smart-d403d631-0ec4-41e1-b09e-743617195475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196356697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle. 196356697
Directory	/workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/1.spi_device_flash_mode.2820076970
Short name	T165
Test name
Test status
Simulation time	6623811967 ps
CPU time	19.95 seconds
Started	Jan 07 01:18:29 PM PST 24
Finished	Jan 07 01:18:51 PM PST 24
Peak memory	249524 kb
Host	smart-051fc1dd-9f3f-4a9d-b7f8-226cc981424a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820076970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2820076970
Directory	/workspace/1.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/1.spi_device_intercept.2593283165
Short name	T1486
Test name
Test status
Simulation time	1221754243 ps
CPU time	3.99 seconds
Started	Jan 07 01:18:28 PM PST 24
Finished	Jan 07 01:18:35 PM PST 24
Peak memory	239116 kb
Host	smart-99726c0e-ec4e-43e5-8729-7c4434fff67e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593283165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2593283165
Directory	/workspace/1.spi_device_intercept/latest

Test location	/workspace/coverage/default/1.spi_device_intr.4078157318
Short name	T802
Test name
Test status
Simulation time	141531443905 ps
CPU time	47.33 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:19:12 PM PST 24
Peak memory	221556 kb
Host	smart-d551b6cf-a8b0-4fca-9ca4-bb5db8643767
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078157318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intr.4078157318
Directory	/workspace/1.spi_device_intr/latest

Test location	/workspace/coverage/default/1.spi_device_mailbox.4180074976
Short name	T1041
Test name
Test status
Simulation time	4137042348 ps
CPU time	17.94 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:57 PM PST 24
Peak memory	249004 kb
Host	smart-3ae74d25-0c96-44c7-912d-09a33c619304
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180074976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4180074976
Directory	/workspace/1.spi_device_mailbox/latest

Test location	/workspace/coverage/default/1.spi_device_mem_parity.2269947748
Short name	T44
Test name
Test status
Simulation time	140565885 ps
CPU time	0.99 seconds
Started	Jan 07 01:18:18 PM PST 24
Finished	Jan 07 01:18:23 PM PST 24
Peak memory	218876 kb
Host	smart-65f9e825-f1f0-4636-bea0-75c65b076376
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269947748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.spi_device_mem_parity.2269947748
Directory	/workspace/1.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2896919282
Short name	T294
Test name
Test status
Simulation time	1568389835 ps
CPU time	6.89 seconds
Started	Jan 07 01:18:31 PM PST 24
Finished	Jan 07 01:18:40 PM PST 24
Peak memory	239228 kb
Host	smart-c708e7d2-0eac-46e1-ad5a-47b8dd7027d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896919282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap .2896919282
Directory	/workspace/1.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/1.spi_device_pass_cmd_filtering.3244322015
Short name	T1529
Test name
Test status
Simulation time	2200016751 ps
CPU time	7.3 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:47 PM PST 24
Peak memory	220388 kb
Host	smart-08adeb39-28e0-4c36-8f43-69cd2f82aae8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244322015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3244322015
Directory	/workspace/1.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/1.spi_device_perf.3352358564
Short name	T1081
Test name
Test status
Simulation time	459678188107 ps
CPU time	2736.49 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 02:04:02 PM PST 24
Peak memory	298992 kb
Host	smart-1ba525eb-cf73-4e96-9009-f42531209f8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352358564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_perf.3352358564
Directory	/workspace/1.spi_device_perf/latest

Test location	/workspace/coverage/default/1.spi_device_read_buffer_direct.3622951197
Short name	T817
Test name
Test status
Simulation time	156974617 ps
CPU time	3.71 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:18:48 PM PST 24
Peak memory	234156 kb
Host	smart-d035b828-f9c4-402a-b85f-1e97f2f032fb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3622951197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire ct.3622951197
Directory	/workspace/1.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/1.spi_device_rx_async_fifo_reset.3718780631
Short name	T854
Test name
Test status
Simulation time	76394965 ps
CPU time	0.82 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:18:45 PM PST 24
Peak memory	208516 kb
Host	smart-f595684d-61b0-488b-b5af-09e5d6208b8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718780631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_async_fifo_reset.3718780631
Directory	/workspace/1.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/1.spi_device_rx_timeout.1595641445
Short name	T1403
Test name
Test status
Simulation time	3335510196 ps
CPU time	5.35 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:18:30 PM PST 24
Peak memory	216964 kb
Host	smart-3f60e538-f2f6-41ed-af49-c4bd99155944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595641445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_rx_timeout.1595641445
Directory	/workspace/1.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/1.spi_device_smoke.2701117271
Short name	T523
Test name
Test status
Simulation time	30405101 ps
CPU time	0.95 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:18:26 PM PST 24
Peak memory	207880 kb
Host	smart-f3301e66-fd68-485f-9aa0-c44fb573be88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701117271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_smoke.2701117271
Directory	/workspace/1.spi_device_smoke/latest

Test location	/workspace/coverage/default/1.spi_device_stress_all.3162330761
Short name	T55
Test name
Test status
Simulation time	48143508879 ps
CPU time	571.33 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:28:10 PM PST 24
Peak memory	411776 kb
Host	smart-74cb8f7b-abab-4e30-b6ff-0779e1675975
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162330761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres s_all.3162330761
Directory	/workspace/1.spi_device_stress_all/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_all.1034172312
Short name	T1461
Test name
Test status
Simulation time	5365211627 ps
CPU time	56.23 seconds
Started	Jan 07 01:18:19 PM PST 24
Finished	Jan 07 01:19:19 PM PST 24
Peak memory	217188 kb
Host	smart-4f9316c0-2fcf-4326-82e3-14f99485e863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034172312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1034172312
Directory	/workspace/1.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.466320121
Short name	T1435
Test name
Test status
Simulation time	576998102 ps
CPU time	5.12 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:18:30 PM PST 24
Peak memory	216772 kb
Host	smart-092a05f8-1b34-4923-9f7e-31196c877264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466320121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.466320121
Directory	/workspace/1.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_rw.3669999131
Short name	T805
Test name
Test status
Simulation time	270021673 ps
CPU time	1.66 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:18:34 PM PST 24
Peak memory	216876 kb
Host	smart-396abc34-f397-4c7c-abd1-649d25897f5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669999131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3669999131
Directory	/workspace/1.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_sts_read.2033347224
Short name	T1288
Test name
Test status
Simulation time	56332969 ps
CPU time	0.92 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:18:47 PM PST 24
Peak memory	206944 kb
Host	smart-612fb489-48c2-455f-8d75-7bfa89a38e81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033347224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2033347224
Directory	/workspace/1.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/1.spi_device_tx_async_fifo_reset.3863957479
Short name	T934
Test name
Test status
Simulation time	54608555 ps
CPU time	0.74 seconds
Started	Jan 07 01:18:28 PM PST 24
Finished	Jan 07 01:18:31 PM PST 24
Peak memory	208368 kb
Host	smart-8896fad3-f5fe-4964-a1c9-586f2e4e387a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863957479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tx_async_fifo_reset.3863957479
Directory	/workspace/1.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/1.spi_device_txrx.2797619831
Short name	T1452
Test name
Test status
Simulation time	73096557341 ps
CPU time	199.81 seconds
Started	Jan 07 01:18:20 PM PST 24
Finished	Jan 07 01:21:45 PM PST 24
Peak memory	304772 kb
Host	smart-ed8125a1-70e6-4969-8365-bafd5080b5be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797619831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_txrx.2797619831
Directory	/workspace/1.spi_device_txrx/latest

Test location	/workspace/coverage/default/1.spi_device_upload.2760565821
Short name	T1038
Test name
Test status
Simulation time	2551025342 ps
CPU time	8.24 seconds
Started	Jan 07 01:18:28 PM PST 24
Finished	Jan 07 01:18:39 PM PST 24
Peak memory	230984 kb
Host	smart-0b8787e9-4512-490c-b267-eebe1fa41396
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760565821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2760565821
Directory	/workspace/1.spi_device_upload/latest

Test location	/workspace/coverage/default/10.spi_device_abort.36259411
Short name	T1632
Test name
Test status
Simulation time	51331554 ps
CPU time	0.75 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:02 PM PST 24
Peak memory	206608 kb
Host	smart-121c8609-2792-473d-8321-da2bbb2450a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36259411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_abort.36259411
Directory	/workspace/10.spi_device_abort/latest

Test location	/workspace/coverage/default/10.spi_device_alert_test.4066068616
Short name	T1247
Test name
Test status
Simulation time	12770283 ps
CPU time	0.7 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:05 PM PST 24
Peak memory	206340 kb
Host	smart-4abcbca1-b692-436b-b3e6-ed6def86d8f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066068616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test. 4066068616
Directory	/workspace/10.spi_device_alert_test/latest

Test location	/workspace/coverage/default/10.spi_device_bit_transfer.3593543920
Short name	T1331
Test name
Test status
Simulation time	89850773 ps
CPU time	2.3 seconds
Started	Jan 07 01:20:02 PM PST 24
Finished	Jan 07 01:20:15 PM PST 24
Peak memory	216880 kb
Host	smart-3b96682a-5491-4895-aec2-c88b249bc0fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3593543920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_bit_transfer.3593543920
Directory	/workspace/10.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/10.spi_device_byte_transfer.1412874449
Short name	T878
Test name
Test status
Simulation time	61125472 ps
CPU time	2.36 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:20:00 PM PST 24
Peak memory	216900 kb
Host	smart-d0f258a4-5080-49f0-9425-d564dce2d4ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412874449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_byte_transfer.1412874449
Directory	/workspace/10.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/10.spi_device_cfg_cmd.256589470
Short name	T1186
Test name
Test status
Simulation time	181376355 ps
CPU time	3.04 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:10 PM PST 24
Peak memory	218872 kb
Host	smart-055fc1b1-7990-4a1e-b3d3-4a27fcdbba67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256589470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.256589470
Directory	/workspace/10.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/10.spi_device_csb_read.3606736024
Short name	T1654
Test name
Test status
Simulation time	159088120 ps
CPU time	0.78 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:20:08 PM PST 24
Peak memory	207544 kb
Host	smart-254de861-9d12-4176-971c-bdbf5e896ffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606736024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3606736024
Directory	/workspace/10.spi_device_csb_read/latest

Test location	/workspace/coverage/default/10.spi_device_dummy_item_extra_dly.3560934622
Short name	T1075
Test name
Test status
Simulation time	48745757034 ps
CPU time	276.18 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:24:19 PM PST 24
Peak memory	282500 kb
Host	smart-62294209-a5d9-4061-ae73-1830a25c0bba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560934622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_dummy_item_extra_dly.3560934622
Directory	/workspace/10.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/10.spi_device_extreme_fifo_size.142823627
Short name	T263
Test name
Test status
Simulation time	80110494917 ps
CPU time	1123.6 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:38:39 PM PST 24
Peak memory	221116 kb
Host	smart-1c795e8a-e044-4a6b-915d-c70826078bed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142823627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_extreme_fifo_size.142823627
Directory	/workspace/10.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/10.spi_device_fifo_full.341787048
Short name	T1277
Test name
Test status
Simulation time	464104045871 ps
CPU time	745.48 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:32:19 PM PST 24
Peak memory	273504 kb
Host	smart-2dd504c7-e0a8-4c72-9645-34b27ef0538f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341787048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_fifo_full.341787048
Directory	/workspace/10.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/10.spi_device_flash_all.4247364169
Short name	T191
Test name
Test status
Simulation time	53179056203 ps
CPU time	182.06 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	257972 kb
Host	smart-3044bab4-ed2e-490a-8f1f-b1fac80b0c16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247364169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4247364169
Directory	/workspace/10.spi_device_flash_all/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm.881532491
Short name	T876
Test name
Test status
Simulation time	170541669967 ps
CPU time	230.02 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	267420 kb
Host	smart-e8c7e199-7f5a-42c2-a8b3-dbaa4ef3dc6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881532491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.881532491
Directory	/workspace/10.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3905453276
Short name	T1355
Test name
Test status
Simulation time	8104481982 ps
CPU time	56.24 seconds
Started	Jan 07 01:19:48 PM PST 24
Finished	Jan 07 01:20:54 PM PST 24
Peak memory	249784 kb
Host	smart-a08f0e5b-6433-4a25-abe6-85f6bb3e915e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905453276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl e.3905453276
Directory	/workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/10.spi_device_flash_mode.680381820
Short name	T1534
Test name
Test status
Simulation time	6267006462 ps
CPU time	19.74 seconds
Started	Jan 07 01:19:58 PM PST 24
Finished	Jan 07 01:20:30 PM PST 24
Peak memory	251604 kb
Host	smart-cdf9a463-9722-410a-907f-d94749134792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680381820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.680381820
Directory	/workspace/10.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/10.spi_device_intercept.3233944531
Short name	T1319
Test name
Test status
Simulation time	1925739559 ps
CPU time	8.12 seconds
Started	Jan 07 01:19:53 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	240156 kb
Host	smart-9a874559-947a-45e3-bdd1-b74536c53980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233944531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3233944531
Directory	/workspace/10.spi_device_intercept/latest

Test location	/workspace/coverage/default/10.spi_device_intr.1433606394
Short name	T828
Test name
Test status
Simulation time	59485329395 ps
CPU time	56.92 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	225196 kb
Host	smart-66a522b2-2948-4c56-aa91-b60cc267a41b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433606394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intr.1433606394
Directory	/workspace/10.spi_device_intr/latest

Test location	/workspace/coverage/default/10.spi_device_mailbox.2293706488
Short name	T208
Test name
Test status
Simulation time	32232668805 ps
CPU time	47.51 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	236248 kb
Host	smart-b9cf3fd8-4148-4b74-947d-128ab73f7dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293706488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2293706488
Directory	/workspace/10.spi_device_mailbox/latest

Test location	/workspace/coverage/default/10.spi_device_mem_parity.1117917988
Short name	T43
Test name
Test status
Simulation time	111560991 ps
CPU time	1.05 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:01 PM PST 24
Peak memory	217824 kb
Host	smart-3fa15b51-1566-4018-8ebe-564caf68084a
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117917988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.spi_device_mem_parity.1117917988
Directory	/workspace/10.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4235575067
Short name	T1220
Test name
Test status
Simulation time	3697058345 ps
CPU time	4.78 seconds
Started	Jan 07 01:19:52 PM PST 24
Finished	Jan 07 01:20:07 PM PST 24
Peak memory	241496 kb
Host	smart-73e8e949-46c0-4d79-bcc1-f74d9bb398a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235575067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa p.4235575067
Directory	/workspace/10.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/10.spi_device_pass_cmd_filtering.1283103583
Short name	T1036
Test name
Test status
Simulation time	31799320968 ps
CPU time	26.88 seconds
Started	Jan 07 01:19:45 PM PST 24
Finished	Jan 07 01:20:24 PM PST 24
Peak memory	240808 kb
Host	smart-7d1d96eb-f8a0-47fd-9ece-ca7d4bb9dbad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283103583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1283103583
Directory	/workspace/10.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/10.spi_device_perf.981207768
Short name	T798
Test name
Test status
Simulation time	14202604858 ps
CPU time	904.41 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:34:58 PM PST 24
Peak memory	257396 kb
Host	smart-04cdf302-986f-42d6-aeb7-e46234e176ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981207768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_perf.981207768
Directory	/workspace/10.spi_device_perf/latest

Test location	/workspace/coverage/default/10.spi_device_ram_cfg.1443978069
Short name	T674
Test name
Test status
Simulation time	18745216 ps
CPU time	0.73 seconds
Started	Jan 07 01:19:51 PM PST 24
Finished	Jan 07 01:20:02 PM PST 24
Peak memory	216752 kb
Host	smart-006785e0-a056-4c6b-8330-57d323071010
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443978069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1443978069
Directory	/workspace/10.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/10.spi_device_read_buffer_direct.67209900
Short name	T1033
Test name
Test status
Simulation time	2056785496 ps
CPU time	4.97 seconds
Started	Jan 07 01:19:56 PM PST 24
Finished	Jan 07 01:20:14 PM PST 24
Peak memory	220108 kb
Host	smart-492ac2f2-72d5-4b2b-9ea1-64ba47c3722c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=67209900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc t.67209900
Directory	/workspace/10.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/10.spi_device_rx_async_fifo_reset.2286397023
Short name	T1128
Test name
Test status
Simulation time	27772522 ps
CPU time	0.89 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:06 PM PST 24
Peak memory	208320 kb
Host	smart-9a9f5b55-c203-48a7-9860-8af527ee585a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286397023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_async_fifo_reset.2286397023
Directory	/workspace/10.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/10.spi_device_rx_timeout.452147696
Short name	T920
Test name
Test status
Simulation time	545365881 ps
CPU time	5.9 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:05 PM PST 24
Peak memory	216868 kb
Host	smart-d420ba66-0c67-4b57-8f8a-b68dcbca0f41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=452147696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_rx_timeout.452147696
Directory	/workspace/10.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/10.spi_device_smoke.1124600221
Short name	T550
Test name
Test status
Simulation time	238633247 ps
CPU time	1.2 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:43 PM PST 24
Peak memory	216804 kb
Host	smart-12c5ba4a-a031-48a1-bbfe-1aff3deede2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124600221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_smoke.1124600221
Directory	/workspace/10.spi_device_smoke/latest

Test location	/workspace/coverage/default/10.spi_device_stress_all.2285866706
Short name	T1228
Test name
Test status
Simulation time	69598807479 ps
CPU time	870.92 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:34:41 PM PST 24
Peak memory	303796 kb
Host	smart-199b7141-0951-4232-88b4-2fd5455f2756
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285866706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre ss_all.2285866706
Directory	/workspace/10.spi_device_stress_all/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_all.696451364
Short name	T335
Test name
Test status
Simulation time	7274086674 ps
CPU time	14.8 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:20:22 PM PST 24
Peak memory	216852 kb
Host	smart-53683ba0-5150-4886-89eb-b3993c55d033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696451364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.696451364
Directory	/workspace/10.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2809383484
Short name	T1458
Test name
Test status
Simulation time	4012777745 ps
CPU time	14.61 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:20:25 PM PST 24
Peak memory	217912 kb
Host	smart-d4431fd9-fe56-477e-a56a-dc3b2be154b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809383484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2809383484
Directory	/workspace/10.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_rw.1125353101
Short name	T557
Test name
Test status
Simulation time	30236617 ps
CPU time	0.95 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:00 PM PST 24
Peak memory	207284 kb
Host	smart-6a5e97bc-2311-4861-921f-4b704bb4f3af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125353101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1125353101
Directory	/workspace/10.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_sts_read.2846840603
Short name	T653
Test name
Test status
Simulation time	96514132 ps
CPU time	0.87 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:01 PM PST 24
Peak memory	206904 kb
Host	smart-2c9708cb-fe0a-4a6c-b404-ff7dec6b6712
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846840603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2846840603
Directory	/workspace/10.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/10.spi_device_tx_async_fifo_reset.3103249258
Short name	T619
Test name
Test status
Simulation time	29787060 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	208288 kb
Host	smart-d4f42742-38e2-457d-acf6-6c06c5dec5fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103249258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tx_async_fifo_reset.3103249258
Directory	/workspace/10.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/10.spi_device_txrx.1696507633
Short name	T1056
Test name
Test status
Simulation time	295705145968 ps
CPU time	290.32 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:24:40 PM PST 24
Peak memory	277896 kb
Host	smart-c63bd783-16c8-4f86-8bfe-eb26f5e9b148
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696507633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_txrx.1696507633
Directory	/workspace/10.spi_device_txrx/latest

Test location	/workspace/coverage/default/10.spi_device_upload.2981079238
Short name	T1702
Test name
Test status
Simulation time	293388473 ps
CPU time	2.63 seconds
Started	Jan 07 01:20:02 PM PST 24
Finished	Jan 07 01:20:15 PM PST 24
Peak memory	217192 kb
Host	smart-b00f73a5-04fb-409e-b34a-e58e02ebb2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981079238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2981079238
Directory	/workspace/10.spi_device_upload/latest

Test location	/workspace/coverage/default/11.spi_device_abort.2495036080
Short name	T719
Test name
Test status
Simulation time	47582253 ps
CPU time	0.78 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	206648 kb
Host	smart-e615d39f-0c29-467e-a3de-a22a62960a6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495036080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_abort.2495036080
Directory	/workspace/11.spi_device_abort/latest

Test location	/workspace/coverage/default/11.spi_device_alert_test.770874131
Short name	T1306
Test name
Test status
Simulation time	18633680 ps
CPU time	0.69 seconds
Started	Jan 07 01:20:00 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	206508 kb
Host	smart-6b24c936-2fba-42e2-884b-1f2fa67905ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770874131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.770874131
Directory	/workspace/11.spi_device_alert_test/latest

Test location	/workspace/coverage/default/11.spi_device_bit_transfer.1991204657
Short name	T752
Test name
Test status
Simulation time	251649201 ps
CPU time	2.75 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:20:10 PM PST 24
Peak memory	216896 kb
Host	smart-b9e40dd1-ae84-4b53-b8c9-85283655b891
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991204657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_bit_transfer.1991204657
Directory	/workspace/11.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/11.spi_device_byte_transfer.977468193
Short name	T1559
Test name
Test status
Simulation time	622621824 ps
CPU time	3.62 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:20:13 PM PST 24
Peak memory	216800 kb
Host	smart-d62d5953-d0a1-4578-bfb6-6fcff8c70b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977468193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_byte_transfer.977468193
Directory	/workspace/11.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/11.spi_device_cfg_cmd.2241747055
Short name	T1454
Test name
Test status
Simulation time	1646739071 ps
CPU time	7.99 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:19 PM PST 24
Peak memory	220524 kb
Host	smart-ccbacbb3-50fa-4f05-9851-3f67395a3d6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241747055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2241747055
Directory	/workspace/11.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/11.spi_device_csb_read.3574589493
Short name	T929
Test name
Test status
Simulation time	63062506 ps
CPU time	0.77 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:05 PM PST 24
Peak memory	206412 kb
Host	smart-b4626f70-9183-4eb5-88bb-eff252e84376
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574589493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3574589493
Directory	/workspace/11.spi_device_csb_read/latest

Test location	/workspace/coverage/default/11.spi_device_dummy_item_extra_dly.1812056411
Short name	T1294
Test name
Test status
Simulation time	439982139611 ps
CPU time	211.14 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:23:32 PM PST 24
Peak memory	257832 kb
Host	smart-3cb69a2f-e642-4d26-a22d-45ca417cae85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812056411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_dummy_item_extra_dly.1812056411
Directory	/workspace/11.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/11.spi_device_extreme_fifo_size.3376458988
Short name	T260
Test name
Test status
Simulation time	64649901376 ps
CPU time	1162.53 seconds
Started	Jan 07 01:20:00 PM PST 24
Finished	Jan 07 01:39:34 PM PST 24
Peak memory	225204 kb
Host	smart-bacfbabe-a457-4681-ac8d-7ab518a65c37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376458988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_extreme_fifo_size.3376458988
Directory	/workspace/11.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/11.spi_device_fifo_full.318996269
Short name	T1446
Test name
Test status
Simulation time	91017413583 ps
CPU time	379.68 seconds
Started	Jan 07 01:19:56 PM PST 24
Finished	Jan 07 01:26:29 PM PST 24
Peak memory	287500 kb
Host	smart-841fa8aa-d94f-4bc6-bd7c-b96ee7448663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318996269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_full.318996269
Directory	/workspace/11.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/11.spi_device_fifo_underflow_overflow.1048860004
Short name	T1295
Test name
Test status
Simulation time	135471881325 ps
CPU time	565.52 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:29:36 PM PST 24
Peak memory	469848 kb
Host	smart-f52513af-d47c-4e22-841e-b693f566cd12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048860004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_fifo_underflow_overf low.1048860004
Directory	/workspace/11.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm.2513963028
Short name	T1018
Test name
Test status
Simulation time	67151275070 ps
CPU time	258.56 seconds
Started	Jan 07 01:20:07 PM PST 24
Finished	Jan 07 01:24:35 PM PST 24
Peak memory	266640 kb
Host	smart-12702856-aa98-4701-b299-bb9425a40187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513963028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2513963028
Directory	/workspace/11.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.865456105
Short name	T1051
Test name
Test status
Simulation time	75685345797 ps
CPU time	336.18 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:25:51 PM PST 24
Peak memory	267064 kb
Host	smart-c6ab6ef4-475a-48e1-8f32-d9c585a46fa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865456105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle .865456105
Directory	/workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/11.spi_device_flash_mode.2041009344
Short name	T164
Test name
Test status
Simulation time	5043242523 ps
CPU time	14.83 seconds
Started	Jan 07 01:20:05 PM PST 24
Finished	Jan 07 01:20:31 PM PST 24
Peak memory	249144 kb
Host	smart-82d046a6-69d8-4cab-add9-d623b43bd950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041009344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2041009344
Directory	/workspace/11.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/11.spi_device_intercept.2490818397
Short name	T739
Test name
Test status
Simulation time	1090181834 ps
CPU time	6.03 seconds
Started	Jan 07 01:20:03 PM PST 24
Finished	Jan 07 01:20:20 PM PST 24
Peak memory	218960 kb
Host	smart-0c2dd112-9d90-4f21-b195-bf9092bbd049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490818397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2490818397
Directory	/workspace/11.spi_device_intercept/latest

Test location	/workspace/coverage/default/11.spi_device_intr.3866700571
Short name	T456
Test name
Test status
Simulation time	17021142214 ps
CPU time	24.83 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:24 PM PST 24
Peak memory	222988 kb
Host	smart-c8415d0a-b8ee-4fab-b92f-da2826e29f09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866700571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intr.3866700571
Directory	/workspace/11.spi_device_intr/latest

Test location	/workspace/coverage/default/11.spi_device_mailbox.1707950947
Short name	T1468
Test name
Test status
Simulation time	4489981590 ps
CPU time	16.13 seconds
Started	Jan 07 01:20:00 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	225068 kb
Host	smart-bd520381-baa2-4e78-8552-deb89aeadccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707950947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1707950947
Directory	/workspace/11.spi_device_mailbox/latest

Test location	/workspace/coverage/default/11.spi_device_mem_parity.3469063531
Short name	T1082
Test name
Test status
Simulation time	57794441 ps
CPU time	1.11 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:02 PM PST 24
Peak memory	218904 kb
Host	smart-2becdb7b-5496-40bf-883a-8ef52160f686
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469063531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.spi_device_mem_parity.3469063531
Directory	/workspace/11.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1472282798
Short name	T843
Test name
Test status
Simulation time	24241932985 ps
CPU time	20.37 seconds
Started	Jan 07 01:20:07 PM PST 24
Finished	Jan 07 01:20:37 PM PST 24
Peak memory	241420 kb
Host	smart-6176ef42-00ef-4ca3-9982-85eeacc10e58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472282798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa p.1472282798
Directory	/workspace/11.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/11.spi_device_pass_cmd_filtering.3828229892
Short name	T241
Test name
Test status
Simulation time	1795498946 ps
CPU time	9.22 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:20:23 PM PST 24
Peak memory	239984 kb
Host	smart-c2fc2080-e4c0-436d-bacf-b4c5c7ad3284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828229892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3828229892
Directory	/workspace/11.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/11.spi_device_perf.454419560
Short name	T1245
Test name
Test status
Simulation time	24038863676 ps
CPU time	995.15 seconds
Started	Jan 07 01:19:51 PM PST 24
Finished	Jan 07 01:36:36 PM PST 24
Peak memory	274764 kb
Host	smart-ee8198e8-64e3-425b-8d5f-7fae8bd3441a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454419560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_perf.454419560
Directory	/workspace/11.spi_device_perf/latest

Test location	/workspace/coverage/default/11.spi_device_ram_cfg.2324497460
Short name	T781
Test name
Test status
Simulation time	97734116 ps
CPU time	0.73 seconds
Started	Jan 07 01:19:58 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	216688 kb
Host	smart-1e775eca-ecbb-4b6a-a8ec-10b8447c7450
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324497460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.2324497460
Directory	/workspace/11.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/11.spi_device_read_buffer_direct.2064859295
Short name	T693
Test name
Test status
Simulation time	1242994275 ps
CPU time	4.92 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:20:19 PM PST 24
Peak memory	235728 kb
Host	smart-4bb9ff4c-6267-4ab7-8a71-55a14146915f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2064859295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir ect.2064859295
Directory	/workspace/11.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/11.spi_device_rx_async_fifo_reset.847001203
Short name	T880
Test name
Test status
Simulation time	23037112 ps
CPU time	0.88 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:20:16 PM PST 24
Peak memory	208504 kb
Host	smart-f0b772ec-5711-48eb-ba08-2d2a3425cc52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847001203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_async_fifo_reset.847001203
Directory	/workspace/11.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/11.spi_device_rx_timeout.2883858619
Short name	T1750
Test name
Test status
Simulation time	3339859987 ps
CPU time	6.51 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:07 PM PST 24
Peak memory	216752 kb
Host	smart-e0f42313-1874-43ab-8467-96e4368d1911
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883858619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_rx_timeout.2883858619
Directory	/workspace/11.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/11.spi_device_smoke.2802141835
Short name	T1545
Test name
Test status
Simulation time	28347347 ps
CPU time	0.95 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	207892 kb
Host	smart-d96ed81a-4d0d-4588-b7d3-2ef1046b292a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802141835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_smoke.2802141835
Directory	/workspace/11.spi_device_smoke/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_all.746269651
Short name	T1049
Test name
Test status
Simulation time	4644361066 ps
CPU time	24.14 seconds
Started	Jan 07 01:19:57 PM PST 24
Finished	Jan 07 01:20:34 PM PST 24
Peak memory	221092 kb
Host	smart-9b8ab7a7-b954-4fc5-831f-a37f4d1e1ba2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746269651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.746269651
Directory	/workspace/11.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1291792738
Short name	T1150
Test name
Test status
Simulation time	91266276259 ps
CPU time	15.06 seconds
Started	Jan 07 01:19:53 PM PST 24
Finished	Jan 07 01:20:19 PM PST 24
Peak memory	216648 kb
Host	smart-9a405244-5f0a-4a54-99ff-d81084bba766
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291792738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1291792738
Directory	/workspace/11.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_rw.1697435721
Short name	T350
Test name
Test status
Simulation time	278690867 ps
CPU time	6.2 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:20:21 PM PST 24
Peak memory	216896 kb
Host	smart-4a4aa64c-dca5-4f26-9c1e-fd6743a6a6db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697435721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1697435721
Directory	/workspace/11.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_sts_read.3759103221
Short name	T461
Test name
Test status
Simulation time	128422602 ps
CPU time	1.04 seconds
Started	Jan 07 01:20:04 PM PST 24
Finished	Jan 07 01:20:16 PM PST 24
Peak memory	206964 kb
Host	smart-e505c4aa-bc06-4b12-8d9b-677e0538c1fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759103221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3759103221
Directory	/workspace/11.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/11.spi_device_tx_async_fifo_reset.3124516062
Short name	T1565
Test name
Test status
Simulation time	14717461 ps
CPU time	0.8 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	208392 kb
Host	smart-e812105c-6170-4315-b7ca-5f0113937f6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124516062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tx_async_fifo_reset.3124516062
Directory	/workspace/11.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/11.spi_device_txrx.860139318
Short name	T1126
Test name
Test status
Simulation time	169824671157 ps
CPU time	1675.64 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:48:03 PM PST 24
Peak memory	264464 kb
Host	smart-48023d54-5041-4184-bc07-157bd2fdc911
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860139318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_txrx.860139318
Directory	/workspace/11.spi_device_txrx/latest

Test location	/workspace/coverage/default/11.spi_device_upload.4062580756
Short name	T210
Test name
Test status
Simulation time	688778715 ps
CPU time	4.17 seconds
Started	Jan 07 01:20:05 PM PST 24
Finished	Jan 07 01:20:20 PM PST 24
Peak memory	235356 kb
Host	smart-73bb9845-b090-4a4f-b712-432dc3e81a96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062580756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4062580756
Directory	/workspace/11.spi_device_upload/latest

Test location	/workspace/coverage/default/12.spi_device_abort.3237260804
Short name	T433
Test name
Test status
Simulation time	52397280 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:20:29 PM PST 24
Peak memory	206596 kb
Host	smart-b53fe7f3-825b-4202-ac15-53780c14d2fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237260804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_abort.3237260804
Directory	/workspace/12.spi_device_abort/latest

Test location	/workspace/coverage/default/12.spi_device_bit_transfer.3846533274
Short name	T840
Test name
Test status
Simulation time	135916373 ps
CPU time	2.12 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	216868 kb
Host	smart-31370038-4588-40f0-9343-450ab96ae21c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846533274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_bit_transfer.3846533274
Directory	/workspace/12.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/12.spi_device_byte_transfer.2326511232
Short name	T703
Test name
Test status
Simulation time	1271777566 ps
CPU time	3.56 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:29 PM PST 24
Peak memory	216892 kb
Host	smart-2894f56e-8730-44c9-bf31-d0c4adf1f482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326511232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_byte_transfer.2326511232
Directory	/workspace/12.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/12.spi_device_cfg_cmd.2643987639
Short name	T1423
Test name
Test status
Simulation time	907861951 ps
CPU time	5.9 seconds
Started	Jan 07 01:20:20 PM PST 24
Finished	Jan 07 01:20:35 PM PST 24
Peak memory	241460 kb
Host	smart-2cf2f4cc-077e-4ea1-8c81-5bdd34eed629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643987639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2643987639
Directory	/workspace/12.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/12.spi_device_csb_read.1391553518
Short name	T1299
Test name
Test status
Simulation time	264689184 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:20:29 PM PST 24
Peak memory	206416 kb
Host	smart-7ecbdda5-bc9e-45c2-b149-212d8050eb19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391553518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1391553518
Directory	/workspace/12.spi_device_csb_read/latest

Test location	/workspace/coverage/default/12.spi_device_dummy_item_extra_dly.489949155
Short name	T1172
Test name
Test status
Simulation time	44769097393 ps
CPU time	730.06 seconds
Started	Jan 07 01:20:20 PM PST 24
Finished	Jan 07 01:32:39 PM PST 24
Peak memory	282496 kb
Host	smart-9dd36133-e86f-4c07-9578-b2e8ff6f1a1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489949155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_dummy_item_extra_dly.489949155
Directory	/workspace/12.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/12.spi_device_fifo_full.1613055345
Short name	T651
Test name
Test status
Simulation time	168659681370 ps
CPU time	1044.84 seconds
Started	Jan 07 01:19:59 PM PST 24
Finished	Jan 07 01:37:36 PM PST 24
Peak memory	257864 kb
Host	smart-ebcba7fb-a81b-46ac-8270-a5f34fc2f4ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613055345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_full.1613055345
Directory	/workspace/12.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/12.spi_device_fifo_underflow_overflow.3093344046
Short name	T1613
Test name
Test status
Simulation time	307761082376 ps
CPU time	393.31 seconds
Started	Jan 07 01:20:05 PM PST 24
Finished	Jan 07 01:26:49 PM PST 24
Peak memory	436048 kb
Host	smart-c1b73dba-0849-489e-84b6-cf05025754ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093344046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_fifo_underflow_overf low.3093344046
Directory	/workspace/12.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/12.spi_device_flash_all.4270331041
Short name	T521
Test name
Test status
Simulation time	1114413043 ps
CPU time	8.38 seconds
Started	Jan 07 01:20:22 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	240476 kb
Host	smart-26372f40-eef0-4921-aa93-68b1abeffcad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270331041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4270331041
Directory	/workspace/12.spi_device_flash_all/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm.4220837978
Short name	T1639
Test name
Test status
Simulation time	37902930587 ps
CPU time	273.37 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:25:00 PM PST 24
Peak memory	256444 kb
Host	smart-4aa1ca9a-fbd5-47d5-ac38-bdf95d9c90e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220837978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4220837978
Directory	/workspace/12.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.276589501
Short name	T1215
Test name
Test status
Simulation time	98104216769 ps
CPU time	389.87 seconds
Started	Jan 07 01:20:21 PM PST 24
Finished	Jan 07 01:27:00 PM PST 24
Peak memory	253128 kb
Host	smart-24f88a87-5cd3-4dac-8e97-381c2047eb7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276589501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle .276589501
Directory	/workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/12.spi_device_flash_mode.313525110
Short name	T258
Test name
Test status
Simulation time	9911292706 ps
CPU time	21.32 seconds
Started	Jan 07 01:20:22 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	240836 kb
Host	smart-b48ee19a-f594-46e4-a3f9-54d04b8263c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313525110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.313525110
Directory	/workspace/12.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/12.spi_device_intercept.2540241995
Short name	T246
Test name
Test status
Simulation time	11943098457 ps
CPU time	12.55 seconds
Started	Jan 07 01:20:21 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	241404 kb
Host	smart-1932556f-ac35-4c5f-bd2b-00e494aac217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540241995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2540241995
Directory	/workspace/12.spi_device_intercept/latest

Test location	/workspace/coverage/default/12.spi_device_intr.2417656514
Short name	T1350
Test name
Test status
Simulation time	153390001958 ps
CPU time	34.51 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:21:03 PM PST 24
Peak memory	232552 kb
Host	smart-e3b5fd61-0e4c-4a3e-b82f-b67d9784570c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417656514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intr.2417656514
Directory	/workspace/12.spi_device_intr/latest

Test location	/workspace/coverage/default/12.spi_device_mailbox.3468958282
Short name	T1047
Test name
Test status
Simulation time	1931474697 ps
CPU time	10.89 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:20:39 PM PST 24
Peak memory	234392 kb
Host	smart-69cae1fe-0288-4dcd-8d3f-5a537016c44b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468958282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3468958282
Directory	/workspace/12.spi_device_mailbox/latest

Test location	/workspace/coverage/default/12.spi_device_mem_parity.3422320586
Short name	T469
Test name
Test status
Simulation time	61873663 ps
CPU time	1.02 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:26 PM PST 24
Peak memory	218864 kb
Host	smart-1eb75fa8-e523-4e9a-9327-62d54457577c
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422320586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.spi_device_mem_parity.3422320586
Directory	/workspace/12.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2415295366
Short name	T1394
Test name
Test status
Simulation time	2045187590 ps
CPU time	8.38 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:34 PM PST 24
Peak memory	224992 kb
Host	smart-48a5995e-2cc4-43bc-a195-a54e519705de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415295366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.2415295366
Directory	/workspace/12.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/12.spi_device_pass_cmd_filtering.377399950
Short name	T1023
Test name
Test status
Simulation time	11539831219 ps
CPU time	16.95 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	239224 kb
Host	smart-0d9fb313-86ca-466c-97d8-1228b3b8acc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377399950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.377399950
Directory	/workspace/12.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/12.spi_device_perf.3989763038
Short name	T1284
Test name
Test status
Simulation time	19382408660 ps
CPU time	452.34 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:28:00 PM PST 24
Peak memory	256980 kb
Host	smart-48a42aeb-9c31-4bf0-b381-f8cb2e4d58d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989763038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_perf.3989763038
Directory	/workspace/12.spi_device_perf/latest

Test location	/workspace/coverage/default/12.spi_device_ram_cfg.136494328
Short name	T1009
Test name
Test status
Simulation time	43316496 ps
CPU time	0.73 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	216516 kb
Host	smart-93e08752-67e3-4d3b-b89c-2ae88a13936e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136494328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.136494328
Directory	/workspace/12.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/12.spi_device_read_buffer_direct.4152145695
Short name	T938
Test name
Test status
Simulation time	159455276 ps
CPU time	3.51 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:29 PM PST 24
Peak memory	218544 kb
Host	smart-962e41d9-5b08-4438-b953-023d5a35badd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4152145695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir ect.4152145695
Directory	/workspace/12.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/12.spi_device_rx_timeout.1729676918
Short name	T856
Test name
Test status
Simulation time	518806175 ps
CPU time	4.98 seconds
Started	Jan 07 01:20:16 PM PST 24
Finished	Jan 07 01:20:28 PM PST 24
Peak memory	216740 kb
Host	smart-6b6f3587-063b-4d5d-a97b-31d4830de684
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729676918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_rx_timeout.1729676918
Directory	/workspace/12.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/12.spi_device_smoke.3671110164
Short name	T831
Test name
Test status
Simulation time	110708572 ps
CPU time	1.12 seconds
Started	Jan 07 01:20:00 PM PST 24
Finished	Jan 07 01:20:13 PM PST 24
Peak memory	208300 kb
Host	smart-b561cd5e-7c5c-44b7-8b29-834920f4726e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671110164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_smoke.3671110164
Directory	/workspace/12.spi_device_smoke/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_all.1036941680
Short name	T1037
Test name
Test status
Simulation time	2666646453 ps
CPU time	21.97 seconds
Started	Jan 07 01:20:19 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	217156 kb
Host	smart-72502dfc-2bec-4b0a-818d-4979e40f7cbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036941680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1036941680
Directory	/workspace/12.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4135630987
Short name	T102
Test name
Test status
Simulation time	32889556394 ps
CPU time	18.71 seconds
Started	Jan 07 01:20:22 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	216828 kb
Host	smart-6841ef87-b5b5-405c-956b-8271ba8d0d98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135630987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4135630987
Directory	/workspace/12.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_rw.945272007
Short name	T573
Test name
Test status
Simulation time	399132809 ps
CPU time	3.33 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:20:30 PM PST 24
Peak memory	216760 kb
Host	smart-fde3300f-e185-46ab-8b8d-3e0f3490a69d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945272007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.945272007
Directory	/workspace/12.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_sts_read.4105815106
Short name	T1147
Test name
Test status
Simulation time	131481355 ps
CPU time	0.83 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:26 PM PST 24
Peak memory	206884 kb
Host	smart-2447c5c0-65fa-411d-9e23-86d10eb209d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105815106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4105815106
Directory	/workspace/12.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/12.spi_device_txrx.1672211826
Short name	T841
Test name
Test status
Simulation time	77902277212 ps
CPU time	737.07 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:32:29 PM PST 24
Peak memory	297556 kb
Host	smart-c11f3b57-a2be-4ac5-a163-dae1924386ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672211826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_txrx.1672211826
Directory	/workspace/12.spi_device_txrx/latest

Test location	/workspace/coverage/default/12.spi_device_upload.3473170374
Short name	T895
Test name
Test status
Simulation time	52952013 ps
CPU time	2.34 seconds
Started	Jan 07 01:20:20 PM PST 24
Finished	Jan 07 01:20:32 PM PST 24
Peak memory	217292 kb
Host	smart-0e492089-44da-4a6a-be17-4c664b94b641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473170374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3473170374
Directory	/workspace/12.spi_device_upload/latest

Test location	/workspace/coverage/default/13.spi_device_abort.3607833530
Short name	T571
Test name
Test status
Simulation time	16145201 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:32 PM PST 24
Finished	Jan 07 01:20:38 PM PST 24
Peak memory	206676 kb
Host	smart-411541c0-6871-49e7-9afd-c3b79440182b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607833530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_abort.3607833530
Directory	/workspace/13.spi_device_abort/latest

Test location	/workspace/coverage/default/13.spi_device_alert_test.3277481863
Short name	T1227
Test name
Test status
Simulation time	14506373 ps
CPU time	0.71 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	206488 kb
Host	smart-4c93a35f-0563-45b9-b411-d5a8e89081e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277481863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test. 3277481863
Directory	/workspace/13.spi_device_alert_test/latest

Test location	/workspace/coverage/default/13.spi_device_bit_transfer.958020660
Short name	T816
Test name
Test status
Simulation time	1326001296 ps
CPU time	2.31 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	216808 kb
Host	smart-896a4a22-3b99-435e-8d5d-767a56a40729
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958020660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_bit_transfer.958020660
Directory	/workspace/13.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/13.spi_device_byte_transfer.3914444283
Short name	T1693
Test name
Test status
Simulation time	101860458 ps
CPU time	2.53 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	216828 kb
Host	smart-d8b19980-4275-4aac-86f7-9bf40e3f9c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914444283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_byte_transfer.3914444283
Directory	/workspace/13.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/13.spi_device_cfg_cmd.2616647663
Short name	T1587
Test name
Test status
Simulation time	6401633211 ps
CPU time	7.22 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:48 PM PST 24
Peak memory	239436 kb
Host	smart-41256382-4e59-4cbd-ae13-14bb69ed2217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616647663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2616647663
Directory	/workspace/13.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/13.spi_device_csb_read.3550265750
Short name	T1671
Test name
Test status
Simulation time	64221251 ps
CPU time	0.77 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	207556 kb
Host	smart-b3a2ce6b-5276-475c-953f-df1f72af8b71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550265750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3550265750
Directory	/workspace/13.spi_device_csb_read/latest

Test location	/workspace/coverage/default/13.spi_device_extreme_fifo_size.872090289
Short name	T687
Test name
Test status
Simulation time	177535940933 ps
CPU time	4029.44 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 02:27:37 PM PST 24
Peak memory	221452 kb
Host	smart-5968734e-7c2a-47af-afd9-b426e50085b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872090289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_extreme_fifo_size.872090289
Directory	/workspace/13.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/13.spi_device_fifo_full.2098221371
Short name	T778
Test name
Test status
Simulation time	194739993209 ps
CPU time	2692.1 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 02:05:19 PM PST 24
Peak memory	314696 kb
Host	smart-3fb6d216-365d-4e24-bcc7-848ed203624f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098221371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_full.2098221371
Directory	/workspace/13.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/13.spi_device_fifo_underflow_overflow.3787446448
Short name	T1032
Test name
Test status
Simulation time	408646845531 ps
CPU time	1309.4 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:42:16 PM PST 24
Peak memory	948152 kb
Host	smart-60f3134d-2cb3-4dec-aab2-48f0ccd475c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787446448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_fifo_underflow_overf low.3787446448
Directory	/workspace/13.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/13.spi_device_flash_all.1188015507
Short name	T1711
Test name
Test status
Simulation time	2140467460 ps
CPU time	38.01 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:21:20 PM PST 24
Peak memory	257772 kb
Host	smart-ae704968-e5c7-471d-bce4-74acaeab0894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188015507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1188015507
Directory	/workspace/13.spi_device_flash_all/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm.3617169692
Short name	T732
Test name
Test status
Simulation time	3367602798 ps
CPU time	35.06 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:21:17 PM PST 24
Peak memory	249764 kb
Host	smart-39e9c2f5-a23a-4184-bf4f-5baed590d2d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617169692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3617169692
Directory	/workspace/13.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.735323527
Short name	T328
Test name
Test status
Simulation time	43807203326 ps
CPU time	103.13 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:22:28 PM PST 24
Peak memory	267912 kb
Host	smart-a6a58b6b-4a9e-45f2-914c-3c9d630b2825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735323527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle .735323527
Directory	/workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/13.spi_device_flash_mode.2010953290
Short name	T1369
Test name
Test status
Simulation time	286531913 ps
CPU time	14.49 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	248540 kb
Host	smart-a775b5c8-8f05-438c-b593-95451d5b5557
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010953290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2010953290
Directory	/workspace/13.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/13.spi_device_intercept.1332976146
Short name	T1249
Test name
Test status
Simulation time	915457692 ps
CPU time	5.83 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	219076 kb
Host	smart-5cff1f09-b678-4d28-93bf-97fad04764be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332976146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1332976146
Directory	/workspace/13.spi_device_intercept/latest

Test location	/workspace/coverage/default/13.spi_device_intr.3098110659
Short name	T865
Test name
Test status
Simulation time	12988808782 ps
CPU time	11.45 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:20:37 PM PST 24
Peak memory	217168 kb
Host	smart-056166fc-d1be-452b-8c15-ff9a20df0eae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098110659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intr.3098110659
Directory	/workspace/13.spi_device_intr/latest

Test location	/workspace/coverage/default/13.spi_device_mailbox.1969677567
Short name	T1013
Test name
Test status
Simulation time	2146269858 ps
CPU time	7.47 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	240636 kb
Host	smart-b54fbd7a-402b-4619-9701-ec94ed588fb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969677567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1969677567
Directory	/workspace/13.spi_device_mailbox/latest

Test location	/workspace/coverage/default/13.spi_device_mem_parity.2364335752
Short name	T1246
Test name
Test status
Simulation time	14121601 ps
CPU time	1.04 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	218844 kb
Host	smart-2b77b7c2-afce-4f57-8e1d-95381a3a7ab4
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364335752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.spi_device_mem_parity.2364335752
Directory	/workspace/13.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.493600800
Short name	T657
Test name
Test status
Simulation time	589068393 ps
CPU time	5.23 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	218684 kb
Host	smart-3e33ea52-0358-4e9d-bd07-c92e09bbc3b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493600800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap .493600800
Directory	/workspace/13.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/13.spi_device_pass_cmd_filtering.1631020906
Short name	T1411
Test name
Test status
Simulation time	28715394644 ps
CPU time	23.51 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	231648 kb
Host	smart-31e7b929-f446-4da3-8f32-cb3e58c86c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631020906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1631020906
Directory	/workspace/13.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/13.spi_device_perf.778423725
Short name	T513
Test name
Test status
Simulation time	78272934115 ps
CPU time	965.24 seconds
Started	Jan 07 01:20:18 PM PST 24
Finished	Jan 07 01:36:32 PM PST 24
Peak memory	301528 kb
Host	smart-748a144e-f73d-4288-bee1-cb8368a6e9d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778423725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_perf.778423725
Directory	/workspace/13.spi_device_perf/latest

Test location	/workspace/coverage/default/13.spi_device_ram_cfg.1738833934
Short name	T86
Test name
Test status
Simulation time	18785922 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:20:39 PM PST 24
Peak memory	216660 kb
Host	smart-cb4feef1-2002-472e-8a23-649943bdf6a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738833934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1738833934
Directory	/workspace/13.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/13.spi_device_read_buffer_direct.4253289409
Short name	T717
Test name
Test status
Simulation time	384046745 ps
CPU time	3.4 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:43 PM PST 24
Peak memory	220180 kb
Host	smart-90c37e0b-0634-4b35-b79d-29ed6acd4842
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4253289409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.4253289409
Directory	/workspace/13.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/13.spi_device_rx_async_fifo_reset.2571150901
Short name	T1089
Test name
Test status
Simulation time	161104851 ps
CPU time	0.91 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	208552 kb
Host	smart-dbd85026-5037-48ad-b4ac-3d163593132a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571150901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_async_fifo_reset.2571150901
Directory	/workspace/13.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/13.spi_device_rx_timeout.2522983971
Short name	T1730
Test name
Test status
Simulation time	1812130527 ps
CPU time	4.64 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	216724 kb
Host	smart-d5a7090d-2560-497f-bf92-e4d19e80c38d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522983971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_rx_timeout.2522983971
Directory	/workspace/13.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/13.spi_device_smoke.4178197403
Short name	T779
Test name
Test status
Simulation time	116480196 ps
CPU time	1.23 seconds
Started	Jan 07 01:20:20 PM PST 24
Finished	Jan 07 01:20:31 PM PST 24
Peak memory	216704 kb
Host	smart-600a8a2b-731f-46eb-8ea1-7386220ea754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4178197403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_smoke.4178197403
Directory	/workspace/13.spi_device_smoke/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_all.3231763628
Short name	T1322
Test name
Test status
Simulation time	9987637691 ps
CPU time	17.98 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:21:01 PM PST 24
Peak memory	217036 kb
Host	smart-8720288e-894a-4a9f-85df-987987fbea0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231763628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3231763628
Directory	/workspace/13.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1110255793
Short name	T1640
Test name
Test status
Simulation time	34065642308 ps
CPU time	16.63 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:21:09 PM PST 24
Peak memory	216832 kb
Host	smart-2b1c43cf-ac2d-4c19-9a2f-c65fd11d452c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110255793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1110255793
Directory	/workspace/13.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_rw.2960441244
Short name	T1705
Test name
Test status
Simulation time	927872204 ps
CPU time	2.32 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	216752 kb
Host	smart-7bbe0ce5-b07e-4c6c-8af4-27563c608a14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960441244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2960441244
Directory	/workspace/13.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_sts_read.1171619056
Short name	T1155
Test name
Test status
Simulation time	47246349 ps
CPU time	0.88 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:43 PM PST 24
Peak memory	206856 kb
Host	smart-dd1331a1-3d78-4e4c-8875-a16176bc2906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171619056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1171619056
Directory	/workspace/13.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/13.spi_device_tx_async_fifo_reset.2280673682
Short name	T1595
Test name
Test status
Simulation time	16202432 ps
CPU time	0.81 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	208488 kb
Host	smart-fe644936-b22c-43e1-930a-52021e5c1226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280673682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tx_async_fifo_reset.2280673682
Directory	/workspace/13.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/13.spi_device_txrx.381299065
Short name	T669
Test name
Test status
Simulation time	22284616356 ps
CPU time	281.23 seconds
Started	Jan 07 01:20:17 PM PST 24
Finished	Jan 07 01:25:07 PM PST 24
Peak memory	261064 kb
Host	smart-084709d5-894e-4f6c-b045-0afa561eb366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381299065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_txrx.381299065
Directory	/workspace/13.spi_device_txrx/latest

Test location	/workspace/coverage/default/13.spi_device_upload.3860801238
Short name	T809
Test name
Test status
Simulation time	629151700 ps
CPU time	3.78 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	238840 kb
Host	smart-2b40d689-c514-4949-805b-3735f0e74b99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860801238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3860801238
Directory	/workspace/13.spi_device_upload/latest

Test location	/workspace/coverage/default/14.spi_device_abort.271546725
Short name	T497
Test name
Test status
Simulation time	48009869 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:43 PM PST 24
Peak memory	206640 kb
Host	smart-8dd0e21a-dda6-411a-a281-d4976d46bc8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271546725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_abort.271546725
Directory	/workspace/14.spi_device_abort/latest

Test location	/workspace/coverage/default/14.spi_device_alert_test.1015932672
Short name	T748
Test name
Test status
Simulation time	11904309 ps
CPU time	0.7 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:20:39 PM PST 24
Peak memory	206496 kb
Host	smart-793e8f3e-5af7-49c7-9208-e1011f22d0c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015932672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 1015932672
Directory	/workspace/14.spi_device_alert_test/latest

Test location	/workspace/coverage/default/14.spi_device_bit_transfer.3332585595
Short name	T438
Test name
Test status
Simulation time	810886215 ps
CPU time	2.45 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:47 PM PST 24
Peak memory	216820 kb
Host	smart-82f74973-41b2-454c-b98d-b7a3623751b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332585595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_bit_transfer.3332585595
Directory	/workspace/14.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/14.spi_device_byte_transfer.1605315744
Short name	T762
Test name
Test status
Simulation time	595956407 ps
CPU time	2.64 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:48 PM PST 24
Peak memory	216840 kb
Host	smart-5715ae2f-7d11-4395-b862-f8bc0b890dc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605315744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_byte_transfer.1605315744
Directory	/workspace/14.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/14.spi_device_cfg_cmd.2091338537
Short name	T12
Test name
Test status
Simulation time	4079682845 ps
CPU time	6.83 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	240712 kb
Host	smart-5601ac9b-8e6f-4a62-9811-cf52d4792cb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091338537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2091338537
Directory	/workspace/14.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/14.spi_device_csb_read.914847613
Short name	T1635
Test name
Test status
Simulation time	37862590 ps
CPU time	0.8 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	207548 kb
Host	smart-c137440b-57d6-4baf-9b8a-4e54e5632d46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914847613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.914847613
Directory	/workspace/14.spi_device_csb_read/latest

Test location	/workspace/coverage/default/14.spi_device_dummy_item_extra_dly.3008427348
Short name	T1475
Test name
Test status
Simulation time	294626321597 ps
CPU time	1147.51 seconds
Started	Jan 07 01:20:38 PM PST 24
Finished	Jan 07 01:39:55 PM PST 24
Peak memory	307004 kb
Host	smart-40e7a52c-7966-4bda-a2ff-5fdc3ffcfddd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008427348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_dummy_item_extra_dly.3008427348
Directory	/workspace/14.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/14.spi_device_extreme_fifo_size.1382897048
Short name	T790
Test name
Test status
Simulation time	59051731278 ps
CPU time	2339.63 seconds
Started	Jan 07 01:20:39 PM PST 24
Finished	Jan 07 01:59:47 PM PST 24
Peak memory	220136 kb
Host	smart-8b3ad4ce-e62d-4677-9736-5972f469396c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382897048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_extreme_fifo_size.1382897048
Directory	/workspace/14.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/14.spi_device_fifo_full.3397194296
Short name	T633
Test name
Test status
Simulation time	20860456633 ps
CPU time	1116.71 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:39:19 PM PST 24
Peak memory	262900 kb
Host	smart-57db3755-cd73-4e81-a164-816f57cdffa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397194296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_full.3397194296
Directory	/workspace/14.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/14.spi_device_fifo_underflow_overflow.2179345073
Short name	T1749
Test name
Test status
Simulation time	81176603995 ps
CPU time	651.21 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:31:30 PM PST 24
Peak memory	629984 kb
Host	smart-506d979d-2876-46b4-b159-4ffe59c96755
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2179345073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_fifo_underflow_overf low.2179345073
Directory	/workspace/14.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/14.spi_device_flash_all.2803586579
Short name	T886
Test name
Test status
Simulation time	21738269002 ps
CPU time	32.49 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:21:11 PM PST 24
Peak memory	240364 kb
Host	smart-9d1c3ae5-dabe-4db3-95e2-c163d1ab4bdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803586579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2803586579
Directory	/workspace/14.spi_device_flash_all/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm.1799364292
Short name	T325
Test name
Test status
Simulation time	199956389268 ps
CPU time	351.84 seconds
Started	Jan 07 01:20:32 PM PST 24
Finished	Jan 07 01:26:30 PM PST 24
Peak memory	269240 kb
Host	smart-2c08c7f5-4c9c-4de6-8f09-0478b3d4bb9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799364292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1799364292
Directory	/workspace/14.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2367777552
Short name	T315
Test name
Test status
Simulation time	5327825977 ps
CPU time	66.5 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:21:50 PM PST 24
Peak memory	249824 kb
Host	smart-5ec2f2c9-fdae-4670-b208-fafef84fdb78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367777552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl e.2367777552
Directory	/workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/14.spi_device_flash_mode.408555288
Short name	T1125
Test name
Test status
Simulation time	5066060821 ps
CPU time	14.14 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	235924 kb
Host	smart-682cf716-9ffe-4710-9d29-c90eb11b78e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408555288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.408555288
Directory	/workspace/14.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/14.spi_device_intercept.1660799853
Short name	T114
Test name
Test status
Simulation time	7974577568 ps
CPU time	15.02 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:56 PM PST 24
Peak memory	221776 kb
Host	smart-62b884e5-12a4-49d5-8dc9-e6749196cf0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660799853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1660799853
Directory	/workspace/14.spi_device_intercept/latest

Test location	/workspace/coverage/default/14.spi_device_intr.913031888
Short name	T1124
Test name
Test status
Simulation time	9713019135 ps
CPU time	54.13 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:21:33 PM PST 24
Peak memory	232768 kb
Host	smart-ec2d253a-279c-459a-8201-11c3c0ae2d61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913031888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intr.913031888
Directory	/workspace/14.spi_device_intr/latest

Test location	/workspace/coverage/default/14.spi_device_mailbox.838293996
Short name	T1713
Test name
Test status
Simulation time	257573976 ps
CPU time	6.21 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:49 PM PST 24
Peak memory	229116 kb
Host	smart-c9680a8e-29b0-4dd4-a8f5-689f517933c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838293996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.838293996
Directory	/workspace/14.spi_device_mailbox/latest

Test location	/workspace/coverage/default/14.spi_device_mem_parity.3267603524
Short name	T1499
Test name
Test status
Simulation time	53875832 ps
CPU time	1.07 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:40 PM PST 24
Peak memory	218892 kb
Host	smart-a35d88d4-468b-4298-81db-7ad51d16134b
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267603524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.spi_device_mem_parity.3267603524
Directory	/workspace/14.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4166073291
Short name	T291
Test name
Test status
Simulation time	3138986401 ps
CPU time	12.09 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	239420 kb
Host	smart-5ae93a20-6f34-4bef-85fc-d00ed6050a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166073291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.4166073291
Directory	/workspace/14.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/14.spi_device_pass_cmd_filtering.241639990
Short name	T1368
Test name
Test status
Simulation time	349796379 ps
CPU time	4.16 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	238136 kb
Host	smart-7ca66267-aee9-495d-8a53-9d972b4d01cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241639990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.241639990
Directory	/workspace/14.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/14.spi_device_perf.2670172450
Short name	T1605
Test name
Test status
Simulation time	23525853584 ps
CPU time	470.41 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:28:29 PM PST 24
Peak memory	249084 kb
Host	smart-1108c9e5-2387-4f34-9e69-b63fcb3be796
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670172450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_perf.2670172450
Directory	/workspace/14.spi_device_perf/latest

Test location	/workspace/coverage/default/14.spi_device_ram_cfg.3802304477
Short name	T575
Test name
Test status
Simulation time	20526139 ps
CPU time	0.71 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:40 PM PST 24
Peak memory	216712 kb
Host	smart-0603d55a-7623-43cb-87aa-415a7bff8d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802304477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3802304477
Directory	/workspace/14.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/14.spi_device_read_buffer_direct.2178572779
Short name	T849
Test name
Test status
Simulation time	4604555758 ps
CPU time	5.87 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:48 PM PST 24
Peak memory	221144 kb
Host	smart-fa662d85-ffeb-49cc-832d-f9767c1f684d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2178572779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir ect.2178572779
Directory	/workspace/14.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/14.spi_device_rx_async_fifo_reset.789605384
Short name	T1103
Test name
Test status
Simulation time	86444957 ps
CPU time	0.95 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	208468 kb
Host	smart-86d313f3-b86c-49e1-b70a-4e7a66251e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789605384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_async_fifo_reset.789605384
Directory	/workspace/14.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/14.spi_device_rx_timeout.1937683256
Short name	T1262
Test name
Test status
Simulation time	666823329 ps
CPU time	5.72 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:47 PM PST 24
Peak memory	216836 kb
Host	smart-b398df78-d450-42be-a0f2-01ec69268b78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937683256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_rx_timeout.1937683256
Directory	/workspace/14.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/14.spi_device_smoke.1415984112
Short name	T683
Test name
Test status
Simulation time	99186221 ps
CPU time	1.03 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	208092 kb
Host	smart-d02b5a58-1a16-4000-a3c7-3b235d96a9b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415984112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_smoke.1415984112
Directory	/workspace/14.spi_device_smoke/latest

Test location	/workspace/coverage/default/14.spi_device_stress_all.3606216131
Short name	T1261
Test name
Test status
Simulation time	1293614886919 ps
CPU time	9042.7 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 03:51:27 PM PST 24
Peak memory	1204976 kb
Host	smart-090d8868-3ce6-4846-8f87-d3885b64dd4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606216131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre ss_all.3606216131
Directory	/workspace/14.spi_device_stress_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_all.1574183584
Short name	T720
Test name
Test status
Simulation time	4457279122 ps
CPU time	32.29 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:21:16 PM PST 24
Peak memory	221432 kb
Host	smart-5eb35e14-549e-4a36-b09e-037c6d7ad8ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574183584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1574183584
Directory	/workspace/14.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1118227785
Short name	T463
Test name
Test status
Simulation time	5135816466 ps
CPU time	8.25 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	216684 kb
Host	smart-d1aa7845-32bf-41d5-a513-7bd45f501995
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118227785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1118227785
Directory	/workspace/14.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_rw.2322310840
Short name	T713
Test name
Test status
Simulation time	346279395 ps
CPU time	2.23 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	216776 kb
Host	smart-d23bd470-00d1-4c53-9d27-a3ab427565e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322310840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2322310840
Directory	/workspace/14.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_sts_read.829717654
Short name	T101
Test name
Test status
Simulation time	80679663 ps
CPU time	0.78 seconds
Started	Jan 07 01:20:32 PM PST 24
Finished	Jan 07 01:20:39 PM PST 24
Peak memory	206848 kb
Host	smart-fcf451eb-b2af-4ae0-b872-c46d3ef5c6d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829717654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.829717654
Directory	/workspace/14.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/14.spi_device_tx_async_fifo_reset.56729669
Short name	T536
Test name
Test status
Simulation time	17482803 ps
CPU time	0.77 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	208292 kb
Host	smart-171e1b12-44f9-42c7-a209-cf62654f0415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56729669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tx_async_fifo_reset.56729669
Directory	/workspace/14.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/14.spi_device_txrx.1896259061
Short name	T889
Test name
Test status
Simulation time	11772454302 ps
CPU time	138.97 seconds
Started	Jan 07 01:20:39 PM PST 24
Finished	Jan 07 01:23:06 PM PST 24
Peak memory	286644 kb
Host	smart-3bb662ec-ce22-4ba1-8f44-b85486b2267d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896259061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_txrx.1896259061
Directory	/workspace/14.spi_device_txrx/latest

Test location	/workspace/coverage/default/14.spi_device_upload.3469839226
Short name	T288
Test name
Test status
Simulation time	180465493 ps
CPU time	3.38 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	239800 kb
Host	smart-5739ae29-c9ca-43ea-9260-c471a9dd142f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469839226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3469839226
Directory	/workspace/14.spi_device_upload/latest

Test location	/workspace/coverage/default/15.spi_device_abort.430819723
Short name	T432
Test name
Test status
Simulation time	40417745 ps
CPU time	0.72 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	206680 kb
Host	smart-fc2a01fd-e0fc-4225-afa7-27944647aa57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430819723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_abort.430819723
Directory	/workspace/15.spi_device_abort/latest

Test location	/workspace/coverage/default/15.spi_device_alert_test.3075686580
Short name	T487
Test name
Test status
Simulation time	16323430 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	206544 kb
Host	smart-47f4078d-9afd-46b8-9e11-afed0846f504
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075686580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 3075686580
Directory	/workspace/15.spi_device_alert_test/latest

Test location	/workspace/coverage/default/15.spi_device_bit_transfer.183359817
Short name	T810
Test name
Test status
Simulation time	176276879 ps
CPU time	2.55 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:47 PM PST 24
Peak memory	216084 kb
Host	smart-a9ee9dcd-c1dc-44da-a892-df0602517082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183359817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_bit_transfer.183359817
Directory	/workspace/15.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/15.spi_device_byte_transfer.1629394268
Short name	T1327
Test name
Test status
Simulation time	268372380 ps
CPU time	2.66 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	216832 kb
Host	smart-e21fabf9-9be2-46ec-9101-5baebc17de4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629394268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_byte_transfer.1629394268
Directory	/workspace/15.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/15.spi_device_cfg_cmd.990055940
Short name	T269
Test name
Test status
Simulation time	66257561 ps
CPU time	2.81 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	234392 kb
Host	smart-4c63e1ef-c1b2-4195-88a1-dd565d0982ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990055940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.990055940
Directory	/workspace/15.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/15.spi_device_csb_read.971805690
Short name	T1620
Test name
Test status
Simulation time	17725173 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:43 PM PST 24
Peak memory	206552 kb
Host	smart-474659b0-c81f-4a34-b27c-0429d2ca10ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971805690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.971805690
Directory	/workspace/15.spi_device_csb_read/latest

Test location	/workspace/coverage/default/15.spi_device_dummy_item_extra_dly.2429099717
Short name	T675
Test name
Test status
Simulation time	156445059750 ps
CPU time	588.68 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:30:35 PM PST 24
Peak memory	311340 kb
Host	smart-26a61e04-2968-4307-8b35-16772a5d852d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429099717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_dummy_item_extra_dly.2429099717
Directory	/workspace/15.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/15.spi_device_extreme_fifo_size.1129079459
Short name	T797
Test name
Test status
Simulation time	322578465780 ps
CPU time	1430.48 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:44:31 PM PST 24
Peak memory	221612 kb
Host	smart-e3ecedfb-b4bc-4509-8d7d-ffb77c2bb001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129079459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_extreme_fifo_size.1129079459
Directory	/workspace/15.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/15.spi_device_fifo_full.560318874
Short name	T1335
Test name
Test status
Simulation time	263897006745 ps
CPU time	1046.69 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:38:08 PM PST 24
Peak memory	264072 kb
Host	smart-3f7449e6-5f08-4f9c-94e9-7bc3a21d09b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560318874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_full.560318874
Directory	/workspace/15.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/15.spi_device_fifo_underflow_overflow.2371928701
Short name	T1266
Test name
Test status
Simulation time	37095083396 ps
CPU time	410.18 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:27:33 PM PST 24
Peak memory	416572 kb
Host	smart-353a7336-609f-4498-88b1-5408b09c64db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371928701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_fifo_underflow_overf low.2371928701
Directory	/workspace/15.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/15.spi_device_flash_all.309888974
Short name	T226
Test name
Test status
Simulation time	47315943514 ps
CPU time	274.29 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	268456 kb
Host	smart-7337c3bf-4ca8-48af-b000-75b1e233e84d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309888974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.309888974
Directory	/workspace/15.spi_device_flash_all/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm.131103918
Short name	T311
Test name
Test status
Simulation time	1280678472000 ps
CPU time	639.42 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 01:31:28 PM PST 24
Peak memory	268676 kb
Host	smart-15a55575-112b-416a-a148-b63cf3229d99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131103918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.131103918
Directory	/workspace/15.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1532255200
Short name	T1336
Test name
Test status
Simulation time	50622227134 ps
CPU time	373.07 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:27:03 PM PST 24
Peak memory	256296 kb
Host	smart-bc9a134f-5c37-4143-920a-20eb3f821e8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532255200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl e.1532255200
Directory	/workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/15.spi_device_flash_mode.3435722552
Short name	T1417
Test name
Test status
Simulation time	1138670418 ps
CPU time	5.57 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	239080 kb
Host	smart-73d7e87f-1234-4b28-8986-26f20c4264bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435722552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3435722552
Directory	/workspace/15.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/15.spi_device_intercept.3808366309
Short name	T218
Test name
Test status
Simulation time	656376195 ps
CPU time	7.46 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	238284 kb
Host	smart-ba469bd8-9b2e-4a34-8de3-193fa1eda11e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808366309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3808366309
Directory	/workspace/15.spi_device_intercept/latest

Test location	/workspace/coverage/default/15.spi_device_intr.827802895
Short name	T1689
Test name
Test status
Simulation time	9930108082 ps
CPU time	39.52 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:21:20 PM PST 24
Peak memory	233308 kb
Host	smart-be0233f2-cb9b-4b90-bcb8-4509d728fa57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827802895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intr.827802895
Directory	/workspace/15.spi_device_intr/latest

Test location	/workspace/coverage/default/15.spi_device_mailbox.3192516755
Short name	T980
Test name
Test status
Simulation time	47193776295 ps
CPU time	35.51 seconds
Started	Jan 07 01:20:32 PM PST 24
Finished	Jan 07 01:21:13 PM PST 24
Peak memory	241492 kb
Host	smart-94e95e9e-2c3d-43e1-9d31-5f45d0404ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192516755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3192516755
Directory	/workspace/15.spi_device_mailbox/latest

Test location	/workspace/coverage/default/15.spi_device_mem_parity.949597163
Short name	T1251
Test name
Test status
Simulation time	38126674 ps
CPU time	1.1 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	218836 kb
Host	smart-162a0bc4-904f-46bb-953a-072caef0656c
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949597163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.949597163
Directory	/workspace/15.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3900068458
Short name	T229
Test name
Test status
Simulation time	346571962 ps
CPU time	7.52 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	230808 kb
Host	smart-240bd880-7483-4cc9-b383-b3713144a872
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900068458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa p.3900068458
Directory	/workspace/15.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/15.spi_device_pass_cmd_filtering.2641294200
Short name	T1617
Test name
Test status
Simulation time	34053648635 ps
CPU time	26.59 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:21:09 PM PST 24
Peak memory	238424 kb
Host	smart-dddde070-c806-468c-ba86-29ab13a4dcc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641294200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2641294200
Directory	/workspace/15.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/15.spi_device_perf.2003563417
Short name	T1747
Test name
Test status
Simulation time	65514236620 ps
CPU time	392.75 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:27:12 PM PST 24
Peak memory	284176 kb
Host	smart-510aa144-b4e7-4681-9e9a-423d6b3e6ed3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003563417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_perf.2003563417
Directory	/workspace/15.spi_device_perf/latest

Test location	/workspace/coverage/default/15.spi_device_ram_cfg.2686905155
Short name	T84
Test name
Test status
Simulation time	19058526 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:45 PM PST 24
Peak memory	215748 kb
Host	smart-59e0f5fb-c2f2-4b28-9d98-b6d2ce1cb41f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686905155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2686905155
Directory	/workspace/15.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/15.spi_device_read_buffer_direct.2108562662
Short name	T1313
Test name
Test status
Simulation time	301821819 ps
CPU time	3.19 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	220472 kb
Host	smart-a1c4ef8f-91fd-4120-9be8-68292e3ef99b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2108562662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir ect.2108562662
Directory	/workspace/15.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/15.spi_device_rx_timeout.416333238
Short name	T1158
Test name
Test status
Simulation time	660368167 ps
CPU time	5.41 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:47 PM PST 24
Peak memory	216792 kb
Host	smart-f67ce392-c3bd-4834-9475-b6d21b480fe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416333238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_rx_timeout.416333238
Directory	/workspace/15.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/15.spi_device_smoke.1889787028
Short name	T898
Test name
Test status
Simulation time	78379042 ps
CPU time	1.05 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	216592 kb
Host	smart-575741ac-8a40-4ded-9cec-8226b650975c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889787028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_smoke.1889787028
Directory	/workspace/15.spi_device_smoke/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_all.3180085495
Short name	T1275
Test name
Test status
Simulation time	8737375159 ps
CPU time	48.18 seconds
Started	Jan 07 01:20:37 PM PST 24
Finished	Jan 07 01:21:34 PM PST 24
Peak memory	216944 kb
Host	smart-70a9b393-5c07-4fab-8cde-601784449615
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180085495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3180085495
Directory	/workspace/15.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4036586774
Short name	T1385
Test name
Test status
Simulation time	8259225821 ps
CPU time	22.05 seconds
Started	Jan 07 01:20:45 PM PST 24
Finished	Jan 07 01:21:15 PM PST 24
Peak memory	216876 kb
Host	smart-d132b0a9-370a-4909-96c3-30a57c31cff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036586774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4036586774
Directory	/workspace/15.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_rw.201596332
Short name	T832
Test name
Test status
Simulation time	61125561 ps
CPU time	2.45 seconds
Started	Jan 07 01:20:34 PM PST 24
Finished	Jan 07 01:20:42 PM PST 24
Peak memory	216808 kb
Host	smart-0c0ffa87-e96f-4569-a097-a685a86285b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201596332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.201596332
Directory	/workspace/15.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_sts_read.1670900622
Short name	T808
Test name
Test status
Simulation time	122859422 ps
CPU time	0.98 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:46 PM PST 24
Peak memory	207912 kb
Host	smart-421185d0-7939-4e4b-bdc8-0c18994c900e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670900622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1670900622
Directory	/workspace/15.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/15.spi_device_tx_async_fifo_reset.3788144948
Short name	T1497
Test name
Test status
Simulation time	116925667 ps
CPU time	0.78 seconds
Started	Jan 07 01:20:36 PM PST 24
Finished	Jan 07 01:20:44 PM PST 24
Peak memory	208440 kb
Host	smart-876c1319-37b6-4e97-abb0-5a8e4e59270d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788144948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tx_async_fifo_reset.3788144948
Directory	/workspace/15.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/15.spi_device_txrx.3738839203
Short name	T635
Test name
Test status
Simulation time	19143564041 ps
CPU time	123.1 seconds
Started	Jan 07 01:20:33 PM PST 24
Finished	Jan 07 01:22:41 PM PST 24
Peak memory	256952 kb
Host	smart-c788bd76-fdeb-4831-b58b-1d6bb426bd56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738839203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_txrx.3738839203
Directory	/workspace/15.spi_device_txrx/latest

Test location	/workspace/coverage/default/15.spi_device_upload.1405929257
Short name	T1229
Test name
Test status
Simulation time	35421302256 ps
CPU time	8.68 seconds
Started	Jan 07 01:20:35 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	219508 kb
Host	smart-8f192075-21a4-4109-8150-399db548caff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405929257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1405929257
Directory	/workspace/15.spi_device_upload/latest

Test location	/workspace/coverage/default/16.spi_device_abort.1739432243
Short name	T1569
Test name
Test status
Simulation time	101858335 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	206688 kb
Host	smart-990aff05-7ea5-4cbe-a6cf-ae30622b6eae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739432243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_abort.1739432243
Directory	/workspace/16.spi_device_abort/latest

Test location	/workspace/coverage/default/16.spi_device_alert_test.2606614879
Short name	T1407
Test name
Test status
Simulation time	29864711 ps
CPU time	0.7 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	206452 kb
Host	smart-7932bfd6-2999-45f6-b9c8-02d1d990273f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606614879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 2606614879
Directory	/workspace/16.spi_device_alert_test/latest

Test location	/workspace/coverage/default/16.spi_device_bit_transfer.1722868721
Short name	T806
Test name
Test status
Simulation time	1115598744 ps
CPU time	3 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	216752 kb
Host	smart-0266b709-489b-4269-95ab-363772798907
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722868721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_bit_transfer.1722868721
Directory	/workspace/16.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/16.spi_device_byte_transfer.2424613626
Short name	T1742
Test name
Test status
Simulation time	649050567 ps
CPU time	2.83 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	216912 kb
Host	smart-64afb90e-508b-4dc5-aee6-649442302d18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424613626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_byte_transfer.2424613626
Directory	/workspace/16.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/16.spi_device_cfg_cmd.1759879712
Short name	T1382
Test name
Test status
Simulation time	2834777508 ps
CPU time	10.23 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	225156 kb
Host	smart-0de501b2-ae4e-409b-9863-690e7f7beb34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759879712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1759879712
Directory	/workspace/16.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/16.spi_device_csb_read.3734305515
Short name	T1479
Test name
Test status
Simulation time	34507010 ps
CPU time	0.77 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	207648 kb
Host	smart-bf27fa2e-d1e9-4826-b5ee-d23941dcba33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734305515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3734305515
Directory	/workspace/16.spi_device_csb_read/latest

Test location	/workspace/coverage/default/16.spi_device_dummy_item_extra_dly.1125086167
Short name	T586
Test name
Test status
Simulation time	42642277825 ps
CPU time	626.87 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:31:16 PM PST 24
Peak memory	297916 kb
Host	smart-eeef0074-4676-4bf0-b4ca-d70eb606d9da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125086167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_dummy_item_extra_dly.1125086167
Directory	/workspace/16.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/16.spi_device_extreme_fifo_size.1258186427
Short name	T1436
Test name
Test status
Simulation time	73652979000 ps
CPU time	1032.84 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:38:02 PM PST 24
Peak memory	220864 kb
Host	smart-61b66870-a8ee-42ed-973b-2b1c7aff5909
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258186427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_extreme_fifo_size.1258186427
Directory	/workspace/16.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/16.spi_device_fifo_full.1758448341
Short name	T1144
Test name
Test status
Simulation time	37265406863 ps
CPU time	184.29 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:23:56 PM PST 24
Peak memory	275516 kb
Host	smart-a6b22516-f7ba-47b0-b2fa-fc1678cf356b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758448341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_full.1758448341
Directory	/workspace/16.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/16.spi_device_fifo_underflow_overflow.1657260972
Short name	T1649
Test name
Test status
Simulation time	108826269664 ps
CPU time	596.57 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:30:47 PM PST 24
Peak memory	457796 kb
Host	smart-90ff7a4d-d63c-4c2b-9645-606dcd7696dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657260972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_fifo_underflow_overf low.1657260972
Directory	/workspace/16.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/16.spi_device_flash_all.2903255341
Short name	T231
Test name
Test status
Simulation time	69956116682 ps
CPU time	99.38 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:22:31 PM PST 24
Peak memory	256172 kb
Host	smart-94c5a262-314a-440e-b4ba-0ff290d4521b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903255341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2903255341
Directory	/workspace/16.spi_device_flash_all/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm.2715408926
Short name	T6
Test name
Test status
Simulation time	36254857803 ps
CPU time	226.63 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:24:36 PM PST 24
Peak memory	258024 kb
Host	smart-26fe5940-6c4e-474e-9341-aa55fa4f9fef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715408926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2715408926
Directory	/workspace/16.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3291870339
Short name	T691
Test name
Test status
Simulation time	44280209859 ps
CPU time	269.59 seconds
Started	Jan 07 01:20:45 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	257348 kb
Host	smart-c8fb6fe6-e97c-411a-acb2-0951bfdb1e80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291870339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl e.3291870339
Directory	/workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/16.spi_device_intercept.2499877018
Short name	T1670
Test name
Test status
Simulation time	3872771579 ps
CPU time	4.83 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:55 PM PST 24
Peak memory	240908 kb
Host	smart-12885d50-3e54-493f-9524-3fb218b2cddb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499877018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2499877018
Directory	/workspace/16.spi_device_intercept/latest

Test location	/workspace/coverage/default/16.spi_device_intr.561246677
Short name	T1601
Test name
Test status
Simulation time	162275565883 ps
CPU time	34.42 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:21:26 PM PST 24
Peak memory	240872 kb
Host	smart-a1d3a886-ef1c-4165-b88a-0fad535b7849
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561246677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intr.561246677
Directory	/workspace/16.spi_device_intr/latest

Test location	/workspace/coverage/default/16.spi_device_mailbox.1733912292
Short name	T747
Test name
Test status
Simulation time	159039528 ps
CPU time	2.53 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:54 PM PST 24
Peak memory	218484 kb
Host	smart-a9b023fb-d2e0-4a68-8d3a-ac11c2ab2673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733912292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1733912292
Directory	/workspace/16.spi_device_mailbox/latest

Test location	/workspace/coverage/default/16.spi_device_mem_parity.2639562124
Short name	T1065
Test name
Test status
Simulation time	18041564 ps
CPU time	0.98 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	218740 kb
Host	smart-0ef308b9-5006-49b5-a318-beeeb4ac8b6c
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639562124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.spi_device_mem_parity.2639562124
Directory	/workspace/16.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.348237851
Short name	T729
Test name
Test status
Simulation time	3215960570 ps
CPU time	3.22 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:55 PM PST 24
Peak memory	218292 kb
Host	smart-b6c55aad-8913-450c-8f13-785bebac3bfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348237851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap .348237851
Directory	/workspace/16.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/16.spi_device_pass_cmd_filtering.3524975937
Short name	T862
Test name
Test status
Simulation time	55115168375 ps
CPU time	40.1 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:21:31 PM PST 24
Peak memory	241520 kb
Host	smart-a00eac7d-53e9-46fc-9c38-261040d73f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524975937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3524975937
Directory	/workspace/16.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/16.spi_device_perf.2196945149
Short name	T475
Test name
Test status
Simulation time	9240046216 ps
CPU time	246.96 seconds
Started	Jan 07 01:20:40 PM PST 24
Finished	Jan 07 01:24:56 PM PST 24
Peak memory	302264 kb
Host	smart-95472801-d57d-4c8e-9926-8b8d0ccc0e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196945149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_perf.2196945149
Directory	/workspace/16.spi_device_perf/latest

Test location	/workspace/coverage/default/16.spi_device_ram_cfg.2947331279
Short name	T1017
Test name
Test status
Simulation time	37417493 ps
CPU time	0.7 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	216708 kb
Host	smart-a8d63047-7d76-4940-aafb-7388bc4a12f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947331279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2947331279
Directory	/workspace/16.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/16.spi_device_read_buffer_direct.2462620592
Short name	T1043
Test name
Test status
Simulation time	3955127641 ps
CPU time	8.2 seconds
Started	Jan 07 01:20:45 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	218916 kb
Host	smart-0f4298df-4ee7-467f-bdc6-50b25eb16428
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2462620592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir ect.2462620592
Directory	/workspace/16.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/16.spi_device_rx_async_fifo_reset.1490311290
Short name	T1609
Test name
Test status
Simulation time	64644040 ps
CPU time	0.88 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	208508 kb
Host	smart-171ac04e-5338-4f84-9171-1847ec71b204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490311290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_async_fifo_reset.1490311290
Directory	/workspace/16.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/16.spi_device_rx_timeout.3020709344
Short name	T1426
Test name
Test status
Simulation time	413877988 ps
CPU time	4.8 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:56 PM PST 24
Peak memory	216792 kb
Host	smart-c2605ff6-a26a-46d4-bf92-47db0268e798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020709344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_rx_timeout.3020709344
Directory	/workspace/16.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/16.spi_device_smoke.2807210500
Short name	T1222
Test name
Test status
Simulation time	537547261 ps
CPU time	1.13 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	216584 kb
Host	smart-409744d6-594c-457f-8518-f419133fbb2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807210500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_smoke.2807210500
Directory	/workspace/16.spi_device_smoke/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_all.4143523385
Short name	T1546
Test name
Test status
Simulation time	36017509325 ps
CPU time	60.91 seconds
Started	Jan 07 01:20:40 PM PST 24
Finished	Jan 07 01:21:50 PM PST 24
Peak memory	216876 kb
Host	smart-6243318f-a0d3-4122-8ddd-1581b22f69b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143523385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4143523385
Directory	/workspace/16.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1159989211
Short name	T455
Test name
Test status
Simulation time	3504261818 ps
CPU time	12.34 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:21:02 PM PST 24
Peak memory	216944 kb
Host	smart-c4d9356a-c1bd-41c4-896a-b099c1c309db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159989211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1159989211
Directory	/workspace/16.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_rw.1693270930
Short name	T1719
Test name
Test status
Simulation time	110054386 ps
CPU time	1.54 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	216784 kb
Host	smart-4a1b3795-c252-4f5c-aa0e-869654626f62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693270930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1693270930
Directory	/workspace/16.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_sts_read.2726253729
Short name	T565
Test name
Test status
Simulation time	150679825 ps
CPU time	0.98 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:52 PM PST 24
Peak memory	208392 kb
Host	smart-09edba2e-c3bc-48d6-b01a-a735067901ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726253729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2726253729
Directory	/workspace/16.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/16.spi_device_tx_async_fifo_reset.3730401765
Short name	T1208
Test name
Test status
Simulation time	54184752 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	208500 kb
Host	smart-f1347739-7812-4a39-be2d-dadc09c33d40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730401765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tx_async_fifo_reset.3730401765
Directory	/workspace/16.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/16.spi_device_txrx.101567217
Short name	T819
Test name
Test status
Simulation time	18723034153 ps
CPU time	99.2 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 01:22:28 PM PST 24
Peak memory	258752 kb
Host	smart-2952de9f-ed0c-4863-9469-94ab00a060e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101567217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_txrx.101567217
Directory	/workspace/16.spi_device_txrx/latest

Test location	/workspace/coverage/default/16.spi_device_upload.255590072
Short name	T1178
Test name
Test status
Simulation time	13109545406 ps
CPU time	12.41 seconds
Started	Jan 07 01:20:45 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	228540 kb
Host	smart-e61b25a9-7a1a-4243-8a32-ec5f95e9b03a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255590072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.255590072
Directory	/workspace/16.spi_device_upload/latest

Test location	/workspace/coverage/default/17.spi_device_abort.2088526888
Short name	T1205
Test name
Test status
Simulation time	17529316 ps
CPU time	0.78 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	206672 kb
Host	smart-0988d233-4911-4c66-ac4a-b4605e44aa38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088526888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_abort.2088526888
Directory	/workspace/17.spi_device_abort/latest

Test location	/workspace/coverage/default/17.spi_device_alert_test.2073474683
Short name	T671
Test name
Test status
Simulation time	49253936 ps
CPU time	0.73 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	206456 kb
Host	smart-4d0c8bbb-3e96-47e1-aa16-3dc0cac6ae33
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073474683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 2073474683
Directory	/workspace/17.spi_device_alert_test/latest

Test location	/workspace/coverage/default/17.spi_device_bit_transfer.4214424586
Short name	T1239
Test name
Test status
Simulation time	840254857 ps
CPU time	2.66 seconds
Started	Jan 07 01:20:46 PM PST 24
Finished	Jan 07 01:20:57 PM PST 24
Peak memory	216804 kb
Host	smart-f1875e8a-00ba-4427-84f0-f2a66c101a54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214424586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_bit_transfer.4214424586
Directory	/workspace/17.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/17.spi_device_byte_transfer.2322751565
Short name	T1377
Test name
Test status
Simulation time	843392620 ps
CPU time	3.12 seconds
Started	Jan 07 01:20:46 PM PST 24
Finished	Jan 07 01:20:57 PM PST 24
Peak memory	216740 kb
Host	smart-d75b0d9b-0add-48a0-9251-fd96227e4dfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322751565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_byte_transfer.2322751565
Directory	/workspace/17.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/17.spi_device_cfg_cmd.3023730301
Short name	T1607
Test name
Test status
Simulation time	148126353 ps
CPU time	3.06 seconds
Started	Jan 07 01:20:56 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	218868 kb
Host	smart-6af4d9b5-4c05-4015-a846-7545ddc05f17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023730301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3023730301
Directory	/workspace/17.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/17.spi_device_csb_read.2107023009
Short name	T1111
Test name
Test status
Simulation time	15117122 ps
CPU time	0.77 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	207640 kb
Host	smart-e80bb231-6b29-4a36-9330-8dd01831f37e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107023009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2107023009
Directory	/workspace/17.spi_device_csb_read/latest

Test location	/workspace/coverage/default/17.spi_device_dummy_item_extra_dly.3647357802
Short name	T454
Test name
Test status
Simulation time	122993647482 ps
CPU time	1344.78 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:43:15 PM PST 24
Peak memory	257792 kb
Host	smart-82cee706-fb46-465e-b11a-b293b96c7bd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647357802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_dummy_item_extra_dly.3647357802
Directory	/workspace/17.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/17.spi_device_extreme_fifo_size.3919925466
Short name	T718
Test name
Test status
Simulation time	19698988921 ps
CPU time	206.37 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:24:17 PM PST 24
Peak memory	233384 kb
Host	smart-e89c616e-6f47-4350-81a9-5f108d8fadd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919925466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_extreme_fifo_size.3919925466
Directory	/workspace/17.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/17.spi_device_fifo_full.323510257
Short name	T621
Test name
Test status
Simulation time	102141260661 ps
CPU time	990.79 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:37:22 PM PST 24
Peak memory	319004 kb
Host	smart-66211991-284f-443e-900a-d678ddac2ea5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323510257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_full.323510257
Directory	/workspace/17.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/17.spi_device_fifo_underflow_overflow.1938199004
Short name	T33
Test name
Test status
Simulation time	697628412920 ps
CPU time	1221.46 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:41:13 PM PST 24
Peak memory	688024 kb
Host	smart-5df3d164-a167-48bd-aa0d-5cda33afe010
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938199004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_fifo_underflow_overf low.1938199004
Directory	/workspace/17.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/17.spi_device_flash_and_tpm.3386814050
Short name	T750
Test name
Test status
Simulation time	80589459883 ps
CPU time	168.82 seconds
Started	Jan 07 01:20:56 PM PST 24
Finished	Jan 07 01:23:52 PM PST 24
Peak memory	258008 kb
Host	smart-779796ed-487c-4989-94c4-05b7a9a13a52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386814050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3386814050
Directory	/workspace/17.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/17.spi_device_flash_mode.4196594124
Short name	T785
Test name
Test status
Simulation time	2234285703 ps
CPU time	14.65 seconds
Started	Jan 07 01:20:51 PM PST 24
Finished	Jan 07 01:21:12 PM PST 24
Peak memory	240948 kb
Host	smart-95979351-acf4-4763-bed6-9cc2e7ed225c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196594124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4196594124
Directory	/workspace/17.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/17.spi_device_intercept.3623661834
Short name	T233
Test name
Test status
Simulation time	243007795 ps
CPU time	3.76 seconds
Started	Jan 07 01:20:47 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	234384 kb
Host	smart-659d8a9c-7b59-4bf0-8683-b18e5b5eafa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623661834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3623661834
Directory	/workspace/17.spi_device_intercept/latest

Test location	/workspace/coverage/default/17.spi_device_intr.2909850603
Short name	T1652
Test name
Test status
Simulation time	8613900703 ps
CPU time	36.8 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 01:21:26 PM PST 24
Peak memory	225192 kb
Host	smart-87792ea6-016a-430b-9460-595e935fcb66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909850603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intr.2909850603
Directory	/workspace/17.spi_device_intr/latest

Test location	/workspace/coverage/default/17.spi_device_mailbox.1852775848
Short name	T244
Test name
Test status
Simulation time	4706610059 ps
CPU time	15.19 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:21:06 PM PST 24
Peak memory	253932 kb
Host	smart-6a317f21-d5aa-44ea-9bcb-41db771b15e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852775848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1852775848
Directory	/workspace/17.spi_device_mailbox/latest

Test location	/workspace/coverage/default/17.spi_device_mem_parity.686581097
Short name	T725
Test name
Test status
Simulation time	46448251 ps
CPU time	1.01 seconds
Started	Jan 07 01:20:47 PM PST 24
Finished	Jan 07 01:20:56 PM PST 24
Peak memory	217760 kb
Host	smart-f9dba254-9358-4b2a-ac2d-9f52b752f68c
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686581097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.686581097
Directory	/workspace/17.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.790463565
Short name	T848
Test name
Test status
Simulation time	5078284767 ps
CPU time	11.12 seconds
Started	Jan 07 01:20:46 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	239544 kb
Host	smart-49402fc6-ec89-4b01-9c75-880652807545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790463565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap .790463565
Directory	/workspace/17.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/17.spi_device_pass_cmd_filtering.1291551689
Short name	T1641
Test name
Test status
Simulation time	35720865051 ps
CPU time	26.94 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:21:18 PM PST 24
Peak memory	238444 kb
Host	smart-71c2d8be-c097-4a8d-99e2-be5211bf5d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291551689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1291551689
Directory	/workspace/17.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/17.spi_device_perf.3858611483
Short name	T1289
Test name
Test status
Simulation time	59111989531 ps
CPU time	369.73 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:27:02 PM PST 24
Peak memory	255476 kb
Host	smart-e6405acb-66d1-4682-a2a6-2aca52380932
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858611483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_perf.3858611483
Directory	/workspace/17.spi_device_perf/latest

Test location	/workspace/coverage/default/17.spi_device_ram_cfg.2560953523
Short name	T697
Test name
Test status
Simulation time	23064519 ps
CPU time	0.71 seconds
Started	Jan 07 01:20:47 PM PST 24
Finished	Jan 07 01:20:56 PM PST 24
Peak memory	216732 kb
Host	smart-6843c675-3c82-4aca-88dc-84438b8e90ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560953523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2560953523
Directory	/workspace/17.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/17.spi_device_read_buffer_direct.2495141270
Short name	T1366
Test name
Test status
Simulation time	1853345266 ps
CPU time	7.87 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:21:06 PM PST 24
Peak memory	218584 kb
Host	smart-3d870e6d-fb3b-406d-b1a2-be34efb05b11
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2495141270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir ect.2495141270
Directory	/workspace/17.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/17.spi_device_rx_async_fifo_reset.2741763335
Short name	T73
Test name
Test status
Simulation time	39432171 ps
CPU time	0.87 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	208512 kb
Host	smart-266450ee-e4f1-4002-9987-e7206e817144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741763335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_rx_async_fifo_reset.2741763335
Directory	/workspace/17.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/17.spi_device_smoke.1550871475
Short name	T525
Test name
Test status
Simulation time	130289396 ps
CPU time	1.19 seconds
Started	Jan 07 01:20:41 PM PST 24
Finished	Jan 07 01:20:50 PM PST 24
Peak memory	216600 kb
Host	smart-bdc7845d-53d4-4503-a41d-d5c13dffdfe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550871475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_smoke.1550871475
Directory	/workspace/17.spi_device_smoke/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_all.4211280025
Short name	T336
Test name
Test status
Simulation time	3317655498 ps
CPU time	16.37 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:21:08 PM PST 24
Peak memory	217252 kb
Host	smart-1e47e784-ec11-45eb-a47b-b3bd4c8efbed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211280025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4211280025
Directory	/workspace/17.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4054736587
Short name	T1592
Test name
Test status
Simulation time	15856018577 ps
CPU time	18.39 seconds
Started	Jan 07 01:20:47 PM PST 24
Finished	Jan 07 01:21:13 PM PST 24
Peak memory	216896 kb
Host	smart-f1149085-eaf5-4362-87cc-e39f023915c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054736587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4054736587
Directory	/workspace/17.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_rw.1385480878
Short name	T1484
Test name
Test status
Simulation time	43007596 ps
CPU time	0.75 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	206884 kb
Host	smart-4a07a5e3-73b5-4a40-b6ae-5dd4e48fd88a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385480878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1385480878
Directory	/workspace/17.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_sts_read.3128685439
Short name	T967
Test name
Test status
Simulation time	140319137 ps
CPU time	1.15 seconds
Started	Jan 07 01:20:44 PM PST 24
Finished	Jan 07 01:20:53 PM PST 24
Peak memory	208012 kb
Host	smart-fa984616-b47f-437f-93b4-90e8dc3d6e3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128685439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3128685439
Directory	/workspace/17.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/17.spi_device_tx_async_fifo_reset.1657558105
Short name	T479
Test name
Test status
Simulation time	16511412 ps
CPU time	0.76 seconds
Started	Jan 07 01:20:42 PM PST 24
Finished	Jan 07 01:20:51 PM PST 24
Peak memory	208504 kb
Host	smart-c684f24c-6022-4da5-8a03-6aff4cf72b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657558105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tx_async_fifo_reset.1657558105
Directory	/workspace/17.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/17.spi_device_txrx.3599320477
Short name	T1644
Test name
Test status
Simulation time	86585839119 ps
CPU time	355.55 seconds
Started	Jan 07 01:20:43 PM PST 24
Finished	Jan 07 01:26:47 PM PST 24
Peak memory	301156 kb
Host	smart-08f7009a-288d-4827-bdb2-903872a4a17c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599320477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_txrx.3599320477
Directory	/workspace/17.spi_device_txrx/latest

Test location	/workspace/coverage/default/17.spi_device_upload.3292697950
Short name	T283
Test name
Test status
Simulation time	6652999719 ps
CPU time	20.68 seconds
Started	Jan 07 01:20:51 PM PST 24
Finished	Jan 07 01:21:18 PM PST 24
Peak memory	245472 kb
Host	smart-d67ce362-9bde-43d5-8c62-442cf58f5f21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292697950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3292697950
Directory	/workspace/17.spi_device_upload/latest

Test location	/workspace/coverage/default/18.spi_device_abort.672796442
Short name	T1406
Test name
Test status
Simulation time	39162426 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	206624 kb
Host	smart-d7849360-ddbb-40ab-955e-edd56081fd4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672796442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_abort.672796442
Directory	/workspace/18.spi_device_abort/latest

Test location	/workspace/coverage/default/18.spi_device_alert_test.2122439856
Short name	T1554
Test name
Test status
Simulation time	46546054 ps
CPU time	0.71 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	206440 kb
Host	smart-7ebb8528-594e-4108-8c80-5428f03f9b7e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122439856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test. 2122439856
Directory	/workspace/18.spi_device_alert_test/latest

Test location	/workspace/coverage/default/18.spi_device_bit_transfer.1782134243
Short name	T652
Test name
Test status
Simulation time	74130718 ps
CPU time	2.3 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:21:03 PM PST 24
Peak memory	216748 kb
Host	smart-c059b9cf-6019-47ba-ac19-8ef17720f76b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782134243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_bit_transfer.1782134243
Directory	/workspace/18.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/18.spi_device_byte_transfer.755065491
Short name	T1663
Test name
Test status
Simulation time	147176904 ps
CPU time	2.51 seconds
Started	Jan 07 01:20:56 PM PST 24
Finished	Jan 07 01:21:06 PM PST 24
Peak memory	216864 kb
Host	smart-87d7c2e2-48b8-44b1-8033-c62179681bb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755065491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_byte_transfer.755065491
Directory	/workspace/18.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/18.spi_device_csb_read.914591554
Short name	T1556
Test name
Test status
Simulation time	20745559 ps
CPU time	0.74 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	207436 kb
Host	smart-a7ccc73f-10f3-4ccf-8568-47d2e3e4dfe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914591554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.914591554
Directory	/workspace/18.spi_device_csb_read/latest

Test location	/workspace/coverage/default/18.spi_device_extreme_fifo_size.1598329136
Short name	T553
Test name
Test status
Simulation time	415379528806 ps
CPU time	1988.53 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:54:07 PM PST 24
Peak memory	218116 kb
Host	smart-ff6d8aac-c143-4915-acfa-9fbee54cfa9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598329136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_extreme_fifo_size.1598329136
Directory	/workspace/18.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/18.spi_device_fifo_full.314602789
Short name	T1588
Test name
Test status
Simulation time	28756492469 ps
CPU time	1495.78 seconds
Started	Jan 07 01:20:50 PM PST 24
Finished	Jan 07 01:45:53 PM PST 24
Peak memory	303088 kb
Host	smart-a5e5c141-52cc-4e97-bae4-8ecd73fc43b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=314602789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_full.314602789
Directory	/workspace/18.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/18.spi_device_fifo_underflow_overflow.2668224756
Short name	T1210
Test name
Test status
Simulation time	140466631601 ps
CPU time	347.88 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:26:46 PM PST 24
Peak memory	355856 kb
Host	smart-40871fa4-215e-4e1c-8b6a-129baa316489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668224756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_fifo_underflow_overf low.2668224756
Directory	/workspace/18.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/18.spi_device_flash_all.2439261157
Short name	T715
Test name
Test status
Simulation time	20845069916 ps
CPU time	113.73 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	253880 kb
Host	smart-c19c48e7-dced-4ecb-865f-622f7d8e0c22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439261157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2439261157
Directory	/workspace/18.spi_device_flash_all/latest

Test location	/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3128999001
Short name	T1658
Test name
Test status
Simulation time	50457154794 ps
CPU time	222.56 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:24:44 PM PST 24
Peak memory	253388 kb
Host	smart-d1615d84-fc30-4092-be00-8142fd942b1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128999001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl e.3128999001
Directory	/workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/18.spi_device_flash_mode.1291232826
Short name	T815
Test name
Test status
Simulation time	2911416851 ps
CPU time	15.94 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:16 PM PST 24
Peak memory	254948 kb
Host	smart-54c6181b-21ad-42e7-b0a7-5a0ca7176625
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291232826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1291232826
Directory	/workspace/18.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/18.spi_device_intercept.1946952707
Short name	T654
Test name
Test status
Simulation time	393318300 ps
CPU time	2.93 seconds
Started	Jan 07 01:20:50 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	225076 kb
Host	smart-382ff734-80cc-4777-aac2-020f85cdb98c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946952707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1946952707
Directory	/workspace/18.spi_device_intercept/latest

Test location	/workspace/coverage/default/18.spi_device_intr.481711689
Short name	T1184
Test name
Test status
Simulation time	5184960998 ps
CPU time	22.01 seconds
Started	Jan 07 01:20:57 PM PST 24
Finished	Jan 07 01:21:26 PM PST 24
Peak memory	219304 kb
Host	smart-313431c5-5e28-4e71-91d2-4e1d1da2894a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481711689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intr.481711689
Directory	/workspace/18.spi_device_intr/latest

Test location	/workspace/coverage/default/18.spi_device_mailbox.1210857468
Short name	T1063
Test name
Test status
Simulation time	843868607 ps
CPU time	12.75 seconds
Started	Jan 07 01:20:57 PM PST 24
Finished	Jan 07 01:21:17 PM PST 24
Peak memory	240260 kb
Host	smart-822be396-89b1-433e-ba11-fad814211aaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210857468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1210857468
Directory	/workspace/18.spi_device_mailbox/latest

Test location	/workspace/coverage/default/18.spi_device_mem_parity.3575128398
Short name	T1086
Test name
Test status
Simulation time	27531182 ps
CPU time	1.08 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:01 PM PST 24
Peak memory	218740 kb
Host	smart-20cf6f9e-19ec-4650-8be7-145e2a092e11
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575128398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.spi_device_mem_parity.3575128398
Directory	/workspace/18.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.235095231
Short name	T247
Test name
Test status
Simulation time	16535276624 ps
CPU time	24.8 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:21:23 PM PST 24
Peak memory	230700 kb
Host	smart-1d01c5b7-6ac5-48b4-856a-046e75e1b0c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235095231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap .235095231
Directory	/workspace/18.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/18.spi_device_pass_cmd_filtering.1096047980
Short name	T1448
Test name
Test status
Simulation time	490242790 ps
CPU time	7.68 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:08 PM PST 24
Peak memory	233148 kb
Host	smart-ec5633c5-b299-488e-95d8-48ed4efed8dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096047980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1096047980
Directory	/workspace/18.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/18.spi_device_perf.2083661424
Short name	T459
Test name
Test status
Simulation time	33272402616 ps
CPU time	275.21 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:25:34 PM PST 24
Peak memory	284152 kb
Host	smart-ce82537b-e67b-45db-86f5-3c415b96974d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083661424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_perf.2083661424
Directory	/workspace/18.spi_device_perf/latest

Test location	/workspace/coverage/default/18.spi_device_ram_cfg.240886644
Short name	T1083
Test name
Test status
Simulation time	40529842 ps
CPU time	0.71 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	216688 kb
Host	smart-b614a479-54c3-4f5a-aa09-46a2fc3fe63b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240886644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.240886644
Directory	/workspace/18.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/18.spi_device_read_buffer_direct.1156948971
Short name	T1209
Test name
Test status
Simulation time	2453564611 ps
CPU time	5.77 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:21:06 PM PST 24
Peak memory	234568 kb
Host	smart-d420565e-436a-4ec4-a63a-22a9aef6e5ff
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1156948971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.1156948971
Directory	/workspace/18.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/18.spi_device_rx_async_fifo_reset.653951513
Short name	T124
Test name
Test status
Simulation time	894166361 ps
CPU time	0.93 seconds
Started	Jan 07 01:20:56 PM PST 24
Finished	Jan 07 01:21:03 PM PST 24
Peak memory	208272 kb
Host	smart-0b1359e9-2d11-41ca-97c1-fd8dc52b78bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653951513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_async_fifo_reset.653951513
Directory	/workspace/18.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/18.spi_device_rx_timeout.3439243287
Short name	T643
Test name
Test status
Simulation time	1249585158 ps
CPU time	5.87 seconds
Started	Jan 07 01:20:51 PM PST 24
Finished	Jan 07 01:21:03 PM PST 24
Peak memory	216788 kb
Host	smart-c13a0681-022a-49f7-81ef-7099a71ece57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439243287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_rx_timeout.3439243287
Directory	/workspace/18.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/18.spi_device_smoke.4094905598
Short name	T1684
Test name
Test status
Simulation time	32480842 ps
CPU time	1.21 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:21:00 PM PST 24
Peak memory	216824 kb
Host	smart-48fcf8da-fb14-4425-be70-ad5fe9514043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094905598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_smoke.4094905598
Directory	/workspace/18.spi_device_smoke/latest

Test location	/workspace/coverage/default/18.spi_device_stress_all.3003395038
Short name	T185
Test name
Test status
Simulation time	73667345026 ps
CPU time	1010.81 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:37:52 PM PST 24
Peak memory	550472 kb
Host	smart-f1aab48f-a052-45aa-adce-95b29cc0c911
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003395038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre ss_all.3003395038
Directory	/workspace/18.spi_device_stress_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_all.3920081600
Short name	T1343
Test name
Test status
Simulation time	2887451839 ps
CPU time	42.24 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:21:44 PM PST 24
Peak memory	217072 kb
Host	smart-be7a08d9-7238-43c9-a47c-1b96b4c2fd1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920081600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3920081600
Directory	/workspace/18.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1763901834
Short name	T480
Test name
Test status
Simulation time	3832852264 ps
CPU time	2.7 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:21:01 PM PST 24
Peak memory	216604 kb
Host	smart-54437f89-20e2-481e-b46a-78be45dea47c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763901834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1763901834
Directory	/workspace/18.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_rw.2595901497
Short name	T345
Test name
Test status
Simulation time	252616611 ps
CPU time	6.61 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	216860 kb
Host	smart-dc521f00-cb81-4cbd-b218-2713cb809050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595901497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2595901497
Directory	/workspace/18.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_sts_read.2756562237
Short name	T706
Test name
Test status
Simulation time	563318775 ps
CPU time	1.03 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	208056 kb
Host	smart-d8b5d62e-3407-4787-b621-64b67a6c7e9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756562237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2756562237
Directory	/workspace/18.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/18.spi_device_tx_async_fifo_reset.1994235726
Short name	T520
Test name
Test status
Simulation time	57632076 ps
CPU time	0.78 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:21:02 PM PST 24
Peak memory	208300 kb
Host	smart-cbad5476-48cc-4254-b16c-dc4956d285c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994235726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tx_async_fifo_reset.1994235726
Directory	/workspace/18.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/18.spi_device_txrx.3856131313
Short name	T811
Test name
Test status
Simulation time	82369088433 ps
CPU time	326.09 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:26:28 PM PST 24
Peak memory	299644 kb
Host	smart-f8874d94-c407-422d-a6f7-b7011ab48b96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856131313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_txrx.3856131313
Directory	/workspace/18.spi_device_txrx/latest

Test location	/workspace/coverage/default/18.spi_device_upload.2988121816
Short name	T285
Test name
Test status
Simulation time	4828223087 ps
CPU time	18.58 seconds
Started	Jan 07 01:20:53 PM PST 24
Finished	Jan 07 01:21:18 PM PST 24
Peak memory	228204 kb
Host	smart-89afdb01-39d0-450a-9dab-4267c7c281e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988121816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2988121816
Directory	/workspace/18.spi_device_upload/latest

Test location	/workspace/coverage/default/19.spi_device_abort.829097925
Short name	T434
Test name
Test status
Simulation time	21654986 ps
CPU time	0.73 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:21:37 PM PST 24
Peak memory	206584 kb
Host	smart-31cfd30b-5856-484c-b1b9-a92bc569cffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=829097925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_abort.829097925
Directory	/workspace/19.spi_device_abort/latest

Test location	/workspace/coverage/default/19.spi_device_alert_test.1809256533
Short name	T522
Test name
Test status
Simulation time	49215309 ps
CPU time	0.72 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:28 PM PST 24
Peak memory	206576 kb
Host	smart-aabc8fa9-b42b-409b-aa69-a188405c603e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809256533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test. 1809256533
Directory	/workspace/19.spi_device_alert_test/latest

Test location	/workspace/coverage/default/19.spi_device_bit_transfer.1841549822
Short name	T1161
Test name
Test status
Simulation time	126959922 ps
CPU time	2.62 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:29 PM PST 24
Peak memory	216712 kb
Host	smart-683e9ad7-1265-4828-b467-d7cad83663db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841549822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_bit_transfer.1841549822
Directory	/workspace/19.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/19.spi_device_byte_transfer.16791571
Short name	T47
Test name
Test status
Simulation time	700845439 ps
CPU time	3.28 seconds
Started	Jan 07 01:21:51 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	216828 kb
Host	smart-a2bc1538-a693-4dcc-a2e1-cb304d18ade9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16791571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_byte_transfer.16791571
Directory	/workspace/19.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/19.spi_device_csb_read.3574323160
Short name	T1207
Test name
Test status
Simulation time	63295730 ps
CPU time	0.77 seconds
Started	Jan 07 01:21:24 PM PST 24
Finished	Jan 07 01:21:26 PM PST 24
Peak memory	206512 kb
Host	smart-159bf7e0-b88c-4865-a068-ce566b047e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574323160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3574323160
Directory	/workspace/19.spi_device_csb_read/latest

Test location	/workspace/coverage/default/19.spi_device_dummy_item_extra_dly.3230177214
Short name	T1531
Test name
Test status
Simulation time	112028609682 ps
CPU time	952.01 seconds
Started	Jan 07 01:20:52 PM PST 24
Finished	Jan 07 01:36:51 PM PST 24
Peak memory	266964 kb
Host	smart-6e82324c-ce30-49cc-9ee0-ce87ec4f2f35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230177214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_dummy_item_extra_dly.3230177214
Directory	/workspace/19.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/19.spi_device_extreme_fifo_size.2779944518
Short name	T1664
Test name
Test status
Simulation time	188841856067 ps
CPU time	2184.3 seconds
Started	Jan 07 01:20:54 PM PST 24
Finished	Jan 07 01:57:24 PM PST 24
Peak memory	219064 kb
Host	smart-de1267b5-e5ff-4d34-9aa1-24548c84de9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779944518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_extreme_fifo_size.2779944518
Directory	/workspace/19.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/19.spi_device_fifo_full.3363976487
Short name	T1358
Test name
Test status
Simulation time	22406214653 ps
CPU time	413.4 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:27:55 PM PST 24
Peak memory	307756 kb
Host	smart-f463297a-725e-43a5-887f-b3ffc6810e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363976487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_full.3363976487
Directory	/workspace/19.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/19.spi_device_fifo_underflow_overflow.3097101104
Short name	T1696
Test name
Test status
Simulation time	1160573425085 ps
CPU time	1284.17 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:42:26 PM PST 24
Peak memory	635652 kb
Host	smart-2ba98e4b-ee11-41ff-9993-0d080ebfeb45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097101104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_fifo_underflow_overf low.3097101104
Directory	/workspace/19.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/19.spi_device_flash_all.2254072864
Short name	T228
Test name
Test status
Simulation time	279113800904 ps
CPU time	363.59 seconds
Started	Jan 07 01:21:17 PM PST 24
Finished	Jan 07 01:27:23 PM PST 24
Peak memory	269628 kb
Host	smart-1758c594-7a9e-446d-b2ee-e08fb9983d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254072864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2254072864
Directory	/workspace/19.spi_device_flash_all/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm.3201753926
Short name	T28
Test name
Test status
Simulation time	5448258508 ps
CPU time	11.62 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:22:19 PM PST 24
Peak memory	237744 kb
Host	smart-00e8560f-dfc8-40f6-a89b-38e63553c930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201753926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3201753926
Directory	/workspace/19.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3302739367
Short name	T1361
Test name
Test status
Simulation time	6242624951 ps
CPU time	13.02 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:41 PM PST 24
Peak memory	249732 kb
Host	smart-3a1018ce-89fc-4298-8f39-6fd16805bf03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302739367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl e.3302739367
Directory	/workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/19.spi_device_flash_mode.3567446953
Short name	T656
Test name
Test status
Simulation time	2170765985 ps
CPU time	15.98 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	233096 kb
Host	smart-3ba3df6e-9f23-4bf8-beab-8d17dfea31dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567446953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3567446953
Directory	/workspace/19.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/19.spi_device_intercept.3582928026
Short name	T250
Test name
Test status
Simulation time	1039039898 ps
CPU time	7.79 seconds
Started	Jan 07 01:21:19 PM PST 24
Finished	Jan 07 01:21:29 PM PST 24
Peak memory	225076 kb
Host	smart-ec8f7710-1c88-42ec-9531-c7b8761b7c0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582928026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3582928026
Directory	/workspace/19.spi_device_intercept/latest

Test location	/workspace/coverage/default/19.spi_device_intr.1810514115
Short name	T181
Test name
Test status
Simulation time	23776927076 ps
CPU time	33.99 seconds
Started	Jan 07 01:21:27 PM PST 24
Finished	Jan 07 01:22:04 PM PST 24
Peak memory	233304 kb
Host	smart-893eb1b3-3109-4314-9e1d-5489093bc72e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810514115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intr.1810514115
Directory	/workspace/19.spi_device_intr/latest

Test location	/workspace/coverage/default/19.spi_device_mailbox.480598265
Short name	T977
Test name
Test status
Simulation time	164964884 ps
CPU time	3.99 seconds
Started	Jan 07 01:21:17 PM PST 24
Finished	Jan 07 01:21:23 PM PST 24
Peak memory	241424 kb
Host	smart-ccb42aa7-2181-4dfd-ac88-570c7ae49ae0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480598265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.480598265
Directory	/workspace/19.spi_device_mailbox/latest

Test location	/workspace/coverage/default/19.spi_device_mem_parity.3243886027
Short name	T1334
Test name
Test status
Simulation time	24797815 ps
CPU time	1.06 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:10 PM PST 24
Peak memory	218844 kb
Host	smart-63ea5456-d4ae-42c9-8bab-d383f1278985
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243886027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.spi_device_mem_parity.3243886027
Directory	/workspace/19.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3786635631
Short name	T1502
Test name
Test status
Simulation time	9519083028 ps
CPU time	19.5 seconds
Started	Jan 07 01:21:18 PM PST 24
Finished	Jan 07 01:21:39 PM PST 24
Peak memory	228996 kb
Host	smart-980e7f9d-d80e-4151-ae54-7e21ee3be915
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786635631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa p.3786635631
Directory	/workspace/19.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/19.spi_device_pass_cmd_filtering.503586339
Short name	T1003
Test name
Test status
Simulation time	234445600 ps
CPU time	4.88 seconds
Started	Jan 07 01:21:28 PM PST 24
Finished	Jan 07 01:21:36 PM PST 24
Peak memory	218096 kb
Host	smart-69eda341-f6f7-4345-a474-862cbf49a585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503586339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.503586339
Directory	/workspace/19.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/19.spi_device_perf.1017499779
Short name	T1234
Test name
Test status
Simulation time	9399690201 ps
CPU time	281.09 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:26:54 PM PST 24
Peak memory	256548 kb
Host	smart-6a20a670-d616-4177-a5ba-2af5e3a8db5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017499779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_perf.1017499779
Directory	/workspace/19.spi_device_perf/latest

Test location	/workspace/coverage/default/19.spi_device_ram_cfg.3177841406
Short name	T1052
Test name
Test status
Simulation time	43166114 ps
CPU time	0.7 seconds
Started	Jan 07 01:21:16 PM PST 24
Finished	Jan 07 01:21:18 PM PST 24
Peak memory	216540 kb
Host	smart-908841ba-b414-438b-a3b7-384210e9217b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177841406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3177841406
Directory	/workspace/19.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/19.spi_device_read_buffer_direct.3025590483
Short name	T927
Test name
Test status
Simulation time	759243020 ps
CPU time	4 seconds
Started	Jan 07 01:21:51 PM PST 24
Finished	Jan 07 01:21:58 PM PST 24
Peak memory	235416 kb
Host	smart-7023e841-368a-4f3c-9049-45b567708aed
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3025590483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir ect.3025590483
Directory	/workspace/19.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/19.spi_device_rx_timeout.3468868453
Short name	T1399
Test name
Test status
Simulation time	3633242245 ps
CPU time	6.77 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:34 PM PST 24
Peak memory	216896 kb
Host	smart-bbba16cd-96da-4818-8855-6002cb24bfb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468868453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_rx_timeout.3468868453
Directory	/workspace/19.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/19.spi_device_smoke.833279732
Short name	T757
Test name
Test status
Simulation time	356610959 ps
CPU time	1.18 seconds
Started	Jan 07 01:20:55 PM PST 24
Finished	Jan 07 01:21:02 PM PST 24
Peak memory	216820 kb
Host	smart-e7436116-a104-4d4d-bf02-b66a8a97ac82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833279732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_smoke.833279732
Directory	/workspace/19.spi_device_smoke/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_all.4230383592
Short name	T337
Test name
Test status
Simulation time	45380305110 ps
CPU time	197.93 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:24:55 PM PST 24
Peak memory	216948 kb
Host	smart-9f0ed4ee-b40b-46b4-86e1-d3114b52db8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230383592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4230383592
Directory	/workspace/19.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.405245532
Short name	T1176
Test name
Test status
Simulation time	3836791226 ps
CPU time	8.63 seconds
Started	Jan 07 01:21:18 PM PST 24
Finished	Jan 07 01:21:28 PM PST 24
Peak memory	216892 kb
Host	smart-6b827260-d9a4-4a62-849f-2272a0b90b1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405245532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.405245532
Directory	/workspace/19.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_rw.1761313270
Short name	T1508
Test name
Test status
Simulation time	171840134 ps
CPU time	2.52 seconds
Started	Jan 07 01:21:17 PM PST 24
Finished	Jan 07 01:21:21 PM PST 24
Peak memory	216640 kb
Host	smart-1c7c86d2-7e7f-41db-8cf0-c5768a1dda92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761313270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1761313270
Directory	/workspace/19.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_sts_read.2346569679
Short name	T1290
Test name
Test status
Simulation time	67029715 ps
CPU time	0.93 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:11 PM PST 24
Peak memory	208032 kb
Host	smart-738d6718-9baf-4f03-851d-061627034b15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346569679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2346569679
Directory	/workspace/19.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/19.spi_device_tx_async_fifo_reset.2246073843
Short name	T939
Test name
Test status
Simulation time	128887129 ps
CPU time	0.75 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:22:08 PM PST 24
Peak memory	208460 kb
Host	smart-cc4ab87e-a8c9-4494-ac36-06e6649135b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246073843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tx_async_fifo_reset.2246073843
Directory	/workspace/19.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/19.spi_device_txrx.4206353661
Short name	T51
Test name
Test status
Simulation time	350722403986 ps
CPU time	782.59 seconds
Started	Jan 07 01:20:51 PM PST 24
Finished	Jan 07 01:34:00 PM PST 24
Peak memory	268220 kb
Host	smart-bbbefc4e-ad9d-4490-ac62-6dd6507dc026
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206353661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_txrx.4206353661
Directory	/workspace/19.spi_device_txrx/latest

Test location	/workspace/coverage/default/19.spi_device_upload.1332241067
Short name	T275
Test name
Test status
Simulation time	1256428089 ps
CPU time	12.18 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:22 PM PST 24
Peak memory	254724 kb
Host	smart-af2c8dd9-cdb5-4d62-996a-39ab4027e5fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332241067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1332241067
Directory	/workspace/19.spi_device_upload/latest

Test location	/workspace/coverage/default/2.spi_device_abort.1916323876
Short name	T1408
Test name
Test status
Simulation time	50446119 ps
CPU time	0.72 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:18:45 PM PST 24
Peak memory	206640 kb
Host	smart-b04f3332-30e8-4d3e-9204-df6c819391cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916323876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_abort.1916323876
Directory	/workspace/2.spi_device_abort/latest

Test location	/workspace/coverage/default/2.spi_device_alert_test.116438510
Short name	T1006
Test name
Test status
Simulation time	21733475 ps
CPU time	0.73 seconds
Started	Jan 07 01:19:13 PM PST 24
Finished	Jan 07 01:19:18 PM PST 24
Peak memory	206520 kb
Host	smart-925a76d7-2159-4b5f-a226-5637498dfe89
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116438510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.116438510
Directory	/workspace/2.spi_device_alert_test/latest

Test location	/workspace/coverage/default/2.spi_device_byte_transfer.711607710
Short name	T431
Test name
Test status
Simulation time	117033425 ps
CPU time	2.95 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:18:36 PM PST 24
Peak memory	216828 kb
Host	smart-b9973ab4-c3e9-445f-a83d-2f7a443d3eba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711607710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_byte_transfer.711607710
Directory	/workspace/2.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/2.spi_device_cfg_cmd.2862860426
Short name	T1177
Test name
Test status
Simulation time	777563590 ps
CPU time	4.05 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:44 PM PST 24
Peak memory	221908 kb
Host	smart-047447f7-ff80-4d91-9739-ba8415c2a75b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862860426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2862860426
Directory	/workspace/2.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/2.spi_device_csb_read.864536816
Short name	T567
Test name
Test status
Simulation time	23477316 ps
CPU time	0.81 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:18:34 PM PST 24
Peak memory	207540 kb
Host	smart-366bf308-e17b-4c77-877d-fac47f95a307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864536816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.864536816
Directory	/workspace/2.spi_device_csb_read/latest

Test location	/workspace/coverage/default/2.spi_device_dummy_item_extra_dly.4246153230
Short name	T689
Test name
Test status
Simulation time	56125072687 ps
CPU time	508.68 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:27:05 PM PST 24
Peak memory	248964 kb
Host	smart-4eebca72-1f4d-4cbb-9e5d-c99f8b9e0b7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246153230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_dummy_item_extra_dly.4246153230
Directory	/workspace/2.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/2.spi_device_fifo_full.2810483575
Short name	T1560
Test name
Test status
Simulation time	33583388559 ps
CPU time	1712.96 seconds
Started	Jan 07 01:18:33 PM PST 24
Finished	Jan 07 01:47:10 PM PST 24
Peak memory	315076 kb
Host	smart-f9a5e499-a030-457e-9ca2-9eeca93cc3af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2810483575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_full.2810483575
Directory	/workspace/2.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/2.spi_device_fifo_underflow_overflow.4226286327
Short name	T1134
Test name
Test status
Simulation time	37173540434 ps
CPU time	357.81 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:24:34 PM PST 24
Peak memory	465064 kb
Host	smart-0736b366-c773-4490-a4ea-5ff5c1dca3b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226286327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_fifo_underflow_overfl ow.4226286327
Directory	/workspace/2.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/2.spi_device_flash_all.957000961
Short name	T1429
Test name
Test status
Simulation time	3413672392 ps
CPU time	34.76 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:19:14 PM PST 24
Peak memory	257532 kb
Host	smart-2db41ed1-7358-42a3-ad5b-be62c6a0c153
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957000961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.957000961
Directory	/workspace/2.spi_device_flash_all/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm.1950488524
Short name	T238
Test name
Test status
Simulation time	28648691865 ps
CPU time	44.39 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:19:23 PM PST 24
Peak memory	251700 kb
Host	smart-18db4d58-76b4-470a-9662-f102b957e47c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950488524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1950488524
Directory	/workspace/2.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2523521391
Short name	T338
Test name
Test status
Simulation time	77329767392 ps
CPU time	279.76 seconds
Started	Jan 07 01:18:29 PM PST 24
Finished	Jan 07 01:23:12 PM PST 24
Peak memory	263124 kb
Host	smart-602a3513-637b-43a0-9ee2-d29cf009ade1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523521391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle .2523521391
Directory	/workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/2.spi_device_flash_mode.1571502168
Short name	T800
Test name
Test status
Simulation time	38455502983 ps
CPU time	31.38 seconds
Started	Jan 07 01:18:31 PM PST 24
Finished	Jan 07 01:19:05 PM PST 24
Peak memory	249108 kb
Host	smart-d5fa1b6e-c305-4c9d-bd54-f0713cd8b71b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571502168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1571502168
Directory	/workspace/2.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/2.spi_device_intercept.2031013182
Short name	T41
Test name
Test status
Simulation time	1029896292 ps
CPU time	3.4 seconds
Started	Jan 07 01:18:35 PM PST 24
Finished	Jan 07 01:18:44 PM PST 24
Peak memory	225876 kb
Host	smart-cb6eb53e-5812-4711-8bd3-8aace88596aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031013182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2031013182
Directory	/workspace/2.spi_device_intercept/latest

Test location	/workspace/coverage/default/2.spi_device_intr.1431075251
Short name	T614
Test name
Test status
Simulation time	2546958712 ps
CPU time	7.01 seconds
Started	Jan 07 01:18:43 PM PST 24
Finished	Jan 07 01:18:53 PM PST 24
Peak memory	218008 kb
Host	smart-e9ebd030-5eb8-4277-91db-a3352049b4fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431075251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intr.1431075251
Directory	/workspace/2.spi_device_intr/latest

Test location	/workspace/coverage/default/2.spi_device_mailbox.1138977310
Short name	T271
Test name
Test status
Simulation time	341334052 ps
CPU time	6.39 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:18:46 PM PST 24
Peak memory	221264 kb
Host	smart-ac7505e0-945b-4fcf-b047-a8a3e6cce642
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1138977310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1138977310
Directory	/workspace/2.spi_device_mailbox/latest

Test location	/workspace/coverage/default/2.spi_device_mem_parity.2462274636
Short name	T974
Test name
Test status
Simulation time	27377665 ps
CPU time	1.06 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:18:34 PM PST 24
Peak memory	218816 kb
Host	smart-c6ff485e-8aa4-4cb0-b752-c8eedb5ffd18
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462274636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.spi_device_mem_parity.2462274636
Directory	/workspace/2.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2671243802
Short name	T999
Test name
Test status
Simulation time	34227892201 ps
CPU time	26.2 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:19:02 PM PST 24
Peak memory	229088 kb
Host	smart-2c532a7d-20d8-4d0c-90bf-60c99da57610
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671243802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap .2671243802
Directory	/workspace/2.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/2.spi_device_pass_cmd_filtering.1431510504
Short name	T735
Test name
Test status
Simulation time	1254068026 ps
CPU time	6.28 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:18:45 PM PST 24
Peak memory	224900 kb
Host	smart-72614156-3cb5-4319-8804-d1b4fb1753ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431510504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1431510504
Directory	/workspace/2.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/2.spi_device_perf.2125172539
Short name	T1117
Test name
Test status
Simulation time	12381313072 ps
CPU time	802.75 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:32:07 PM PST 24
Peak memory	255448 kb
Host	smart-14ff739a-d2af-4185-bd63-8f943f1a3118
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125172539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_perf.2125172539
Directory	/workspace/2.spi_device_perf/latest

Test location	/workspace/coverage/default/2.spi_device_ram_cfg.1470137428
Short name	T623
Test name
Test status
Simulation time	17836270 ps
CPU time	0.75 seconds
Started	Jan 07 01:18:43 PM PST 24
Finished	Jan 07 01:18:47 PM PST 24
Peak memory	216724 kb
Host	smart-eb6343f2-6e99-42db-b137-22c4e39e1a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470137428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.1470137428
Directory	/workspace/2.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/2.spi_device_read_buffer_direct.709094799
Short name	T1563
Test name
Test status
Simulation time	94103461 ps
CPU time	3.39 seconds
Started	Jan 07 01:18:31 PM PST 24
Finished	Jan 07 01:18:37 PM PST 24
Peak memory	219300 kb
Host	smart-decf097a-5ee6-4149-8088-f70ce8efcdbe
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=709094799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc t.709094799
Directory	/workspace/2.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/2.spi_device_rx_async_fifo_reset.2621556273
Short name	T1553
Test name
Test status
Simulation time	315672317 ps
CPU time	0.89 seconds
Started	Jan 07 01:18:31 PM PST 24
Finished	Jan 07 01:18:35 PM PST 24
Peak memory	208444 kb
Host	smart-ed293115-946e-4446-af55-934e73809ba5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621556273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_async_fifo_reset.2621556273
Directory	/workspace/2.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/2.spi_device_rx_timeout.2061595436
Short name	T908
Test name
Test status
Simulation time	657114478 ps
CPU time	5.6 seconds
Started	Jan 07 01:18:29 PM PST 24
Finished	Jan 07 01:18:37 PM PST 24
Peak memory	216840 kb
Host	smart-4cd9bad8-520e-42a1-b570-4b3aa2f17755
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061595436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_rx_timeout.2061595436
Directory	/workspace/2.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/2.spi_device_sec_cm.460203416
Short name	T91
Test name
Test status
Simulation time	318502704 ps
CPU time	1.25 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:19:13 PM PST 24
Peak memory	238148 kb
Host	smart-6e1492df-b366-4d55-a312-535206962dd6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460203416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.460203416
Directory	/workspace/2.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/2.spi_device_smoke.3218969608
Short name	T1600
Test name
Test status
Simulation time	132567347 ps
CPU time	0.98 seconds
Started	Jan 07 01:18:42 PM PST 24
Finished	Jan 07 01:18:45 PM PST 24
Peak memory	208032 kb
Host	smart-94ca3226-08cb-45c5-bc11-5c420b1348fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218969608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_smoke.3218969608
Directory	/workspace/2.spi_device_smoke/latest

Test location	/workspace/coverage/default/2.spi_device_stress_all.2894564769
Short name	T1416
Test name
Test status
Simulation time	1333928811425 ps
CPU time	1668.21 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:47:16 PM PST 24
Peak memory	344184 kb
Host	smart-8ff2462c-9c25-485c-aeb3-aebdb644f1f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894564769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres s_all.2894564769
Directory	/workspace/2.spi_device_stress_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_all.3826160701
Short name	T527
Test name
Test status
Simulation time	12734149364 ps
CPU time	96.12 seconds
Started	Jan 07 01:18:30 PM PST 24
Finished	Jan 07 01:20:09 PM PST 24
Peak memory	217020 kb
Host	smart-14d60a07-6f81-4640-b622-4cbfcb62fa22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826160701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3826160701
Directory	/workspace/2.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2994364847
Short name	T494
Test name
Test status
Simulation time	1446649338 ps
CPU time	3.29 seconds
Started	Jan 07 01:18:33 PM PST 24
Finished	Jan 07 01:18:40 PM PST 24
Peak memory	216728 kb
Host	smart-147d78fd-b03a-4a08-808e-13e67e88db86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994364847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2994364847
Directory	/workspace/2.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_rw.1926371116
Short name	T917
Test name
Test status
Simulation time	57720947 ps
CPU time	1.78 seconds
Started	Jan 07 01:18:34 PM PST 24
Finished	Jan 07 01:18:40 PM PST 24
Peak memory	216788 kb
Host	smart-b7a3a8e1-119f-4343-9e01-224145aa29d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926371116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1926371116
Directory	/workspace/2.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_sts_read.1920875629
Short name	T882
Test name
Test status
Simulation time	29100772 ps
CPU time	0.76 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:18:37 PM PST 24
Peak memory	206912 kb
Host	smart-ef703dee-1600-4926-aa84-4fd64a7b8ccf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920875629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1920875629
Directory	/workspace/2.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/2.spi_device_tx_async_fifo_reset.2737071996
Short name	T755
Test name
Test status
Simulation time	201005382 ps
CPU time	0.76 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:18:35 PM PST 24
Peak memory	208404 kb
Host	smart-8691c8bd-05df-42bb-b5b7-e70cfb1396b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737071996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tx_async_fifo_reset.2737071996
Directory	/workspace/2.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/2.spi_device_txrx.1919649803
Short name	T1364
Test name
Test status
Simulation time	115027213765 ps
CPU time	450.74 seconds
Started	Jan 07 01:18:33 PM PST 24
Finished	Jan 07 01:26:08 PM PST 24
Peak memory	308856 kb
Host	smart-a456828f-91c6-4492-a4f8-93da511ed9c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919649803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_txrx.1919649803
Directory	/workspace/2.spi_device_txrx/latest

Test location	/workspace/coverage/default/2.spi_device_upload.3758386400
Short name	T888
Test name
Test status
Simulation time	3639682245 ps
CPU time	15.03 seconds
Started	Jan 07 01:18:32 PM PST 24
Finished	Jan 07 01:18:49 PM PST 24
Peak memory	247648 kb
Host	smart-e6f33e77-6806-4ac2-9ac2-c0f4eedc1427
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758386400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3758386400
Directory	/workspace/2.spi_device_upload/latest

Test location	/workspace/coverage/default/20.spi_device_abort.355756804
Short name	T997
Test name
Test status
Simulation time	13843710 ps
CPU time	0.76 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:29 PM PST 24
Peak memory	206684 kb
Host	smart-aec19d53-ab11-480b-b603-a9a8fa2be2ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=355756804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_abort.355756804
Directory	/workspace/20.spi_device_abort/latest

Test location	/workspace/coverage/default/20.spi_device_alert_test.1868596357
Short name	T580
Test name
Test status
Simulation time	13511721 ps
CPU time	0.71 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:13 PM PST 24
Peak memory	206508 kb
Host	smart-cc5d873e-ffbb-45a5-ad59-e74dbb9732cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868596357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test. 1868596357
Directory	/workspace/20.spi_device_alert_test/latest

Test location	/workspace/coverage/default/20.spi_device_bit_transfer.3521685219
Short name	T1405
Test name
Test status
Simulation time	372983478 ps
CPU time	2.24 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:12 PM PST 24
Peak memory	216764 kb
Host	smart-3b851c19-260b-408c-86f0-0423be6443cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521685219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_bit_transfer.3521685219
Directory	/workspace/20.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/20.spi_device_byte_transfer.4227506371
Short name	T1659
Test name
Test status
Simulation time	313038248 ps
CPU time	2.93 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:32 PM PST 24
Peak memory	216856 kb
Host	smart-0583bfd2-5d55-4d11-9fde-6187832b386d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4227506371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_byte_transfer.4227506371
Directory	/workspace/20.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/20.spi_device_cfg_cmd.1935802383
Short name	T759
Test name
Test status
Simulation time	427997512 ps
CPU time	4.59 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:20 PM PST 24
Peak memory	238600 kb
Host	smart-03278d8b-7ef2-4f55-bd3f-35f998a84f24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935802383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1935802383
Directory	/workspace/20.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/20.spi_device_csb_read.641471339
Short name	T786
Test name
Test status
Simulation time	28974654 ps
CPU time	0.76 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:42 PM PST 24
Peak memory	207660 kb
Host	smart-5ae1aba7-6c49-40c0-baa2-536a3b641be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641471339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.641471339
Directory	/workspace/20.spi_device_csb_read/latest

Test location	/workspace/coverage/default/20.spi_device_dummy_item_extra_dly.3502879486
Short name	T1647
Test name
Test status
Simulation time	65753839481 ps
CPU time	385.12 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:27:54 PM PST 24
Peak memory	288548 kb
Host	smart-449995af-35fa-426e-8ce9-bf7f4b26b6d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502879486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_dummy_item_extra_dly.3502879486
Directory	/workspace/20.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/20.spi_device_extreme_fifo_size.205795504
Short name	T1235
Test name
Test status
Simulation time	98708801706 ps
CPU time	1141.11 seconds
Started	Jan 07 01:21:16 PM PST 24
Finished	Jan 07 01:40:19 PM PST 24
Peak memory	220392 kb
Host	smart-6b039297-183b-4b22-8dae-c2c9bbe26489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205795504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_extreme_fifo_size.205795504
Directory	/workspace/20.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/20.spi_device_fifo_full.1290644097
Short name	T545
Test name
Test status
Simulation time	34876723140 ps
CPU time	178.45 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:24:26 PM PST 24
Peak memory	273256 kb
Host	smart-90451390-5dd9-4ff2-96fb-4f5bf29b0e06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290644097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_fifo_full.1290644097
Directory	/workspace/20.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/20.spi_device_flash_all.721717016
Short name	T489
Test name
Test status
Simulation time	701838918 ps
CPU time	4.3 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	236608 kb
Host	smart-f4ffb969-97eb-42c8-a2c8-c6d7b7babd86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721717016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.721717016
Directory	/workspace/20.spi_device_flash_all/latest

Test location	/workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1831572825
Short name	T765
Test name
Test status
Simulation time	76405943551 ps
CPU time	281.39 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:26:51 PM PST 24
Peak memory	253652 kb
Host	smart-de906b97-b05d-49ac-b639-9268ef22876d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831572825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl e.1831572825
Directory	/workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/20.spi_device_flash_mode.482949131
Short name	T1723
Test name
Test status
Simulation time	771413171 ps
CPU time	12.82 seconds
Started	Jan 07 01:21:39 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	241324 kb
Host	smart-14f80288-6a50-4f8a-a61c-02af6a2e1555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482949131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.482949131
Directory	/workspace/20.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/20.spi_device_intercept.4028073427
Short name	T1339
Test name
Test status
Simulation time	2282366058 ps
CPU time	9.76 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:26 PM PST 24
Peak memory	238620 kb
Host	smart-b8e2c044-4a42-4107-86df-b8e26531f92e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028073427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4028073427
Directory	/workspace/20.spi_device_intercept/latest

Test location	/workspace/coverage/default/20.spi_device_intr.4273910639
Short name	T641
Test name
Test status
Simulation time	7715380262 ps
CPU time	31.74 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:49 PM PST 24
Peak memory	220528 kb
Host	smart-df20c70c-9175-49b7-ab4c-a5be7eeddb93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273910639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intr.4273910639
Directory	/workspace/20.spi_device_intr/latest

Test location	/workspace/coverage/default/20.spi_device_mailbox.387319095
Short name	T983
Test name
Test status
Simulation time	27212161861 ps
CPU time	66.98 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:23:19 PM PST 24
Peak memory	233124 kb
Host	smart-79bac86b-c498-43a4-9ce9-ccb898b820e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387319095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.387319095
Directory	/workspace/20.spi_device_mailbox/latest

Test location	/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1479919731
Short name	T678
Test name
Test status
Simulation time	1773275423 ps
CPU time	8.67 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:36 PM PST 24
Peak memory	218604 kb
Host	smart-0cf1d652-8d54-4caa-a9d0-9e7f6d51c0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479919731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.1479919731
Directory	/workspace/20.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/20.spi_device_pass_cmd_filtering.3703699962
Short name	T1148
Test name
Test status
Simulation time	3272131687 ps
CPU time	12.72 seconds
Started	Jan 07 01:22:13 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	237616 kb
Host	smart-1e344af5-5c7b-4515-8e87-288c2df35d54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703699962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3703699962
Directory	/workspace/20.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/20.spi_device_perf.1803921871
Short name	T668
Test name
Test status
Simulation time	71936128375 ps
CPU time	934.28 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:37:03 PM PST 24
Peak memory	284268 kb
Host	smart-27ec508c-cd46-48c6-ac5d-358695f3a343
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803921871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_perf.1803921871
Directory	/workspace/20.spi_device_perf/latest

Test location	/workspace/coverage/default/20.spi_device_read_buffer_direct.1795918367
Short name	T1666
Test name
Test status
Simulation time	790309347 ps
CPU time	3.95 seconds
Started	Jan 07 01:21:50 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	218572 kb
Host	smart-dfb63333-0e44-47af-b5a7-74fea04e7d6d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1795918367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.1795918367
Directory	/workspace/20.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/20.spi_device_rx_async_fifo_reset.3316125326
Short name	T1292
Test name
Test status
Simulation time	159945540 ps
CPU time	0.91 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:29 PM PST 24
Peak memory	208408 kb
Host	smart-010b025e-2306-4a37-a0a1-03f25eb2a393
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3316125326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_async_fifo_reset.3316125326
Directory	/workspace/20.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/20.spi_device_rx_timeout.3992218142
Short name	T474
Test name
Test status
Simulation time	2878215819 ps
CPU time	5.63 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:32 PM PST 24
Peak memory	216896 kb
Host	smart-7e18a731-aec4-4c58-8aec-b93b58b2d544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992218142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_rx_timeout.3992218142
Directory	/workspace/20.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/20.spi_device_smoke.3063914181
Short name	T756
Test name
Test status
Simulation time	256397224 ps
CPU time	1.02 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	208028 kb
Host	smart-999e245e-ea23-4d57-8b99-cd6941a430e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063914181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_smoke.3063914181
Directory	/workspace/20.spi_device_smoke/latest

Test location	/workspace/coverage/default/20.spi_device_stress_all.1891945380
Short name	T1444
Test name
Test status
Simulation time	329484962475 ps
CPU time	1068.58 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:39:30 PM PST 24
Peak memory	336384 kb
Host	smart-563bbae4-9f7f-4b06-995b-fcb852bb49a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891945380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre ss_all.1891945380
Directory	/workspace/20.spi_device_stress_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_all.1881176069
Short name	T971
Test name
Test status
Simulation time	23553589819 ps
CPU time	59.14 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:22:28 PM PST 24
Peak memory	216888 kb
Host	smart-6ccf5b16-5e9c-4f0f-86db-2dd9265a5cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881176069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1881176069
Directory	/workspace/20.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4278578614
Short name	T1281
Test name
Test status
Simulation time	39469952909 ps
CPU time	11.12 seconds
Started	Jan 07 01:21:28 PM PST 24
Finished	Jan 07 01:21:42 PM PST 24
Peak memory	216880 kb
Host	smart-c70eb7c1-2e83-4d25-a0b3-07e6543bf1d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278578614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4278578614
Directory	/workspace/20.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_rw.2235871322
Short name	T556
Test name
Test status
Simulation time	70872619 ps
CPU time	1.29 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:13 PM PST 24
Peak memory	216808 kb
Host	smart-c86d1669-56c9-474f-ada2-12452c1a2985
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235871322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2235871322
Directory	/workspace/20.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_sts_read.2536523206
Short name	T1409
Test name
Test status
Simulation time	189987845 ps
CPU time	1.28 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:21:28 PM PST 24
Peak memory	208008 kb
Host	smart-c017c37c-f0e6-4401-8085-d2fab07c723a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536523206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2536523206
Directory	/workspace/20.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/20.spi_device_tx_async_fifo_reset.1275943997
Short name	T629
Test name
Test status
Simulation time	16287839 ps
CPU time	0.79 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:30 PM PST 24
Peak memory	208472 kb
Host	smart-1cd513db-c2fe-4767-b827-22fcbdb09aba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275943997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tx_async_fifo_reset.1275943997
Directory	/workspace/20.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/20.spi_device_txrx.3290220506
Short name	T1078
Test name
Test status
Simulation time	75551016542 ps
CPU time	267.12 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:26:35 PM PST 24
Peak memory	297860 kb
Host	smart-3cb99ac1-7770-411a-94d7-a15f8aff46eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290220506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_txrx.3290220506
Directory	/workspace/20.spi_device_txrx/latest

Test location	/workspace/coverage/default/20.spi_device_upload.1686840670
Short name	T1010
Test name
Test status
Simulation time	5284326398 ps
CPU time	12.77 seconds
Started	Jan 07 01:21:24 PM PST 24
Finished	Jan 07 01:21:38 PM PST 24
Peak memory	220888 kb
Host	smart-694e1a40-0b11-4cd5-8cbe-bebbaddd4339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686840670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1686840670
Directory	/workspace/20.spi_device_upload/latest

Test location	/workspace/coverage/default/21.spi_device_abort.1457734335
Short name	T488
Test name
Test status
Simulation time	24670328 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:11 PM PST 24
Peak memory	206676 kb
Host	smart-afac44e1-f918-4660-8fe7-b088b879b836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457734335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_abort.1457734335
Directory	/workspace/21.spi_device_abort/latest

Test location	/workspace/coverage/default/21.spi_device_alert_test.2498498775
Short name	T486
Test name
Test status
Simulation time	12453365 ps
CPU time	0.72 seconds
Started	Jan 07 01:21:27 PM PST 24
Finished	Jan 07 01:21:30 PM PST 24
Peak memory	206452 kb
Host	smart-e0899c25-7e66-4265-af76-290ae47bf749
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498498775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test. 2498498775
Directory	/workspace/21.spi_device_alert_test/latest

Test location	/workspace/coverage/default/21.spi_device_bit_transfer.1315998643
Short name	T560
Test name
Test status
Simulation time	355211293 ps
CPU time	2.13 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:31 PM PST 24
Peak memory	216776 kb
Host	smart-fdc5fb1a-6579-4520-a4f7-02ae92bf0610
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315998643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_bit_transfer.1315998643
Directory	/workspace/21.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/21.spi_device_byte_transfer.2313545370
Short name	T1136
Test name
Test status
Simulation time	751823981 ps
CPU time	3.25 seconds
Started	Jan 07 01:21:39 PM PST 24
Finished	Jan 07 01:21:47 PM PST 24
Peak memory	216888 kb
Host	smart-53401f47-3037-461c-b4c2-a3e2047c3af5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313545370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_byte_transfer.2313545370
Directory	/workspace/21.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/21.spi_device_cfg_cmd.1513604902
Short name	T1501
Test name
Test status
Simulation time	379178827 ps
CPU time	3.46 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:14 PM PST 24
Peak memory	218824 kb
Host	smart-b0b97256-b23d-498e-9f88-e55d73ade7e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513604902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1513604902
Directory	/workspace/21.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/21.spi_device_csb_read.1227798085
Short name	T36
Test name
Test status
Simulation time	83388589 ps
CPU time	0.83 seconds
Started	Jan 07 01:21:27 PM PST 24
Finished	Jan 07 01:21:31 PM PST 24
Peak memory	207452 kb
Host	smart-20efecd8-2287-409e-810a-68fd56470e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227798085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1227798085
Directory	/workspace/21.spi_device_csb_read/latest

Test location	/workspace/coverage/default/21.spi_device_dummy_item_extra_dly.260175524
Short name	T666
Test name
Test status
Simulation time	48578982492 ps
CPU time	206.27 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:24:54 PM PST 24
Peak memory	288740 kb
Host	smart-8d203cde-9081-4757-9edb-f62e05f7ecfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260175524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_dummy_item_extra_dly.260175524
Directory	/workspace/21.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/21.spi_device_extreme_fifo_size.1682593641
Short name	T1373
Test name
Test status
Simulation time	5826085586 ps
CPU time	27.75 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	231324 kb
Host	smart-a2052a7e-9c28-4e0d-a1bf-b723d12f217d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682593641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_extreme_fifo_size.1682593641
Directory	/workspace/21.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/21.spi_device_fifo_full.4143809726
Short name	T1727
Test name
Test status
Simulation time	25408389975 ps
CPU time	525.69 seconds
Started	Jan 07 01:21:39 PM PST 24
Finished	Jan 07 01:30:28 PM PST 24
Peak memory	259348 kb
Host	smart-c26d7cf3-1861-4a20-a6d3-7717f24683ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143809726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_full.4143809726
Directory	/workspace/21.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/21.spi_device_fifo_underflow_overflow.3609399423
Short name	T264
Test name
Test status
Simulation time	368968911268 ps
CPU time	354.93 seconds
Started	Jan 07 01:21:36 PM PST 24
Finished	Jan 07 01:27:34 PM PST 24
Peak memory	322236 kb
Host	smart-d7dc6c22-62e7-49ad-8111-af003e1cf707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609399423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_fifo_underflow_overf low.3609399423
Directory	/workspace/21.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/21.spi_device_flash_all.3914343482
Short name	T1324
Test name
Test status
Simulation time	10530070929 ps
CPU time	81.28 seconds
Started	Jan 07 01:21:36 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	257532 kb
Host	smart-ceec921d-4def-48ec-b1cc-a4a81efbee06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914343482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3914343482
Directory	/workspace/21.spi_device_flash_all/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm.262716978
Short name	T38
Test name
Test status
Simulation time	298041397218 ps
CPU time	211.03 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:25:39 PM PST 24
Peak memory	258016 kb
Host	smart-2465152f-39f7-487f-9414-9bab2c4d45da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262716978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.262716978
Directory	/workspace/21.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2492122579
Short name	T1714
Test name
Test status
Simulation time	163488180864 ps
CPU time	131.97 seconds
Started	Jan 07 01:21:50 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	239112 kb
Host	smart-ee187d89-08d9-4c1e-a6b2-89361caaa825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492122579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl e.2492122579
Directory	/workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/21.spi_device_flash_mode.3623872288
Short name	T659
Test name
Test status
Simulation time	2728112694 ps
CPU time	17.06 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	229720 kb
Host	smart-48adece1-900e-4ded-83b4-34f37a2c0a32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623872288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3623872288
Directory	/workspace/21.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/21.spi_device_intercept.3531383529
Short name	T903
Test name
Test status
Simulation time	1611788257 ps
CPU time	6.49 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:22:15 PM PST 24
Peak memory	219116 kb
Host	smart-02391988-afc2-4524-bb82-4fb5af55bbab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531383529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3531383529
Directory	/workspace/21.spi_device_intercept/latest

Test location	/workspace/coverage/default/21.spi_device_intr.2304025984
Short name	T1606
Test name
Test status
Simulation time	34749839856 ps
CPU time	15.35 seconds
Started	Jan 07 01:22:13 PM PST 24
Finished	Jan 07 01:22:34 PM PST 24
Peak memory	224824 kb
Host	smart-0fc8c9a2-9495-4359-8465-afaebc8001a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304025984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intr.2304025984
Directory	/workspace/21.spi_device_intr/latest

Test location	/workspace/coverage/default/21.spi_device_mailbox.4119489465
Short name	T1574
Test name
Test status
Simulation time	1154572519 ps
CPU time	5.41 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:22 PM PST 24
Peak memory	224844 kb
Host	smart-0d14cdfd-84f6-4e6c-ac52-000dca90ce91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119489465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4119489465
Directory	/workspace/21.spi_device_mailbox/latest

Test location	/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1123585248
Short name	T293
Test name
Test status
Simulation time	716236426 ps
CPU time	6.38 seconds
Started	Jan 07 01:21:27 PM PST 24
Finished	Jan 07 01:21:37 PM PST 24
Peak memory	246580 kb
Host	smart-c5bd0176-9420-4593-87d0-8e854047fe6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123585248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa p.1123585248
Directory	/workspace/21.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/21.spi_device_pass_cmd_filtering.2154691805
Short name	T1183
Test name
Test status
Simulation time	20290799826 ps
CPU time	19.33 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:21:57 PM PST 24
Peak memory	224620 kb
Host	smart-eb2e4025-190b-4087-a5fa-1537917665c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154691805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2154691805
Directory	/workspace/21.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/21.spi_device_perf.4139275524
Short name	T458
Test name
Test status
Simulation time	82854310677 ps
CPU time	976.52 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:38:29 PM PST 24
Peak memory	257548 kb
Host	smart-eff30f93-1bed-4970-98eb-e2b6c64e44fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139275524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_perf.4139275524
Directory	/workspace/21.spi_device_perf/latest

Test location	/workspace/coverage/default/21.spi_device_read_buffer_direct.2576478860
Short name	T1707
Test name
Test status
Simulation time	2042012382 ps
CPU time	8.14 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:20 PM PST 24
Peak memory	219000 kb
Host	smart-aa9072f5-c6ae-4cff-9fe9-09da9df18372
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2576478860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir ect.2576478860
Directory	/workspace/21.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/21.spi_device_rx_async_fifo_reset.1933450834
Short name	T483
Test name
Test status
Simulation time	23451053 ps
CPU time	0.88 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:43 PM PST 24
Peak memory	208516 kb
Host	smart-399a56e0-d361-435b-bfdc-0fa1269a064b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933450834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_async_fifo_reset.1933450834
Directory	/workspace/21.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/21.spi_device_rx_timeout.1896235754
Short name	T1675
Test name
Test status
Simulation time	470936465 ps
CPU time	4.71 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:21 PM PST 24
Peak memory	216836 kb
Host	smart-ede99f0a-baaf-4a5f-b25c-bee0d8a831e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896235754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_rx_timeout.1896235754
Directory	/workspace/21.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/21.spi_device_smoke.2544520738
Short name	T1568
Test name
Test status
Simulation time	19571140 ps
CPU time	0.95 seconds
Started	Jan 07 01:21:24 PM PST 24
Finished	Jan 07 01:21:26 PM PST 24
Peak memory	208116 kb
Host	smart-7b935069-a079-41a3-9147-a529653cacd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544520738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_smoke.2544520738
Directory	/workspace/21.spi_device_smoke/latest

Test location	/workspace/coverage/default/21.spi_device_stress_all.365426149
Short name	T160
Test name
Test status
Simulation time	69979992495 ps
CPU time	861.11 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:36:38 PM PST 24
Peak memory	389616 kb
Host	smart-6a37c9c0-eb75-441f-9385-a92e5a7c6245
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365426149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres s_all.365426149
Directory	/workspace/21.spi_device_stress_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_all.4277627109
Short name	T1109
Test name
Test status
Simulation time	5497220620 ps
CPU time	46.03 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:57 PM PST 24
Peak memory	221940 kb
Host	smart-5fdd85c0-c239-482e-b764-f447e2ad2fd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277627109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4277627109
Directory	/workspace/21.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4055015526
Short name	T1710
Test name
Test status
Simulation time	22418392002 ps
CPU time	8.72 seconds
Started	Jan 07 01:21:26 PM PST 24
Finished	Jan 07 01:21:37 PM PST 24
Peak memory	216864 kb
Host	smart-d204a615-36cc-4975-902b-9d180d875cfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055015526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4055015526
Directory	/workspace/21.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_rw.1378233815
Short name	T1357
Test name
Test status
Simulation time	105455067 ps
CPU time	1.81 seconds
Started	Jan 07 01:21:54 PM PST 24
Finished	Jan 07 01:21:58 PM PST 24
Peak memory	216784 kb
Host	smart-4129330d-5f12-49b8-b255-b2b0021c5f49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1378233815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1378233815
Directory	/workspace/21.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_sts_read.1131248488
Short name	T1280
Test name
Test status
Simulation time	228199571 ps
CPU time	0.84 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:43 PM PST 24
Peak memory	206936 kb
Host	smart-90c67b34-3926-4599-8fd0-bda7f02efb5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131248488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1131248488
Directory	/workspace/21.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/21.spi_device_tx_async_fifo_reset.1873134528
Short name	T482
Test name
Test status
Simulation time	13474554 ps
CPU time	0.78 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:14 PM PST 24
Peak memory	208476 kb
Host	smart-60d273cc-945b-4d13-b957-8a12043903df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873134528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tx_async_fifo_reset.1873134528
Directory	/workspace/21.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/21.spi_device_txrx.1906372880
Short name	T853
Test name
Test status
Simulation time	12397041628 ps
CPU time	116.88 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:23:25 PM PST 24
Peak memory	251860 kb
Host	smart-f0797dc8-2f61-41d0-b8dd-018e47d1f4ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906372880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_txrx.1906372880
Directory	/workspace/21.spi_device_txrx/latest

Test location	/workspace/coverage/default/21.spi_device_upload.1636520379
Short name	T685
Test name
Test status
Simulation time	359434293 ps
CPU time	3.12 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:45 PM PST 24
Peak memory	219040 kb
Host	smart-bd3cf061-9e54-45e9-9ece-964723ea18f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636520379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1636520379
Directory	/workspace/21.spi_device_upload/latest

Test location	/workspace/coverage/default/22.spi_device_abort.1760531173
Short name	T1278
Test name
Test status
Simulation time	68355727 ps
CPU time	0.76 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:43 PM PST 24
Peak memory	206576 kb
Host	smart-3f24a578-51f6-4524-91a9-c7c1bf3f2b92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760531173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_abort.1760531173
Directory	/workspace/22.spi_device_abort/latest

Test location	/workspace/coverage/default/22.spi_device_alert_test.3535177300
Short name	T945
Test name
Test status
Simulation time	19357875 ps
CPU time	0.73 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:21:41 PM PST 24
Peak memory	206464 kb
Host	smart-3556b295-0d33-40b2-bddf-a007d7f1151f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535177300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 3535177300
Directory	/workspace/22.spi_device_alert_test/latest

Test location	/workspace/coverage/default/22.spi_device_bit_transfer.1426809543
Short name	T712
Test name
Test status
Simulation time	796633842 ps
CPU time	2.74 seconds
Started	Jan 07 01:21:33 PM PST 24
Finished	Jan 07 01:21:37 PM PST 24
Peak memory	216736 kb
Host	smart-e87138d9-8c31-443d-9417-cb39b6e0cf6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426809543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_bit_transfer.1426809543
Directory	/workspace/22.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/22.spi_device_byte_transfer.997110543
Short name	T1054
Test name
Test status
Simulation time	337160266 ps
CPU time	3.09 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:45 PM PST 24
Peak memory	216864 kb
Host	smart-e3db00b7-dacf-49b0-88a2-5f4b7f36a864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997110543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_byte_transfer.997110543
Directory	/workspace/22.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/22.spi_device_cfg_cmd.2337153173
Short name	T1287
Test name
Test status
Simulation time	538308976 ps
CPU time	5.26 seconds
Started	Jan 07 01:21:36 PM PST 24
Finished	Jan 07 01:21:43 PM PST 24
Peak memory	236484 kb
Host	smart-ffbd2e7e-7ecb-42ec-9796-02e95dc7149f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337153173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2337153173
Directory	/workspace/22.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/22.spi_device_csb_read.2763554562
Short name	T868
Test name
Test status
Simulation time	16724217 ps
CPU time	0.78 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:12 PM PST 24
Peak memory	207624 kb
Host	smart-4e433f3d-18d6-4396-bf25-54fff4d5c616
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763554562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2763554562
Directory	/workspace/22.spi_device_csb_read/latest

Test location	/workspace/coverage/default/22.spi_device_dummy_item_extra_dly.194247564
Short name	T1105
Test name
Test status
Simulation time	40806216845 ps
CPU time	220.84 seconds
Started	Jan 07 01:21:24 PM PST 24
Finished	Jan 07 01:25:06 PM PST 24
Peak memory	273880 kb
Host	smart-265a072a-01bc-4dd4-b79a-e30c050255a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194247564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_dummy_item_extra_dly.194247564
Directory	/workspace/22.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/22.spi_device_extreme_fifo_size.3838544157
Short name	T1115
Test name
Test status
Simulation time	262659574958 ps
CPU time	1037.26 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:39:31 PM PST 24
Peak memory	225112 kb
Host	smart-39f1b4b9-17c0-4fd1-bd1e-ad0bcebac414
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838544157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_extreme_fifo_size.3838544157
Directory	/workspace/22.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/22.spi_device_fifo_full.1374519164
Short name	T1648
Test name
Test status
Simulation time	42752612604 ps
CPU time	1153.24 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:41:27 PM PST 24
Peak memory	281680 kb
Host	smart-ad3df039-7af4-425f-a7d0-47894cb130db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374519164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_full.1374519164
Directory	/workspace/22.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/22.spi_device_fifo_underflow_overflow.1268290988
Short name	T96
Test name
Test status
Simulation time	55094964200 ps
CPU time	152.95 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:24:43 PM PST 24
Peak memory	343056 kb
Host	smart-4fbfa04e-1759-49ef-b30a-61dc8c7e2ff7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268290988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_fifo_underflow_overf low.1268290988
Directory	/workspace/22.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/22.spi_device_flash_all.873863062
Short name	T253
Test name
Test status
Simulation time	54683701186 ps
CPU time	90.04 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:23:38 PM PST 24
Peak memory	250768 kb
Host	smart-e6b7ac27-68bb-48b8-9990-8f1a2353745a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873863062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.873863062
Directory	/workspace/22.spi_device_flash_all/latest

Test location	/workspace/coverage/default/22.spi_device_flash_and_tpm.3279273395
Short name	T330
Test name
Test status
Simulation time	90786225275 ps
CPU time	339.33 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:27:48 PM PST 24
Peak memory	253072 kb
Host	smart-0ff006fa-8893-4614-b76a-e0a1787bc252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279273395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3279273395
Directory	/workspace/22.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/22.spi_device_intercept.2967455134
Short name	T1123
Test name
Test status
Simulation time	8768442113 ps
CPU time	7.63 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:23 PM PST 24
Peak memory	236836 kb
Host	smart-2e2a788b-f08e-47ef-930e-200ea63d5b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967455134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2967455134
Directory	/workspace/22.spi_device_intercept/latest

Test location	/workspace/coverage/default/22.spi_device_intr.2777283720
Short name	T824
Test name
Test status
Simulation time	6418821191 ps
CPU time	47.12 seconds
Started	Jan 07 01:21:25 PM PST 24
Finished	Jan 07 01:22:14 PM PST 24
Peak memory	234484 kb
Host	smart-dd57c428-09fe-462a-b918-47267f206b91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777283720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intr.2777283720
Directory	/workspace/22.spi_device_intr/latest

Test location	/workspace/coverage/default/22.spi_device_mailbox.3460374430
Short name	T1401
Test name
Test status
Simulation time	2773128178 ps
CPU time	15.01 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:21:55 PM PST 24
Peak memory	247016 kb
Host	smart-55a55e49-0c22-43bd-adb3-75e2945b4bcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460374430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3460374430
Directory	/workspace/22.spi_device_mailbox/latest

Test location	/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3640012748
Short name	T1566
Test name
Test status
Simulation time	25994196059 ps
CPU time	35.49 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	249116 kb
Host	smart-23b6b72d-4fc6-455d-80f5-29ccb6a7ced2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640012748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa p.3640012748
Directory	/workspace/22.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/22.spi_device_pass_cmd_filtering.3987086863
Short name	T1698
Test name
Test status
Simulation time	46522639827 ps
CPU time	28.35 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:42 PM PST 24
Peak memory	251752 kb
Host	smart-c1fe546a-3c66-4d6e-845d-5a263dd1dca8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987086863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3987086863
Directory	/workspace/22.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/22.spi_device_perf.2583183557
Short name	T1321
Test name
Test status
Simulation time	150330461685 ps
CPU time	1816.64 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:51:53 PM PST 24
Peak memory	241024 kb
Host	smart-f54fd8c4-9c39-4bbe-9ae9-d61ec189a26e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583183557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_perf.2583183557
Directory	/workspace/22.spi_device_perf/latest

Test location	/workspace/coverage/default/22.spi_device_read_buffer_direct.1944088980
Short name	T1481
Test name
Test status
Simulation time	2504885040 ps
CPU time	3.94 seconds
Started	Jan 07 01:21:53 PM PST 24
Finished	Jan 07 01:22:00 PM PST 24
Peak memory	218928 kb
Host	smart-f0e3d7c7-49be-4345-8f20-1d3fb4de284a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1944088980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir ect.1944088980
Directory	/workspace/22.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/22.spi_device_rx_async_fifo_reset.1853431196
Short name	T1447
Test name
Test status
Simulation time	190440621 ps
CPU time	0.93 seconds
Started	Jan 07 01:22:05 PM PST 24
Finished	Jan 07 01:22:08 PM PST 24
Peak memory	208440 kb
Host	smart-bd4cf03b-9493-4d94-a555-b021dbb0d287
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853431196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_async_fifo_reset.1853431196
Directory	/workspace/22.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/22.spi_device_rx_timeout.847483168
Short name	T1678
Test name
Test status
Simulation time	2040151175 ps
CPU time	5.67 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:20 PM PST 24
Peak memory	216744 kb
Host	smart-602ce4ed-d3c2-46ed-a919-0b4350fe7360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847483168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_rx_timeout.847483168
Directory	/workspace/22.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/22.spi_device_smoke.3216845263
Short name	T965
Test name
Test status
Simulation time	40267947 ps
CPU time	1.23 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:21:39 PM PST 24
Peak memory	216824 kb
Host	smart-4bed584e-0542-4b79-81f8-8869ef3d352e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216845263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_smoke.3216845263
Directory	/workspace/22.spi_device_smoke/latest

Test location	/workspace/coverage/default/22.spi_device_stress_all.1612394580
Short name	T327
Test name
Test status
Simulation time	110769283493 ps
CPU time	910.17 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:36:53 PM PST 24
Peak memory	299604 kb
Host	smart-e49cdade-9e47-4120-9964-57fd027a0b05
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612394580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre ss_all.1612394580
Directory	/workspace/22.spi_device_stress_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_all.357945262
Short name	T663
Test name
Test status
Simulation time	872717383 ps
CPU time	2.57 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:21:39 PM PST 24
Peak memory	219340 kb
Host	smart-1f07fbbe-c0cc-4744-9878-320aba8ce7f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357945262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.357945262
Directory	/workspace/22.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3466488224
Short name	T1623
Test name
Test status
Simulation time	1601055556 ps
CPU time	7.08 seconds
Started	Jan 07 01:21:39 PM PST 24
Finished	Jan 07 01:21:50 PM PST 24
Peak memory	216820 kb
Host	smart-416f6fb2-fca0-4757-ab2a-040326776352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466488224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3466488224
Directory	/workspace/22.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_rw.2523465546
Short name	T15
Test name
Test status
Simulation time	346305328 ps
CPU time	1.2 seconds
Started	Jan 07 01:22:06 PM PST 24
Finished	Jan 07 01:22:10 PM PST 24
Peak memory	208436 kb
Host	smart-30dc046b-d654-4d39-b614-80b46d691069
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523465546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2523465546
Directory	/workspace/22.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_sts_read.1907274244
Short name	T1095
Test name
Test status
Simulation time	55560782 ps
CPU time	0.93 seconds
Started	Jan 07 01:22:07 PM PST 24
Finished	Jan 07 01:22:11 PM PST 24
Peak memory	206888 kb
Host	smart-d7ca565f-5ad6-4e33-8a10-79a0618c4c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907274244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1907274244
Directory	/workspace/22.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/22.spi_device_tx_async_fifo_reset.2116464971
Short name	T1455
Test name
Test status
Simulation time	59786004 ps
CPU time	0.79 seconds
Started	Jan 07 01:22:05 PM PST 24
Finished	Jan 07 01:22:08 PM PST 24
Peak memory	208344 kb
Host	smart-66221294-2cac-47bc-81d2-3f94bef509c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116464971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tx_async_fifo_reset.2116464971
Directory	/workspace/22.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/22.spi_device_txrx.1594309487
Short name	T436
Test name
Test status
Simulation time	32936751524 ps
CPU time	228.96 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	270184 kb
Host	smart-63ceaa1d-1d1f-4f5c-b582-dca4081e7fd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594309487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_txrx.1594309487
Directory	/workspace/22.spi_device_txrx/latest

Test location	/workspace/coverage/default/22.spi_device_upload.2295457333
Short name	T1376
Test name
Test status
Simulation time	1742237302 ps
CPU time	13.26 seconds
Started	Jan 07 01:21:35 PM PST 24
Finished	Jan 07 01:21:50 PM PST 24
Peak memory	249600 kb
Host	smart-4e5ddefb-db5c-4baa-bbe0-8041c433cd20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295457333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2295457333
Directory	/workspace/22.spi_device_upload/latest

Test location	/workspace/coverage/default/23.spi_device_abort.1991130141
Short name	T957
Test name
Test status
Simulation time	13249120 ps
CPU time	0.73 seconds
Started	Jan 07 01:22:22 PM PST 24
Finished	Jan 07 01:22:30 PM PST 24
Peak memory	206612 kb
Host	smart-40390932-9255-428b-84b3-1dd367150788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991130141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_abort.1991130141
Directory	/workspace/23.spi_device_abort/latest

Test location	/workspace/coverage/default/23.spi_device_alert_test.3685093807
Short name	T1372
Test name
Test status
Simulation time	31209439 ps
CPU time	0.7 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	206520 kb
Host	smart-0f1f311f-f8ac-4596-87f5-fd86c400ace7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685093807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test. 3685093807
Directory	/workspace/23.spi_device_alert_test/latest

Test location	/workspace/coverage/default/23.spi_device_bit_transfer.4014539714
Short name	T861
Test name
Test status
Simulation time	1483683558 ps
CPU time	2.43 seconds
Started	Jan 07 01:22:22 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	216884 kb
Host	smart-f8e458d8-7bff-4d93-9a04-e6c18e281a0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014539714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_bit_transfer.4014539714
Directory	/workspace/23.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/23.spi_device_byte_transfer.3756747121
Short name	T543
Test name
Test status
Simulation time	450363688 ps
CPU time	2.93 seconds
Started	Jan 07 01:22:22 PM PST 24
Finished	Jan 07 01:22:34 PM PST 24
Peak memory	216644 kb
Host	smart-098ec68f-c422-4fec-9384-0015d2b607a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756747121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_byte_transfer.3756747121
Directory	/workspace/23.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/23.spi_device_cfg_cmd.1955202039
Short name	T276
Test name
Test status
Simulation time	752329268 ps
CPU time	3.76 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:21 PM PST 24
Peak memory	237940 kb
Host	smart-11a18f12-2b16-48c6-97d2-11cc6a714360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955202039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1955202039
Directory	/workspace/23.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/23.spi_device_csb_read.937046670
Short name	T763
Test name
Test status
Simulation time	24407776 ps
CPU time	0.78 seconds
Started	Jan 07 01:21:39 PM PST 24
Finished	Jan 07 01:21:44 PM PST 24
Peak memory	207624 kb
Host	smart-29c519f3-8909-4d87-a6d4-d5259f891670
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937046670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.937046670
Directory	/workspace/23.spi_device_csb_read/latest

Test location	/workspace/coverage/default/23.spi_device_dummy_item_extra_dly.2301953233
Short name	T1211
Test name
Test status
Simulation time	476327847326 ps
CPU time	936.98 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:37:52 PM PST 24
Peak memory	274268 kb
Host	smart-ab27b9c2-5720-4ee6-bae3-9cbf75370d7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301953233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_dummy_item_extra_dly.2301953233
Directory	/workspace/23.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/23.spi_device_extreme_fifo_size.594398173
Short name	T1437
Test name
Test status
Simulation time	207851767133 ps
CPU time	918.49 seconds
Started	Jan 07 01:21:37 PM PST 24
Finished	Jan 07 01:36:59 PM PST 24
Peak memory	218056 kb
Host	smart-70e12d44-fb77-42c2-9e4b-a1ff4e41f274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594398173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_extreme_fifo_size.594398173
Directory	/workspace/23.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/23.spi_device_fifo_full.3494664604
Short name	T203
Test name
Test status
Simulation time	26360403995 ps
CPU time	594.59 seconds
Started	Jan 07 01:22:15 PM PST 24
Finished	Jan 07 01:32:15 PM PST 24
Peak memory	255728 kb
Host	smart-7d6d05b0-4770-4238-a64b-47a8de4df461
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494664604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_full.3494664604
Directory	/workspace/23.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/23.spi_device_fifo_underflow_overflow.4137996057
Short name	T838
Test name
Test status
Simulation time	98315726151 ps
CPU time	288.01 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:26:30 PM PST 24
Peak memory	379812 kb
Host	smart-26c57eb1-4956-4739-a6ca-c85d25b2cf5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137996057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_fifo_underflow_overf low.4137996057
Directory	/workspace/23.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/23.spi_device_flash_all.2603812068
Short name	T530
Test name
Test status
Simulation time	48772173054 ps
CPU time	76.64 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:23:32 PM PST 24
Peak memory	254208 kb
Host	smart-97d87502-a748-41b0-8253-2baf75601393
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603812068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2603812068
Directory	/workspace/23.spi_device_flash_all/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm.3073900280
Short name	T1166
Test name
Test status
Simulation time	3636857622 ps
CPU time	84.34 seconds
Started	Jan 07 01:21:50 PM PST 24
Finished	Jan 07 01:23:17 PM PST 24
Peak memory	273544 kb
Host	smart-303735b2-0836-4f33-98b5-3647c3d3ba9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073900280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3073900280
Directory	/workspace/23.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.271702347
Short name	T953
Test name
Test status
Simulation time	1729545133 ps
CPU time	33.82 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:51 PM PST 24
Peak memory	250420 kb
Host	smart-3666a3e1-9377-4ea6-94a7-c2c290c760ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271702347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle .271702347
Directory	/workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/23.spi_device_flash_mode.638183532
Short name	T758
Test name
Test status
Simulation time	2026642559 ps
CPU time	20.61 seconds
Started	Jan 07 01:21:55 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	244576 kb
Host	smart-0893b505-ca7c-44ce-b906-fa213f6f1918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638183532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.638183532
Directory	/workspace/23.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/23.spi_device_intercept.1880629778
Short name	T615
Test name
Test status
Simulation time	648557622 ps
CPU time	3.35 seconds
Started	Jan 07 01:21:51 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	241312 kb
Host	smart-43f2bab0-dc5f-466c-bdb1-2faf3a070bb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880629778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1880629778
Directory	/workspace/23.spi_device_intercept/latest

Test location	/workspace/coverage/default/23.spi_device_intr.1453092593
Short name	T535
Test name
Test status
Simulation time	18947011094 ps
CPU time	10.48 seconds
Started	Jan 07 01:21:55 PM PST 24
Finished	Jan 07 01:22:08 PM PST 24
Peak memory	218164 kb
Host	smart-3ee2d1cd-2960-4eeb-812d-5738fb3ab52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453092593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intr.1453092593
Directory	/workspace/23.spi_device_intr/latest

Test location	/workspace/coverage/default/23.spi_device_mailbox.392066689
Short name	T213
Test name
Test status
Simulation time	32406094902 ps
CPU time	31.48 seconds
Started	Jan 07 01:21:42 PM PST 24
Finished	Jan 07 01:22:17 PM PST 24
Peak memory	231788 kb
Host	smart-af6f0e99-db1b-4da9-a56d-ccaa88560797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392066689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.392066689
Directory	/workspace/23.spi_device_mailbox/latest

Test location	/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.426809555
Short name	T1192
Test name
Test status
Simulation time	1390853914 ps
CPU time	10.84 seconds
Started	Jan 07 01:21:40 PM PST 24
Finished	Jan 07 01:21:55 PM PST 24
Peak memory	233336 kb
Host	smart-00c1bfa3-a749-4345-aa35-007f67f9cc1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426809555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap .426809555
Directory	/workspace/23.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/23.spi_device_pass_cmd_filtering.1879401177
Short name	T1549
Test name
Test status
Simulation time	7326028895 ps
CPU time	9.77 seconds
Started	Jan 07 01:21:50 PM PST 24
Finished	Jan 07 01:22:02 PM PST 24
Peak memory	239752 kb
Host	smart-f5208c70-f7ab-4c50-b63f-477bbba5c354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879401177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1879401177
Directory	/workspace/23.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/23.spi_device_perf.3157831426
Short name	T968
Test name
Test status
Simulation time	79651273734 ps
CPU time	487.58 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:30:26 PM PST 24
Peak memory	257000 kb
Host	smart-d2e5db33-fa5f-4138-9fa3-6095faea0c9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157831426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_perf.3157831426
Directory	/workspace/23.spi_device_perf/latest

Test location	/workspace/coverage/default/23.spi_device_read_buffer_direct.374021892
Short name	T1133
Test name
Test status
Simulation time	15115545683 ps
CPU time	7.01 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:23 PM PST 24
Peak memory	234740 kb
Host	smart-507b022d-ed47-4d0f-a7c8-3bf5f689facc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=374021892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire ct.374021892
Directory	/workspace/23.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/23.spi_device_rx_async_fifo_reset.465408427
Short name	T1599
Test name
Test status
Simulation time	41071528 ps
CPU time	0.88 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:30 PM PST 24
Peak memory	208436 kb
Host	smart-5d641d9c-a8a3-46ae-977e-ff6902938c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465408427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_async_fifo_reset.465408427
Directory	/workspace/23.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/23.spi_device_rx_timeout.4102265900
Short name	T692
Test name
Test status
Simulation time	4809622143 ps
CPU time	5.16 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:21:47 PM PST 24
Peak memory	216964 kb
Host	smart-8b0dac29-18d9-42ab-8275-1b7ab30977be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102265900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_rx_timeout.4102265900
Directory	/workspace/23.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/23.spi_device_smoke.2557083550
Short name	T867
Test name
Test status
Simulation time	53817272 ps
CPU time	1.18 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	216592 kb
Host	smart-de353182-0385-45e9-a8d8-b54d42a749c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557083550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_smoke.2557083550
Directory	/workspace/23.spi_device_smoke/latest

Test location	/workspace/coverage/default/23.spi_device_stress_all.2439382769
Short name	T340
Test name
Test status
Simulation time	85625520831 ps
CPU time	877.44 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:36:53 PM PST 24
Peak memory	450884 kb
Host	smart-fdcc8ced-d57d-46a4-b02d-f030051ae3ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439382769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre ss_all.2439382769
Directory	/workspace/23.spi_device_stress_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_all.3405675969
Short name	T342
Test name
Test status
Simulation time	14745401096 ps
CPU time	41.67 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	217092 kb
Host	smart-f4068862-7bd0-45d8-92ec-1fbf7f1f9896
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405675969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3405675969
Directory	/workspace/23.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.569075975
Short name	T913
Test name
Test status
Simulation time	13416012527 ps
CPU time	29.33 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:23:01 PM PST 24
Peak memory	216708 kb
Host	smart-b01bad87-ed67-428a-bd93-0a31cb3562e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569075975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.569075975
Directory	/workspace/23.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_rw.3337569501
Short name	T1570
Test name
Test status
Simulation time	393596302 ps
CPU time	1.74 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:31 PM PST 24
Peak memory	216812 kb
Host	smart-daccace2-f730-47f2-bb0c-9c3816a75f9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337569501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3337569501
Directory	/workspace/23.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_sts_read.3951333631
Short name	T1709
Test name
Test status
Simulation time	286285572 ps
CPU time	0.83 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:22:36 PM PST 24
Peak memory	206732 kb
Host	smart-8ee4074c-6e50-4283-8132-7c92430fe2ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951333631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3951333631
Directory	/workspace/23.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/23.spi_device_tx_async_fifo_reset.1587506017
Short name	T70
Test name
Test status
Simulation time	57723759 ps
CPU time	0.8 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:30 PM PST 24
Peak memory	208448 kb
Host	smart-c96318cc-fd23-4e65-bf87-f2ea82e40663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587506017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tx_async_fifo_reset.1587506017
Directory	/workspace/23.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/23.spi_device_txrx.3932328454
Short name	T724
Test name
Test status
Simulation time	113271634290 ps
CPU time	74.16 seconds
Started	Jan 07 01:21:38 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	249764 kb
Host	smart-b3be1fdd-be8a-4124-947d-6d596a9a605e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932328454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_txrx.3932328454
Directory	/workspace/23.spi_device_txrx/latest

Test location	/workspace/coverage/default/23.spi_device_upload.3088111666
Short name	T221
Test name
Test status
Simulation time	3638794935 ps
CPU time	7.53 seconds
Started	Jan 07 01:21:52 PM PST 24
Finished	Jan 07 01:22:01 PM PST 24
Peak memory	219372 kb
Host	smart-48012f3c-dad9-42e2-985f-537e22027785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088111666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3088111666
Directory	/workspace/23.spi_device_upload/latest

Test location	/workspace/coverage/default/24.spi_device_abort.2452893754
Short name	T34
Test name
Test status
Simulation time	114076235 ps
CPU time	0.74 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	206608 kb
Host	smart-0055e6d2-479f-4976-b60d-1105f694d40f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452893754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_abort.2452893754
Directory	/workspace/24.spi_device_abort/latest

Test location	/workspace/coverage/default/24.spi_device_alert_test.1130306970
Short name	T75
Test name
Test status
Simulation time	13012859 ps
CPU time	0.71 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:16 PM PST 24
Peak memory	206388 kb
Host	smart-b8486263-2743-4a47-8a05-9e527a19ffb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130306970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test. 1130306970
Directory	/workspace/24.spi_device_alert_test/latest

Test location	/workspace/coverage/default/24.spi_device_bit_transfer.2282705032
Short name	T680
Test name
Test status
Simulation time	310016471 ps
CPU time	1.85 seconds
Started	Jan 07 01:22:08 PM PST 24
Finished	Jan 07 01:22:14 PM PST 24
Peak memory	216784 kb
Host	smart-3d73a382-4358-4524-8cdd-1e7aec46df6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282705032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_bit_transfer.2282705032
Directory	/workspace/24.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/24.spi_device_byte_transfer.3622855602
Short name	T1509
Test name
Test status
Simulation time	220691170 ps
CPU time	2.96 seconds
Started	Jan 07 01:21:51 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	216820 kb
Host	smart-0a5dd3a4-66cb-4b70-ae3f-08d0f4d429aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622855602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_byte_transfer.3622855602
Directory	/workspace/24.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/24.spi_device_cfg_cmd.3368035179
Short name	T1320
Test name
Test status
Simulation time	297725350 ps
CPU time	2.54 seconds
Started	Jan 07 01:21:41 PM PST 24
Finished	Jan 07 01:21:47 PM PST 24
Peak memory	219492 kb
Host	smart-2574337e-481b-4555-8902-d55daede183b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368035179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3368035179
Directory	/workspace/24.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/24.spi_device_csb_read.3909869478
Short name	T648
Test name
Test status
Simulation time	53518695 ps
CPU time	0.81 seconds
Started	Jan 07 01:21:40 PM PST 24
Finished	Jan 07 01:21:45 PM PST 24
Peak memory	206520 kb
Host	smart-23d2a12f-92c7-4c7f-b0b4-da9a068ac6e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909869478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3909869478
Directory	/workspace/24.spi_device_csb_read/latest

Test location	/workspace/coverage/default/24.spi_device_dummy_item_extra_dly.838229399
Short name	T1193
Test name
Test status
Simulation time	84442982061 ps
CPU time	356.96 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:28:12 PM PST 24
Peak memory	269064 kb
Host	smart-e0af6a10-1713-44cd-943f-a724345e73c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838229399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_dummy_item_extra_dly.838229399
Directory	/workspace/24.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/24.spi_device_extreme_fifo_size.2355678288
Short name	T1154
Test name
Test status
Simulation time	228204326568 ps
CPU time	937.32 seconds
Started	Jan 07 01:22:15 PM PST 24
Finished	Jan 07 01:37:58 PM PST 24
Peak memory	219008 kb
Host	smart-95744b5a-2937-43bd-83f0-62c8f42d7021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355678288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_extreme_fifo_size.2355678288
Directory	/workspace/24.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/24.spi_device_fifo_full.3313729366
Short name	T1530
Test name
Test status
Simulation time	22616898255 ps
CPU time	1116.07 seconds
Started	Jan 07 01:22:15 PM PST 24
Finished	Jan 07 01:40:57 PM PST 24
Peak memory	302084 kb
Host	smart-2eee7010-9234-4416-88e5-e89c3402cf2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313729366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_full.3313729366
Directory	/workspace/24.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/24.spi_device_fifo_underflow_overflow.1142857646
Short name	T56
Test name
Test status
Simulation time	15172755891 ps
CPU time	177.85 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	361676 kb
Host	smart-80c59dcf-025d-4d4f-8b75-05518cce3960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142857646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_fifo_underflow_overf low.1142857646
Directory	/workspace/24.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/24.spi_device_flash_all.2097114086
Short name	T1198
Test name
Test status
Simulation time	1614591015 ps
CPU time	12.28 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:22:31 PM PST 24
Peak memory	237204 kb
Host	smart-9b050305-f74a-47f9-a651-6dacbd074057
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097114086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2097114086
Directory	/workspace/24.spi_device_flash_all/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm.2500254079
Short name	T1540
Test name
Test status
Simulation time	2762216592 ps
CPU time	70.95 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:23:24 PM PST 24
Peak memory	249852 kb
Host	smart-be982f93-c754-4946-af8a-e626307f553e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500254079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2500254079
Directory	/workspace/24.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2763182746
Short name	T248
Test name
Test status
Simulation time	40404241992 ps
CPU time	165.56 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:25:00 PM PST 24
Peak memory	257932 kb
Host	smart-44396e6e-a62b-45d2-8fb6-1757dc89a003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763182746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl e.2763182746
Directory	/workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/24.spi_device_flash_mode.987769709
Short name	T777
Test name
Test status
Simulation time	1055452423 ps
CPU time	14.16 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	238152 kb
Host	smart-0dcf89ff-5e9d-4f89-bed3-718986d7587b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987769709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.987769709
Directory	/workspace/24.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/24.spi_device_intercept.3088273536
Short name	T1462
Test name
Test status
Simulation time	4322945697 ps
CPU time	7.25 seconds
Started	Jan 07 01:21:53 PM PST 24
Finished	Jan 07 01:22:02 PM PST 24
Peak memory	220692 kb
Host	smart-bbfa9ff1-15e9-45cc-8657-2063bfec4ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088273536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3088273536
Directory	/workspace/24.spi_device_intercept/latest

Test location	/workspace/coverage/default/24.spi_device_intr.3215760579
Short name	T978
Test name
Test status
Simulation time	11972173393 ps
CPU time	50.66 seconds
Started	Jan 07 01:21:52 PM PST 24
Finished	Jan 07 01:22:45 PM PST 24
Peak memory	232296 kb
Host	smart-0190ab43-1847-4223-a7bc-908752c73dd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215760579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intr.3215760579
Directory	/workspace/24.spi_device_intr/latest

Test location	/workspace/coverage/default/24.spi_device_mailbox.1409236199
Short name	T1101
Test name
Test status
Simulation time	2638747854 ps
CPU time	4.57 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:22:22 PM PST 24
Peak memory	226444 kb
Host	smart-483bf877-022d-4dc3-9661-c707333d3f74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409236199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1409236199
Directory	/workspace/24.spi_device_mailbox/latest

Test location	/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.259335000
Short name	T97
Test name
Test status
Simulation time	187987236 ps
CPU time	4.13 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:17 PM PST 24
Peak memory	225148 kb
Host	smart-06b11c3e-18c0-4113-8d40-82bbe213230d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259335000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap .259335000
Directory	/workspace/24.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/24.spi_device_pass_cmd_filtering.1718792075
Short name	T1451
Test name
Test status
Simulation time	8717357355 ps
CPU time	15.07 seconds
Started	Jan 07 01:22:22 PM PST 24
Finished	Jan 07 01:22:47 PM PST 24
Peak memory	240972 kb
Host	smart-654d1375-72ee-426a-b6c0-6fac9bfebf76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718792075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1718792075
Directory	/workspace/24.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/24.spi_device_perf.2103550547
Short name	T201
Test name
Test status
Simulation time	3649352088 ps
CPU time	249.48 seconds
Started	Jan 07 01:21:50 PM PST 24
Finished	Jan 07 01:26:02 PM PST 24
Peak memory	241540 kb
Host	smart-4599f635-2352-41aa-adab-b4100af1df4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103550547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_perf.2103550547
Directory	/workspace/24.spi_device_perf/latest

Test location	/workspace/coverage/default/24.spi_device_read_buffer_direct.450441890
Short name	T37
Test name
Test status
Simulation time	162589803 ps
CPU time	3.64 seconds
Started	Jan 07 01:21:54 PM PST 24
Finished	Jan 07 01:22:01 PM PST 24
Peak memory	218776 kb
Host	smart-8e9b0d25-f682-4e82-b590-b43880f30f58
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=450441890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire ct.450441890
Directory	/workspace/24.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/24.spi_device_rx_async_fifo_reset.2108196139
Short name	T1506
Test name
Test status
Simulation time	36617174 ps
CPU time	0.92 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:15 PM PST 24
Peak memory	208432 kb
Host	smart-11153065-0d68-4643-89ec-dcd222342f88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108196139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_async_fifo_reset.2108196139
Directory	/workspace/24.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/24.spi_device_rx_timeout.2552236069
Short name	T511
Test name
Test status
Simulation time	3515723287 ps
CPU time	5.26 seconds
Started	Jan 07 01:21:53 PM PST 24
Finished	Jan 07 01:22:01 PM PST 24
Peak memory	216904 kb
Host	smart-8a1462be-83a6-43b2-b59c-5fde1efdbc12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2552236069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_rx_timeout.2552236069
Directory	/workspace/24.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/24.spi_device_smoke.1582686768
Short name	T1397
Test name
Test status
Simulation time	299152689 ps
CPU time	1.1 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:15 PM PST 24
Peak memory	216520 kb
Host	smart-c4157e2c-4380-4501-9f51-335b3b1aa459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582686768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_smoke.1582686768
Directory	/workspace/24.spi_device_smoke/latest

Test location	/workspace/coverage/default/24.spi_device_stress_all.2426817187
Short name	T1344
Test name
Test status
Simulation time	25430155723 ps
CPU time	262.09 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:26:37 PM PST 24
Peak memory	282672 kb
Host	smart-9ac49388-3ba0-4195-8448-0e6b381ac944
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426817187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre ss_all.2426817187
Directory	/workspace/24.spi_device_stress_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_all.2180136046
Short name	T952
Test name
Test status
Simulation time	12146193230 ps
CPU time	50.9 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:23:06 PM PST 24
Peak memory	216956 kb
Host	smart-9c9d331f-bc92-4a27-8d9e-e5ab6534b14c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180136046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2180136046
Directory	/workspace/24.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1772254618
Short name	T1181
Test name
Test status
Simulation time	2246162626 ps
CPU time	5.93 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:21 PM PST 24
Peak memory	216748 kb
Host	smart-e5adc1fc-6324-4060-adf7-597c1277ffac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772254618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1772254618
Directory	/workspace/24.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_rw.3206473845
Short name	T533
Test name
Test status
Simulation time	247672882 ps
CPU time	2.43 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	216760 kb
Host	smart-8b8e9f3c-1dfd-4293-953f-3f8862569abd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206473845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3206473845
Directory	/workspace/24.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_sts_read.206498078
Short name	T99
Test name
Test status
Simulation time	81806562 ps
CPU time	0.83 seconds
Started	Jan 07 01:21:54 PM PST 24
Finished	Jan 07 01:21:58 PM PST 24
Peak memory	206840 kb
Host	smart-de298ad3-86d7-4c40-a88f-b30c8b786fb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206498078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.206498078
Directory	/workspace/24.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/24.spi_device_tx_async_fifo_reset.3253946718
Short name	T71
Test name
Test status
Simulation time	13666533 ps
CPU time	0.76 seconds
Started	Jan 07 01:21:51 PM PST 24
Finished	Jan 07 01:21:54 PM PST 24
Peak memory	208496 kb
Host	smart-bd16d315-cd94-4dfc-b5d6-a83f192ee86e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253946718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tx_async_fifo_reset.3253946718
Directory	/workspace/24.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/24.spi_device_txrx.1185964065
Short name	T833
Test name
Test status
Simulation time	81829858514 ps
CPU time	192.43 seconds
Started	Jan 07 01:21:53 PM PST 24
Finished	Jan 07 01:25:08 PM PST 24
Peak memory	274124 kb
Host	smart-2fc8e9db-433b-4b25-b869-f92853d1ea13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185964065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_txrx.1185964065
Directory	/workspace/24.spi_device_txrx/latest

Test location	/workspace/coverage/default/24.spi_device_upload.162985868
Short name	T1740
Test name
Test status
Simulation time	4164292872 ps
CPU time	6.14 seconds
Started	Jan 07 01:22:09 PM PST 24
Finished	Jan 07 01:22:21 PM PST 24
Peak memory	241520 kb
Host	smart-daf9ee48-c6a2-48bc-ae45-6d84ca70df5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162985868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.162985868
Directory	/workspace/24.spi_device_upload/latest

Test location	/workspace/coverage/default/25.spi_device_abort.4115370927
Short name	T490
Test name
Test status
Simulation time	86599383 ps
CPU time	0.8 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	206584 kb
Host	smart-484e9726-b990-44e9-a12d-0ab5da239d75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115370927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_abort.4115370927
Directory	/workspace/25.spi_device_abort/latest

Test location	/workspace/coverage/default/25.spi_device_alert_test.1084354586
Short name	T661
Test name
Test status
Simulation time	29095770 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:22:47 PM PST 24
Peak memory	206456 kb
Host	smart-5584f481-b02f-4bc9-80f8-e1db48c58852
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084354586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 1084354586
Directory	/workspace/25.spi_device_alert_test/latest

Test location	/workspace/coverage/default/25.spi_device_bit_transfer.1090591184
Short name	T1026
Test name
Test status
Simulation time	863153501 ps
CPU time	2.41 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:35 PM PST 24
Peak memory	216824 kb
Host	smart-2b16595a-c990-4d4e-bdd2-4e1b59cd1e27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090591184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_bit_transfer.1090591184
Directory	/workspace/25.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/25.spi_device_byte_transfer.1124564332
Short name	T448
Test name
Test status
Simulation time	594395473 ps
CPU time	3.17 seconds
Started	Jan 07 01:22:18 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	216808 kb
Host	smart-56e7476e-2c1f-4341-851b-6a4718176715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124564332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_byte_transfer.1124564332
Directory	/workspace/25.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/25.spi_device_cfg_cmd.515622269
Short name	T702
Test name
Test status
Simulation time	1844587898 ps
CPU time	5.47 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	221444 kb
Host	smart-f10b3117-9751-4c4f-a555-be514ebc0101
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515622269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.515622269
Directory	/workspace/25.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/25.spi_device_csb_read.4280191306
Short name	T1085
Test name
Test status
Simulation time	13615311 ps
CPU time	0.78 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	207604 kb
Host	smart-2e943af9-eade-4128-91f1-7b053e4aa789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280191306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4280191306
Directory	/workspace/25.spi_device_csb_read/latest

Test location	/workspace/coverage/default/25.spi_device_dummy_item_extra_dly.791381942
Short name	T548
Test name
Test status
Simulation time	27744066242 ps
CPU time	459.98 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:30:08 PM PST 24
Peak memory	267796 kb
Host	smart-b8435295-c059-43f4-bdeb-793fb5e690c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791381942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_dummy_item_extra_dly.791381942
Directory	/workspace/25.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/25.spi_device_extreme_fifo_size.2183305356
Short name	T1282
Test name
Test status
Simulation time	62266091746 ps
CPU time	1005.75 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:39:14 PM PST 24
Peak memory	220128 kb
Host	smart-90c9503b-6208-4c94-807c-4bbe7716675f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183305356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_extreme_fifo_size.2183305356
Directory	/workspace/25.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/25.spi_device_fifo_full.3149932366
Short name	T1471
Test name
Test status
Simulation time	60535906173 ps
CPU time	812.62 seconds
Started	Jan 07 01:22:30 PM PST 24
Finished	Jan 07 01:36:10 PM PST 24
Peak memory	263076 kb
Host	smart-5b902e05-d99f-46f2-bc0e-6c4ddaa1e2b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149932366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_full.3149932366
Directory	/workspace/25.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/25.spi_device_fifo_underflow_overflow.4189903023
Short name	T1703
Test name
Test status
Simulation time	104016574634 ps
CPU time	426.28 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:29:35 PM PST 24
Peak memory	374304 kb
Host	smart-b9bf8cfc-3f80-471c-b0d0-0340ba1ef5cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189903023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_fifo_underflow_overf low.4189903023
Directory	/workspace/25.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/25.spi_device_flash_all.3266477164
Short name	T1374
Test name
Test status
Simulation time	3115460683 ps
CPU time	30.1 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:23:10 PM PST 24
Peak memory	233288 kb
Host	smart-6ce9a016-fc1e-44c5-b36f-89c274379493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266477164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3266477164
Directory	/workspace/25.spi_device_flash_all/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm.4270003168
Short name	T601
Test name
Test status
Simulation time	24752758171 ps
CPU time	160.79 seconds
Started	Jan 07 01:22:46 PM PST 24
Finished	Jan 07 01:25:29 PM PST 24
Peak memory	250128 kb
Host	smart-174cb7c6-595c-4140-a699-cd4881d1ace8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270003168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4270003168
Directory	/workspace/25.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1397378452
Short name	T211
Test name
Test status
Simulation time	43109739945 ps
CPU time	334.34 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:28:25 PM PST 24
Peak memory	265280 kb
Host	smart-2c3b1ee9-e58e-45ae-aa63-7d6adc7bc49e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397378452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl e.1397378452
Directory	/workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/25.spi_device_flash_mode.83098638
Short name	T1300
Test name
Test status
Simulation time	369589345 ps
CPU time	14.2 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:52 PM PST 24
Peak memory	237392 kb
Host	smart-73f01501-32c5-473a-acc3-b38fc0d59918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83098638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.83098638
Directory	/workspace/25.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/25.spi_device_intercept.576093272
Short name	T21
Test name
Test status
Simulation time	214909462 ps
CPU time	2.99 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:41 PM PST 24
Peak memory	234320 kb
Host	smart-537c48a5-fd1c-4e76-b4f2-d1d541146747
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576093272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.576093272
Directory	/workspace/25.spi_device_intercept/latest

Test location	/workspace/coverage/default/25.spi_device_intr.3771391043
Short name	T1580
Test name
Test status
Simulation time	15623233392 ps
CPU time	14.99 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	216872 kb
Host	smart-d9fadc2d-68b9-4360-aa1d-91fde8487ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771391043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intr.3771391043
Directory	/workspace/25.spi_device_intr/latest

Test location	/workspace/coverage/default/25.spi_device_mailbox.1300887736
Short name	T740
Test name
Test status
Simulation time	2563904757 ps
CPU time	7.9 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	219636 kb
Host	smart-bdcb3f46-1195-4dc1-8a03-71ab8dc93a5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300887736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1300887736
Directory	/workspace/25.spi_device_mailbox/latest

Test location	/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3701338828
Short name	T1517
Test name
Test status
Simulation time	2677086503 ps
CPU time	10.17 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:50 PM PST 24
Peak memory	218424 kb
Host	smart-9f2802ac-2246-46ae-98a1-6cc405e03135
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701338828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa p.3701338828
Directory	/workspace/25.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/25.spi_device_pass_cmd_filtering.711292090
Short name	T223
Test name
Test status
Simulation time	11753393538 ps
CPU time	15.95 seconds
Started	Jan 07 01:22:38 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	219440 kb
Host	smart-bbdd749d-7f46-4d8e-b080-deeaccc3b408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711292090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.711292090
Directory	/workspace/25.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/25.spi_device_perf.401783132
Short name	T676
Test name
Test status
Simulation time	46622528012 ps
CPU time	1174.76 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:42:02 PM PST 24
Peak memory	282144 kb
Host	smart-6763c77b-dc21-4bd9-a872-db8c66effeb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401783132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_perf.401783132
Directory	/workspace/25.spi_device_perf/latest

Test location	/workspace/coverage/default/25.spi_device_read_buffer_direct.807361727
Short name	T990
Test name
Test status
Simulation time	883640725 ps
CPU time	6.47 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:46 PM PST 24
Peak memory	234452 kb
Host	smart-fe731361-f22a-4ee3-a516-7435a1119b26
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=807361727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire ct.807361727
Directory	/workspace/25.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/25.spi_device_rx_async_fifo_reset.2116462338
Short name	T803
Test name
Test status
Simulation time	48528557 ps
CPU time	0.87 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	208408 kb
Host	smart-1be84c89-f479-4175-924e-4ae383f1c637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116462338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_async_fifo_reset.2116462338
Directory	/workspace/25.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/25.spi_device_rx_timeout.815865582
Short name	T928
Test name
Test status
Simulation time	1449821358 ps
CPU time	6.3 seconds
Started	Jan 07 01:22:31 PM PST 24
Finished	Jan 07 01:22:44 PM PST 24
Peak memory	216808 kb
Host	smart-87cbc641-d419-4480-be84-0200f6ceff63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815865582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_rx_timeout.815865582
Directory	/workspace/25.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/25.spi_device_smoke.2439755114
Short name	T541
Test name
Test status
Simulation time	262216971 ps
CPU time	1.22 seconds
Started	Jan 07 01:21:52 PM PST 24
Finished	Jan 07 01:21:56 PM PST 24
Peak memory	216532 kb
Host	smart-9da8d6fa-980a-41bd-b84d-39b887593dda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439755114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_smoke.2439755114
Directory	/workspace/25.spi_device_smoke/latest

Test location	/workspace/coverage/default/25.spi_device_stress_all.1878859677
Short name	T1268
Test name
Test status
Simulation time	137341980402 ps
CPU time	2216.61 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:59:49 PM PST 24
Peak memory	431324 kb
Host	smart-c61d4c30-87cc-44c8-b264-120f79f3881d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878859677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre ss_all.1878859677
Directory	/workspace/25.spi_device_stress_all/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_all.1831153460
Short name	T1708
Test name
Test status
Simulation time	3013681586 ps
CPU time	28.52 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	217076 kb
Host	smart-d70e0c18-b4f2-407a-8dc5-828eceecf30b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831153460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1831153460
Directory	/workspace/25.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3254430059
Short name	T611
Test name
Test status
Simulation time	20007820644 ps
CPU time	13.46 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	216824 kb
Host	smart-9da43052-599d-47cd-b556-00a47d7c4f29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254430059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3254430059
Directory	/workspace/25.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_rw.3520180565
Short name	T890
Test name
Test status
Simulation time	282967875 ps
CPU time	3.2 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	216836 kb
Host	smart-5358b183-1181-4206-9f94-69ad21b2c726
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520180565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3520180565
Directory	/workspace/25.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_sts_read.404465455
Short name	T1434
Test name
Test status
Simulation time	39100478 ps
CPU time	0.79 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	206860 kb
Host	smart-c634eaaa-f662-42a4-bf9c-789455867eb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404465455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.404465455
Directory	/workspace/25.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/25.spi_device_tx_async_fifo_reset.1262087968
Short name	T1681
Test name
Test status
Simulation time	16535576 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:24 PM PST 24
Finished	Jan 07 01:22:33 PM PST 24
Peak memory	208508 kb
Host	smart-66823717-9b6a-4941-a56a-007b27f22a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262087968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tx_async_fifo_reset.1262087968
Directory	/workspace/25.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/25.spi_device_txrx.577039362
Short name	T179
Test name
Test status
Simulation time	22223029992 ps
CPU time	151.08 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:24:49 PM PST 24
Peak memory	290148 kb
Host	smart-b0871204-7a88-4756-92b8-978fcb7ddb55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577039362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_txrx.577039362
Directory	/workspace/25.spi_device_txrx/latest

Test location	/workspace/coverage/default/25.spi_device_upload.4250282470
Short name	T534
Test name
Test status
Simulation time	1304843897 ps
CPU time	6.92 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:22:42 PM PST 24
Peak memory	236388 kb
Host	smart-5df713a6-2691-4762-bb61-32c1db5ed8d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250282470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4250282470
Directory	/workspace/25.spi_device_upload/latest

Test location	/workspace/coverage/default/26.spi_device_abort.3596321736
Short name	T1676
Test name
Test status
Simulation time	53872380 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	206488 kb
Host	smart-a5c130c9-b33b-49b4-be75-9ad82885bdac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596321736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_abort.3596321736
Directory	/workspace/26.spi_device_abort/latest

Test location	/workspace/coverage/default/26.spi_device_alert_test.863965683
Short name	T76
Test name
Test status
Simulation time	12946499 ps
CPU time	0.72 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	206544 kb
Host	smart-7da183f4-8c9e-4794-8469-994ff45aa978
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863965683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.863965683
Directory	/workspace/26.spi_device_alert_test/latest

Test location	/workspace/coverage/default/26.spi_device_bit_transfer.3727060664
Short name	T1316
Test name
Test status
Simulation time	278016015 ps
CPU time	2.14 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	216752 kb
Host	smart-46d66163-0a4c-4f26-a8c9-a3a0161490d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727060664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.3727060664
Directory	/workspace/26.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/26.spi_device_byte_transfer.2629286323
Short name	T1231
Test name
Test status
Simulation time	2037166283 ps
CPU time	2.7 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:22:19 PM PST 24
Peak memory	216848 kb
Host	smart-bcd8ee69-a60a-44b6-8bff-c6108c4d9420
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629286323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_byte_transfer.2629286323
Directory	/workspace/26.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/26.spi_device_cfg_cmd.2804642864
Short name	T804
Test name
Test status
Simulation time	2925728071 ps
CPU time	5.4 seconds
Started	Jan 07 01:22:16 PM PST 24
Finished	Jan 07 01:22:27 PM PST 24
Peak memory	219376 kb
Host	smart-663b5eb7-df47-40d5-ba84-94d4fecf0edf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804642864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2804642864
Directory	/workspace/26.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/26.spi_device_csb_read.4051739482
Short name	T1031
Test name
Test status
Simulation time	31763337 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	207496 kb
Host	smart-9956fe99-bd3a-493f-81d8-f946df64a4f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051739482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4051739482
Directory	/workspace/26.spi_device_csb_read/latest

Test location	/workspace/coverage/default/26.spi_device_dummy_item_extra_dly.4130707866
Short name	T620
Test name
Test status
Simulation time	61578674133 ps
CPU time	1409.83 seconds
Started	Jan 07 01:22:10 PM PST 24
Finished	Jan 07 01:45:47 PM PST 24
Peak memory	255736 kb
Host	smart-1aef9af3-3206-4d39-83a8-482a9f5b8511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130707866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_dummy_item_extra_dly.4130707866
Directory	/workspace/26.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/26.spi_device_extreme_fifo_size.3965720223
Short name	T1098
Test name
Test status
Simulation time	268108544973 ps
CPU time	915.87 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:37:34 PM PST 24
Peak memory	220092 kb
Host	smart-08385a0e-4bec-497a-bdb7-35b7a8b9d0a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965720223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_extreme_fifo_size.3965720223
Directory	/workspace/26.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/26.spi_device_fifo_full.259348540
Short name	T466
Test name
Test status
Simulation time	760945417468 ps
CPU time	1014.49 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:39:12 PM PST 24
Peak memory	273932 kb
Host	smart-f6b905c8-954e-4e8d-8f79-9e3f255856d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259348540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_full.259348540
Directory	/workspace/26.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/26.spi_device_fifo_underflow_overflow.351961367
Short name	T53
Test name
Test status
Simulation time	194066958959 ps
CPU time	443.41 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:29:40 PM PST 24
Peak memory	405496 kb
Host	smart-a8a67caf-8ba2-4003-afc0-9dec92c72683
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351961367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_fifo_underflow_overfl ow.351961367
Directory	/workspace/26.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/26.spi_device_flash_all.1102599228
Short name	T216
Test name
Test status
Simulation time	13726793902 ps
CPU time	62.93 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:23:35 PM PST 24
Peak memory	254368 kb
Host	smart-726f39d3-e17b-4259-85d0-dc50c2b6d54b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102599228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1102599228
Directory	/workspace/26.spi_device_flash_all/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm.4213442238
Short name	T1087
Test name
Test status
Simulation time	3444877141 ps
CPU time	84.45 seconds
Started	Jan 07 01:22:17 PM PST 24
Finished	Jan 07 01:23:48 PM PST 24
Peak memory	257068 kb
Host	smart-e28636c0-fde3-4923-8789-727cef686c54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213442238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4213442238
Directory	/workspace/26.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1771283331
Short name	T313
Test name
Test status
Simulation time	62155261319 ps
CPU time	208.26 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:25:56 PM PST 24
Peak memory	282264 kb
Host	smart-d86b4f32-3df6-4fa4-9de1-3dd8bf8baea2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771283331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl e.1771283331
Directory	/workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/26.spi_device_flash_mode.2793054637
Short name	T956
Test name
Test status
Simulation time	10688443972 ps
CPU time	56.36 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:23:24 PM PST 24
Peak memory	250832 kb
Host	smart-ca62e1b7-066d-4c35-bae0-004e92d55a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793054637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2793054637
Directory	/workspace/26.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/26.spi_device_intercept.1851597412
Short name	T591
Test name
Test status
Simulation time	4175289042 ps
CPU time	8.84 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:37 PM PST 24
Peak memory	236440 kb
Host	smart-d58b79c0-2c78-4847-b25c-e155d3ef77a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851597412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1851597412
Directory	/workspace/26.spi_device_intercept/latest

Test location	/workspace/coverage/default/26.spi_device_intr.890244265
Short name	T918
Test name
Test status
Simulation time	39821716286 ps
CPU time	34.88 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:23:02 PM PST 24
Peak memory	240784 kb
Host	smart-3e5b6e80-0061-493d-9bf0-d924e2ae44ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890244265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intr.890244265
Directory	/workspace/26.spi_device_intr/latest

Test location	/workspace/coverage/default/26.spi_device_mailbox.2435417149
Short name	T301
Test name
Test status
Simulation time	7948661801 ps
CPU time	23.92 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	243908 kb
Host	smart-afe1b79d-b7a1-4075-b9d6-0fad51e97e7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435417149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2435417149
Directory	/workspace/26.spi_device_mailbox/latest

Test location	/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3819940538
Short name	T766
Test name
Test status
Simulation time	12171142950 ps
CPU time	8.18 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:25 PM PST 24
Peak memory	222236 kb
Host	smart-2a437f7d-b8db-4cd0-80ef-82ac54fbaba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819940538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa p.3819940538
Directory	/workspace/26.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/26.spi_device_pass_cmd_filtering.1537898908
Short name	T115
Test name
Test status
Simulation time	7509148192 ps
CPU time	13.48 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:31 PM PST 24
Peak memory	241464 kb
Host	smart-5747132a-ebf8-4748-83a4-72ce01091232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537898908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1537898908
Directory	/workspace/26.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/26.spi_device_perf.1320841410
Short name	T1248
Test name
Test status
Simulation time	49841112043 ps
CPU time	885.98 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:37:13 PM PST 24
Peak memory	289908 kb
Host	smart-c3120c2f-b20a-4c8d-a38e-e8e63d12279e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320841410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_perf.1320841410
Directory	/workspace/26.spi_device_perf/latest

Test location	/workspace/coverage/default/26.spi_device_read_buffer_direct.4067513930
Short name	T1042
Test name
Test status
Simulation time	442930293 ps
CPU time	4.18 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:31 PM PST 24
Peak memory	234428 kb
Host	smart-fd3bd394-fc79-4505-8366-d2af9f6ea5bc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4067513930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir ect.4067513930
Directory	/workspace/26.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/26.spi_device_rx_async_fifo_reset.2541885544
Short name	T477
Test name
Test status
Simulation time	26901482 ps
CPU time	0.91 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	208396 kb
Host	smart-f8a0e478-920b-4c0d-97f4-fa36c99ad629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541885544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_async_fifo_reset.2541885544
Directory	/workspace/26.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/26.spi_device_rx_timeout.4196996854
Short name	T1487
Test name
Test status
Simulation time	7374562327 ps
CPU time	6.96 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:34 PM PST 24
Peak memory	216804 kb
Host	smart-c3be39e0-7f4b-4074-bdba-2ce2953dd4ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196996854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_rx_timeout.4196996854
Directory	/workspace/26.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/26.spi_device_smoke.3361201983
Short name	T1160
Test name
Test status
Simulation time	39247808 ps
CPU time	0.95 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	208264 kb
Host	smart-986a6fb2-2a99-4452-9fa4-7ca9ba9e9dca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361201983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_smoke.3361201983
Directory	/workspace/26.spi_device_smoke/latest

Test location	/workspace/coverage/default/26.spi_device_stress_all.305996028
Short name	T317
Test name
Test status
Simulation time	114897768253 ps
CPU time	415.49 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:29:25 PM PST 24
Peak memory	356636 kb
Host	smart-b8fb1206-9159-454e-a656-d8dab65b52c9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305996028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres s_all.305996028
Directory	/workspace/26.spi_device_stress_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_all.832161146
Short name	T891
Test name
Test status
Simulation time	6455907810 ps
CPU time	85.72 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:23:53 PM PST 24
Peak memory	216852 kb
Host	smart-d49fda1c-f1c5-49d1-8f86-8e6fdd807c6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832161146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.832161146
Directory	/workspace/26.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4245032758
Short name	T526
Test name
Test status
Simulation time	1175516143 ps
CPU time	5.86 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:33 PM PST 24
Peak memory	216780 kb
Host	smart-7a2ffc8e-094d-4166-9903-dc4de7cd4edf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245032758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4245032758
Directory	/workspace/26.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_rw.3447988863
Short name	T1093
Test name
Test status
Simulation time	3308417212 ps
CPU time	8.32 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:22:35 PM PST 24
Peak memory	216756 kb
Host	smart-ced872a5-3e30-4f32-af67-88ad3dc846a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447988863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3447988863
Directory	/workspace/26.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_sts_read.3910060146
Short name	T771
Test name
Test status
Simulation time	427055858 ps
CPU time	1 seconds
Started	Jan 07 01:22:11 PM PST 24
Finished	Jan 07 01:22:18 PM PST 24
Peak memory	206908 kb
Host	smart-e9103c94-3894-48fd-9b7d-f925ea56ed66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910060146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3910060146
Directory	/workspace/26.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/26.spi_device_tx_async_fifo_reset.659776580
Short name	T1068
Test name
Test status
Simulation time	13366084 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:28 PM PST 24
Peak memory	208320 kb
Host	smart-c23979ec-5efa-4434-b1e3-bffe3d65b802
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659776580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tx_async_fifo_reset.659776580
Directory	/workspace/26.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/26.spi_device_txrx.2103245654
Short name	T48
Test name
Test status
Simulation time	131469145458 ps
CPU time	255.23 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:26:42 PM PST 24
Peak memory	249136 kb
Host	smart-91e57407-4e9f-4269-8eed-d542be007c42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103245654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_txrx.2103245654
Directory	/workspace/26.spi_device_txrx/latest

Test location	/workspace/coverage/default/26.spi_device_upload.873157162
Short name	T760
Test name
Test status
Simulation time	25276511763 ps
CPU time	17.21 seconds
Started	Jan 07 01:22:12 PM PST 24
Finished	Jan 07 01:22:35 PM PST 24
Peak memory	222704 kb
Host	smart-eef2dbc3-ba1c-4943-9ae9-d407f01bc660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873157162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.873157162
Directory	/workspace/26.spi_device_upload/latest

Test location	/workspace/coverage/default/27.spi_device_abort.267594291
Short name	T731
Test name
Test status
Simulation time	37752198 ps
CPU time	0.74 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	206572 kb
Host	smart-354f0a73-5d01-4630-8ec1-732170fdfaf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267594291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_abort.267594291
Directory	/workspace/27.spi_device_abort/latest

Test location	/workspace/coverage/default/27.spi_device_alert_test.937059322
Short name	T1533
Test name
Test status
Simulation time	11183095 ps
CPU time	0.72 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	206436 kb
Host	smart-73e2668f-e72b-4b27-82c0-031edcfc0a1b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937059322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.937059322
Directory	/workspace/27.spi_device_alert_test/latest

Test location	/workspace/coverage/default/27.spi_device_bit_transfer.2935429045
Short name	T532
Test name
Test status
Simulation time	370042920 ps
CPU time	2.33 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:42 PM PST 24
Peak memory	216860 kb
Host	smart-28fe718d-fce7-4805-9207-960bb2bd4538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935429045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_bit_transfer.2935429045
Directory	/workspace/27.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/27.spi_device_byte_transfer.2315437090
Short name	T1424
Test name
Test status
Simulation time	135667060 ps
CPU time	2.96 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:22:38 PM PST 24
Peak memory	216896 kb
Host	smart-67b76a43-0053-42fb-b751-686303ac9a85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315437090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_byte_transfer.2315437090
Directory	/workspace/27.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/27.spi_device_cfg_cmd.181314734
Short name	T1421
Test name
Test status
Simulation time	731089247 ps
CPU time	3.93 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:22:50 PM PST 24
Peak memory	224932 kb
Host	smart-098571de-7dae-463b-86a5-0558c426b0f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181314734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.181314734
Directory	/workspace/27.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/27.spi_device_csb_read.2856995798
Short name	T1365
Test name
Test status
Simulation time	14098314 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	207436 kb
Host	smart-2aa6d7cb-cd7b-437f-9a30-3eb857bbbc0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856995798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2856995798
Directory	/workspace/27.spi_device_csb_read/latest

Test location	/workspace/coverage/default/27.spi_device_dummy_item_extra_dly.2808423780
Short name	T672
Test name
Test status
Simulation time	110731674594 ps
CPU time	450.71 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:30:11 PM PST 24
Peak memory	315388 kb
Host	smart-9a833394-6b22-465a-8813-f9ccf7b1601b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808423780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_dummy_item_extra_dly.2808423780
Directory	/workspace/27.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/27.spi_device_fifo_full.2854608388
Short name	T1219
Test name
Test status
Simulation time	24916342258 ps
CPU time	287.97 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:27:14 PM PST 24
Peak memory	273388 kb
Host	smart-7f0a896a-b94c-4bcc-98f1-a3f362e02cdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854608388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_full.2854608388
Directory	/workspace/27.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/27.spi_device_fifo_underflow_overflow.1053263239
Short name	T738
Test name
Test status
Simulation time	19264328540 ps
CPU time	236.25 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:26:31 PM PST 24
Peak memory	319388 kb
Host	smart-4f024c4a-ef8b-4a89-ac56-99b351cdba3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053263239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_fifo_underflow_overf low.1053263239
Directory	/workspace/27.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2064886131
Short name	T251
Test name
Test status
Simulation time	21934728122 ps
CPU time	169.51 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	252780 kb
Host	smart-8e53161c-7d1c-433a-9461-0b404290a0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064886131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl e.2064886131
Directory	/workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/27.spi_device_flash_mode.3260518343
Short name	T1298
Test name
Test status
Simulation time	5720610422 ps
CPU time	32.16 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:23:22 PM PST 24
Peak memory	256924 kb
Host	smart-dedfce83-c636-4880-9427-dd76127424d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260518343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3260518343
Directory	/workspace/27.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/27.spi_device_intercept.1949670961
Short name	T1491
Test name
Test status
Simulation time	149014450 ps
CPU time	4.38 seconds
Started	Jan 07 01:22:46 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	238544 kb
Host	smart-4d83827b-353d-4c50-9639-3d3c39e33b06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949670961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1949670961
Directory	/workspace/27.spi_device_intercept/latest

Test location	/workspace/coverage/default/27.spi_device_intr.939931740
Short name	T821
Test name
Test status
Simulation time	22654254741 ps
CPU time	102.01 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	246828 kb
Host	smart-d967e3b9-8ecf-40de-b9e7-624326d0f5d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939931740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intr.939931740
Directory	/workspace/27.spi_device_intr/latest

Test location	/workspace/coverage/default/27.spi_device_mailbox.1082113510
Short name	T555
Test name
Test status
Simulation time	1313037148 ps
CPU time	6.86 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	250576 kb
Host	smart-259942f5-cdfc-4488-9e15-bc7d4073a25a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082113510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1082113510
Directory	/workspace/27.spi_device_mailbox/latest

Test location	/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3531757994
Short name	T205
Test name
Test status
Simulation time	4888942705 ps
CPU time	17.56 seconds
Started	Jan 07 01:22:42 PM PST 24
Finished	Jan 07 01:23:03 PM PST 24
Peak memory	239372 kb
Host	smart-77e2cf53-3142-4cd0-acbd-04e69e19f3b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531757994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.3531757994
Directory	/workspace/27.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/27.spi_device_pass_cmd_filtering.3946692996
Short name	T1185
Test name
Test status
Simulation time	190179329 ps
CPU time	5.3 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:45 PM PST 24
Peak memory	241384 kb
Host	smart-9c6e794d-0989-45a0-97bc-9ef9df21c04b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946692996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3946692996
Directory	/workspace/27.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/27.spi_device_perf.4103154883
Short name	T1430
Test name
Test status
Simulation time	36995654742 ps
CPU time	169.2 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:25:27 PM PST 24
Peak memory	256892 kb
Host	smart-386b6d8a-fcda-4fc6-8eaa-931684cf44e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103154883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_perf.4103154883
Directory	/workspace/27.spi_device_perf/latest

Test location	/workspace/coverage/default/27.spi_device_read_buffer_direct.4077121745
Short name	T1360
Test name
Test status
Simulation time	3952394718 ps
CPU time	6.27 seconds
Started	Jan 07 01:22:45 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	237060 kb
Host	smart-ac36deb4-68ae-4ef3-b30e-b67c8c6975e8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4077121745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.4077121745
Directory	/workspace/27.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/27.spi_device_rx_async_fifo_reset.3325977851
Short name	T1194
Test name
Test status
Simulation time	171368174 ps
CPU time	0.92 seconds
Started	Jan 07 01:22:30 PM PST 24
Finished	Jan 07 01:22:38 PM PST 24
Peak memory	208552 kb
Host	smart-2dde9a20-fc86-40b9-b876-89db5c7af977
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325977851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_async_fifo_reset.3325977851
Directory	/workspace/27.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/27.spi_device_rx_timeout.618498096
Short name	T1459
Test name
Test status
Simulation time	1190515383 ps
CPU time	5.45 seconds
Started	Jan 07 01:22:36 PM PST 24
Finished	Jan 07 01:22:47 PM PST 24
Peak memory	216804 kb
Host	smart-317f6fc9-1a14-4cff-bd37-234c98dd4bca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618498096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_rx_timeout.618498096
Directory	/workspace/27.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/27.spi_device_smoke.2566401218
Short name	T801
Test name
Test status
Simulation time	126726692 ps
CPU time	1.03 seconds
Started	Jan 07 01:22:24 PM PST 24
Finished	Jan 07 01:22:34 PM PST 24
Peak memory	208368 kb
Host	smart-5f6fd56b-9997-47ea-9de0-ba531efcd9dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2566401218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_smoke.2566401218
Directory	/workspace/27.spi_device_smoke/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_all.4131683195
Short name	T1725
Test name
Test status
Simulation time	9810294625 ps
CPU time	44.29 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:23:16 PM PST 24
Peak memory	217056 kb
Host	smart-b9333ffe-3c6d-4fbc-a602-247fc2c7a298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131683195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4131683195
Directory	/workspace/27.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1805645083
Short name	T1127
Test name
Test status
Simulation time	1772777214 ps
CPU time	7.91 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	216808 kb
Host	smart-12518d4a-19e3-4634-b797-304dc42eafa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805645083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1805645083
Directory	/workspace/27.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_rw.3380146037
Short name	T944
Test name
Test status
Simulation time	1284854690 ps
CPU time	6.59 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:59 PM PST 24
Peak memory	216836 kb
Host	smart-851ea0e6-0098-451e-bd0b-8791ed7d300d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380146037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3380146037
Directory	/workspace/27.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_sts_read.1640165981
Short name	T1182
Test name
Test status
Simulation time	193139715 ps
CPU time	0.88 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:22:52 PM PST 24
Peak memory	206940 kb
Host	smart-b829adfb-f7fc-4a09-8c39-e132bec1db91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640165981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1640165981
Directory	/workspace/27.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/27.spi_device_tx_async_fifo_reset.2217310515
Short name	T1680
Test name
Test status
Simulation time	35114471 ps
CPU time	0.75 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	208412 kb
Host	smart-ef8e2fca-0b96-470e-85f6-1fdcabfaf130
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217310515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tx_async_fifo_reset.2217310515
Directory	/workspace/27.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/27.spi_device_txrx.2607262729
Short name	T1291
Test name
Test status
Simulation time	37312239008 ps
CPU time	143.99 seconds
Started	Jan 07 01:22:25 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	256328 kb
Host	smart-1f4ca0fc-4568-4a28-9365-1237fb06cdb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607262729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_txrx.2607262729
Directory	/workspace/27.spi_device_txrx/latest

Test location	/workspace/coverage/default/27.spi_device_upload.3133555139
Short name	T234
Test name
Test status
Simulation time	68266661748 ps
CPU time	35.42 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:23:26 PM PST 24
Peak memory	249732 kb
Host	smart-4476ddec-7ea6-4106-9a4b-12ae4607af8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133555139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3133555139
Directory	/workspace/27.spi_device_upload/latest

Test location	/workspace/coverage/default/28.spi_device_abort.649260635
Short name	T1285
Test name
Test status
Simulation time	90327577 ps
CPU time	0.78 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	206580 kb
Host	smart-7e0ef344-d428-4d89-adcc-765cc572aab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649260635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_abort.649260635
Directory	/workspace/28.spi_device_abort/latest

Test location	/workspace/coverage/default/28.spi_device_alert_test.3026847309
Short name	T1323
Test name
Test status
Simulation time	44473401 ps
CPU time	0.74 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	206452 kb
Host	smart-7650b4e8-65a5-4c56-8b69-ee4335ef19b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026847309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 3026847309
Directory	/workspace/28.spi_device_alert_test/latest

Test location	/workspace/coverage/default/28.spi_device_bit_transfer.3796820775
Short name	T826
Test name
Test status
Simulation time	240461012 ps
CPU time	2.1 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:22:28 PM PST 24
Peak memory	216824 kb
Host	smart-cb6f7cb9-47f0-43c6-b370-37d636f82b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796820775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_bit_transfer.3796820775
Directory	/workspace/28.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/28.spi_device_byte_transfer.3188259249
Short name	T1622
Test name
Test status
Simulation time	844441718 ps
CPU time	2.89 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	216784 kb
Host	smart-a2d5fb6b-4d68-49ce-848a-9eced659b641
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188259249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_byte_transfer.3188259249
Directory	/workspace/28.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/28.spi_device_cfg_cmd.4243351217
Short name	T1472
Test name
Test status
Simulation time	192298356 ps
CPU time	3.69 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	238580 kb
Host	smart-cc7131d1-6175-4c88-916f-83e99ae0c6ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243351217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4243351217
Directory	/workspace/28.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/28.spi_device_csb_read.938580898
Short name	T1138
Test name
Test status
Simulation time	65200082 ps
CPU time	0.75 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	206512 kb
Host	smart-a921e7c3-dcc3-43a4-ad76-b2c69ea52854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938580898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.938580898
Directory	/workspace/28.spi_device_csb_read/latest

Test location	/workspace/coverage/default/28.spi_device_dummy_item_extra_dly.3419191004
Short name	T1092
Test name
Test status
Simulation time	177856255166 ps
CPU time	507.96 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:31:08 PM PST 24
Peak memory	288748 kb
Host	smart-57fb7d4d-596f-4ab0-8b1e-8f7d720e67a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419191004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_dummy_item_extra_dly.3419191004
Directory	/workspace/28.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/28.spi_device_extreme_fifo_size.2293443634
Short name	T1159
Test name
Test status
Simulation time	25195725644 ps
CPU time	48.35 seconds
Started	Jan 07 01:22:24 PM PST 24
Finished	Jan 07 01:23:21 PM PST 24
Peak memory	241164 kb
Host	smart-df3842ae-c0c6-45e1-9757-41e19a038b0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293443634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_extreme_fifo_size.2293443634
Directory	/workspace/28.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/28.spi_device_fifo_full.1371011581
Short name	T1066
Test name
Test status
Simulation time	82689516470 ps
CPU time	891.21 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:37:18 PM PST 24
Peak memory	249840 kb
Host	smart-c900704a-b5ab-4cd4-a662-33259b363d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371011581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_full.1371011581
Directory	/workspace/28.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/28.spi_device_fifo_underflow_overflow.3813353176
Short name	T1525
Test name
Test status
Simulation time	92931867223 ps
CPU time	302.05 seconds
Started	Jan 07 01:22:18 PM PST 24
Finished	Jan 07 01:27:28 PM PST 24
Peak memory	391200 kb
Host	smart-99955202-fb33-4786-a8f5-3f535d3b2b4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813353176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_fifo_underflow_overf low.3813353176
Directory	/workspace/28.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/28.spi_device_flash_all.3233495010
Short name	T188
Test name
Test status
Simulation time	9804740393 ps
CPU time	101.84 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	273348 kb
Host	smart-c1be7384-9dba-4190-8cb4-db32d6cb147a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233495010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3233495010
Directory	/workspace/28.spi_device_flash_all/latest

Test location	/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3633396707
Short name	T220
Test name
Test status
Simulation time	233750274498 ps
CPU time	366.38 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:28:46 PM PST 24
Peak memory	267532 kb
Host	smart-95e5e4f2-2179-42a7-9cf9-3b9d78349713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633396707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl e.3633396707
Directory	/workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/28.spi_device_flash_mode.3176450051
Short name	T332
Test name
Test status
Simulation time	12421258921 ps
CPU time	17.89 seconds
Started	Jan 07 01:22:38 PM PST 24
Finished	Jan 07 01:23:02 PM PST 24
Peak memory	225180 kb
Host	smart-ff23febf-9083-423d-b7f3-17dc5aabaaff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176450051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3176450051
Directory	/workspace/28.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/28.spi_device_intercept.335331748
Short name	T230
Test name
Test status
Simulation time	452098874 ps
CPU time	4.82 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	220972 kb
Host	smart-0568898f-3ae0-48da-8b14-b74c9ef47ebe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335331748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.335331748
Directory	/workspace/28.spi_device_intercept/latest

Test location	/workspace/coverage/default/28.spi_device_intr.3667001414
Short name	T592
Test name
Test status
Simulation time	5096440635 ps
CPU time	26.14 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:23:05 PM PST 24
Peak memory	225148 kb
Host	smart-efe00f14-a787-4a0b-8bc3-51eaf16db6ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667001414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intr.3667001414
Directory	/workspace/28.spi_device_intr/latest

Test location	/workspace/coverage/default/28.spi_device_mailbox.3964334807
Short name	T279
Test name
Test status
Simulation time	4789511103 ps
CPU time	19.47 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	256836 kb
Host	smart-28c9d6d1-e4e6-4312-918e-48c9a21aa32c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964334807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3964334807
Directory	/workspace/28.spi_device_mailbox/latest

Test location	/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2205307777
Short name	T930
Test name
Test status
Simulation time	2342550124 ps
CPU time	7.01 seconds
Started	Jan 07 01:22:25 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	219712 kb
Host	smart-92f12f6c-e8fd-4db6-a402-431f14fc75f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205307777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa p.2205307777
Directory	/workspace/28.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/28.spi_device_pass_cmd_filtering.2795408380
Short name	T1272
Test name
Test status
Simulation time	38411849933 ps
CPU time	25.2 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:23:03 PM PST 24
Peak memory	246776 kb
Host	smart-7ca26d17-7e5d-4c02-8d26-efdabe02d87f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795408380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2795408380
Directory	/workspace/28.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/28.spi_device_perf.3535819552
Short name	T1450
Test name
Test status
Simulation time	39782719189 ps
CPU time	487.62 seconds
Started	Jan 07 01:22:27 PM PST 24
Finished	Jan 07 01:30:43 PM PST 24
Peak memory	279976 kb
Host	smart-322903c0-cafe-4b79-acbf-bb5573ef25c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535819552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_perf.3535819552
Directory	/workspace/28.spi_device_perf/latest

Test location	/workspace/coverage/default/28.spi_device_read_buffer_direct.590138514
Short name	T1413
Test name
Test status
Simulation time	917389256 ps
CPU time	5.13 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	218812 kb
Host	smart-1f7be44f-35c1-4014-bf15-d1963a418c8a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=590138514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire ct.590138514
Directory	/workspace/28.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/28.spi_device_rx_async_fifo_reset.40392299
Short name	T714
Test name
Test status
Simulation time	127929426 ps
CPU time	0.92 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:22:38 PM PST 24
Peak memory	208424 kb
Host	smart-09fb733f-55e0-4f94-a3ea-d36da4e7b999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40392299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_async_fifo_reset.40392299
Directory	/workspace/28.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/28.spi_device_rx_timeout.372209131
Short name	T970
Test name
Test status
Simulation time	1880303982 ps
CPU time	6.39 seconds
Started	Jan 07 01:22:20 PM PST 24
Finished	Jan 07 01:22:34 PM PST 24
Peak memory	216732 kb
Host	smart-860b3398-18ec-487a-bba2-0aee36296ae3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372209131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_rx_timeout.372209131
Directory	/workspace/28.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/28.spi_device_smoke.3003981761
Short name	T470
Test name
Test status
Simulation time	283611137 ps
CPU time	1.14 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:22:29 PM PST 24
Peak memory	216700 kb
Host	smart-12e60106-7377-4207-b9ee-08122cd24814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003981761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_smoke.3003981761
Directory	/workspace/28.spi_device_smoke/latest

Test location	/workspace/coverage/default/28.spi_device_stress_all.29871365
Short name	T298
Test name
Test status
Simulation time	835833751562 ps
CPU time	3500.91 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 02:20:55 PM PST 24
Peak memory	267796 kb
Host	smart-3d4c42b1-cd5a-47a5-8220-b2e050f591b5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29871365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress _all.29871365
Directory	/workspace/28.spi_device_stress_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_all.3793585684
Short name	T986
Test name
Test status
Simulation time	22184662891 ps
CPU time	51.89 seconds
Started	Jan 07 01:22:21 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	217004 kb
Host	smart-b80821d8-64f8-4501-975f-a552646044e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793585684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3793585684
Directory	/workspace/28.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.31876617
Short name	T1333
Test name
Test status
Simulation time	937554989 ps
CPU time	3.97 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:36 PM PST 24
Peak memory	216644 kb
Host	smart-beecd02c-e2be-4f66-8c79-7d5e5cbea53d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31876617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.31876617
Directory	/workspace/28.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_rw.230541998
Short name	T4
Test name
Test status
Simulation time	38593050 ps
CPU time	0.83 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:33 PM PST 24
Peak memory	206888 kb
Host	smart-3fb030a5-92ec-4826-868b-35a3e13b0032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230541998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.230541998
Directory	/workspace/28.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_sts_read.997427301
Short name	T884
Test name
Test status
Simulation time	176997412 ps
CPU time	0.79 seconds
Started	Jan 07 01:22:26 PM PST 24
Finished	Jan 07 01:22:35 PM PST 24
Peak memory	206944 kb
Host	smart-100412bc-69c3-4a29-8374-fdf21e532585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997427301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.997427301
Directory	/workspace/28.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/28.spi_device_tx_async_fifo_reset.3628109368
Short name	T772
Test name
Test status
Simulation time	13709606 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:23 PM PST 24
Finished	Jan 07 01:22:33 PM PST 24
Peak memory	208312 kb
Host	smart-33bb41ec-3593-465e-9eac-0dbd1f7ab9de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628109368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tx_async_fifo_reset.3628109368
Directory	/workspace/28.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/28.spi_device_txrx.3964593453
Short name	T1728
Test name
Test status
Simulation time	34917928793 ps
CPU time	723.23 seconds
Started	Jan 07 01:22:19 PM PST 24
Finished	Jan 07 01:34:30 PM PST 24
Peak memory	265732 kb
Host	smart-20053e96-c940-4adb-8c71-69fff7075378
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964593453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_txrx.3964593453
Directory	/workspace/28.spi_device_txrx/latest

Test location	/workspace/coverage/default/28.spi_device_upload.99705520
Short name	T289
Test name
Test status
Simulation time	598595705 ps
CPU time	3.96 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:44 PM PST 24
Peak memory	218172 kb
Host	smart-c9aea297-56ca-4aac-9539-a5f343192420
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99705520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.99705520
Directory	/workspace/28.spi_device_upload/latest

Test location	/workspace/coverage/default/29.spi_device_abort.1221280107
Short name	T1717
Test name
Test status
Simulation time	48834772 ps
CPU time	0.74 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	206676 kb
Host	smart-0a3070ef-acd7-4fe4-8d36-c207d9798897
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221280107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_abort.1221280107
Directory	/workspace/29.spi_device_abort/latest

Test location	/workspace/coverage/default/29.spi_device_alert_test.266383616
Short name	T847
Test name
Test status
Simulation time	37938480 ps
CPU time	0.72 seconds
Started	Jan 07 01:22:43 PM PST 24
Finished	Jan 07 01:22:47 PM PST 24
Peak memory	206464 kb
Host	smart-ac5580c4-9860-40e0-8f73-a87df83fd901
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266383616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.266383616
Directory	/workspace/29.spi_device_alert_test/latest

Test location	/workspace/coverage/default/29.spi_device_bit_transfer.493211421
Short name	T1572
Test name
Test status
Simulation time	584032963 ps
CPU time	2.28 seconds
Started	Jan 07 01:22:32 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	216724 kb
Host	smart-5059c4bb-9f6f-43e8-8f23-d0fc29acdc9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493211421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_bit_transfer.493211421
Directory	/workspace/29.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/29.spi_device_byte_transfer.2818802651
Short name	T1264
Test name
Test status
Simulation time	65173189 ps
CPU time	2.24 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:55 PM PST 24
Peak memory	216880 kb
Host	smart-35499aa3-c757-4ee2-87ee-08a3796ffcf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818802651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_byte_transfer.2818802651
Directory	/workspace/29.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/29.spi_device_cfg_cmd.3727724424
Short name	T1691
Test name
Test status
Simulation time	289815488 ps
CPU time	2.52 seconds
Started	Jan 07 01:22:45 PM PST 24
Finished	Jan 07 01:22:50 PM PST 24
Peak memory	239452 kb
Host	smart-2f97a0fc-dab4-46c1-91e2-54ef05e188b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727724424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3727724424
Directory	/workspace/29.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/29.spi_device_csb_read.825178195
Short name	T711
Test name
Test status
Simulation time	19219060 ps
CPU time	0.82 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	207560 kb
Host	smart-512ac6eb-da08-4ab2-95ee-4b3f46422a06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825178195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.825178195
Directory	/workspace/29.spi_device_csb_read/latest

Test location	/workspace/coverage/default/29.spi_device_dummy_item_extra_dly.1580573679
Short name	T1608
Test name
Test status
Simulation time	247352614735 ps
CPU time	154.52 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	266000 kb
Host	smart-92312ca1-ae3b-43ee-bb24-b2c72df02dad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580573679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_dummy_item_extra_dly.1580573679
Directory	/workspace/29.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/29.spi_device_extreme_fifo_size.3007518263
Short name	T1265
Test name
Test status
Simulation time	61992691030 ps
CPU time	883.35 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:37:33 PM PST 24
Peak memory	220172 kb
Host	smart-028de41d-3e38-4065-af0f-3c035abe077b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007518263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_extreme_fifo_size.3007518263
Directory	/workspace/29.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/29.spi_device_fifo_full.276553263
Short name	T1724
Test name
Test status
Simulation time	75556277659 ps
CPU time	792.64 seconds
Started	Jan 07 01:22:46 PM PST 24
Finished	Jan 07 01:36:01 PM PST 24
Peak memory	270832 kb
Host	smart-73c3fdeb-b996-4f3c-8627-d11e9dbfb4f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276553263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_full.276553263
Directory	/workspace/29.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/29.spi_device_fifo_underflow_overflow.2312603919
Short name	T799
Test name
Test status
Simulation time	21317572471 ps
CPU time	149.73 seconds
Started	Jan 07 01:22:45 PM PST 24
Finished	Jan 07 01:25:17 PM PST 24
Peak memory	314264 kb
Host	smart-5256bd19-340f-435a-983d-16154e7eb3b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312603919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_fifo_underflow_overf low.2312603919
Directory	/workspace/29.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/29.spi_device_flash_all.999860929
Short name	T20
Test name
Test status
Simulation time	72815910997 ps
CPU time	101.89 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:24:31 PM PST 24
Peak memory	251808 kb
Host	smart-81fa5423-00f2-4ed3-9d4b-64cefbcd5f0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999860929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.999860929
Directory	/workspace/29.spi_device_flash_all/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm.651615000
Short name	T209
Test name
Test status
Simulation time	31757604285 ps
CPU time	199.18 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:26:06 PM PST 24
Peak memory	282352 kb
Host	smart-69c331b8-9a85-4a5a-bc39-a454c4dcb7a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651615000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.651615000
Directory	/workspace/29.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2422043055
Short name	T103
Test name
Test status
Simulation time	27192508727 ps
CPU time	217.69 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:26:30 PM PST 24
Peak memory	254908 kb
Host	smart-326af6a0-b405-40f3-8a1f-212b68ef32d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422043055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl e.2422043055
Directory	/workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/29.spi_device_flash_mode.24018427
Short name	T1697
Test name
Test status
Simulation time	26804566598 ps
CPU time	40.17 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:23:29 PM PST 24
Peak memory	249492 kb
Host	smart-512823dc-a435-43a3-855f-33ad8ba13a46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24018427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.24018427
Directory	/workspace/29.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/29.spi_device_intercept.446220471
Short name	T217
Test name
Test status
Simulation time	7859729207 ps
CPU time	6.93 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	220932 kb
Host	smart-0111fb05-2462-43ee-ab56-2ddef555faf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446220471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.446220471
Directory	/workspace/29.spi_device_intercept/latest

Test location	/workspace/coverage/default/29.spi_device_mailbox.2015767899
Short name	T1736
Test name
Test status
Simulation time	3650447163 ps
CPU time	12.83 seconds
Started	Jan 07 01:22:36 PM PST 24
Finished	Jan 07 01:22:54 PM PST 24
Peak memory	238736 kb
Host	smart-3700e5af-64fe-417f-b728-ef202d72b43b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015767899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2015767899
Directory	/workspace/29.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2656958764
Short name	T1493
Test name
Test status
Simulation time	107484344 ps
CPU time	2.57 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	218220 kb
Host	smart-e242671c-4038-47bc-bada-4c5f1106ca36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656958764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa p.2656958764
Directory	/workspace/29.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/29.spi_device_pass_cmd_filtering.1957248560
Short name	T93
Test name
Test status
Simulation time	665430953 ps
CPU time	7.12 seconds
Started	Jan 07 01:22:31 PM PST 24
Finished	Jan 07 01:22:44 PM PST 24
Peak memory	246744 kb
Host	smart-0c023e1e-ad1b-4d32-aad0-00a6ddf53c15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957248560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1957248560
Directory	/workspace/29.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/29.spi_device_perf.2538869581
Short name	T1297
Test name
Test status
Simulation time	20848910840 ps
CPU time	491.07 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:30:52 PM PST 24
Peak memory	257304 kb
Host	smart-9ce9a3e6-ca5e-4271-b136-2dc47b5a9039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538869581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_perf.2538869581
Directory	/workspace/29.spi_device_perf/latest

Test location	/workspace/coverage/default/29.spi_device_read_buffer_direct.2194061612
Short name	T169
Test name
Test status
Simulation time	388929006 ps
CPU time	3.69 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	218552 kb
Host	smart-cab8cf01-e9dc-42c3-9712-858a07a87ff8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2194061612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir ect.2194061612
Directory	/workspace/29.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/29.spi_device_rx_async_fifo_reset.3859467317
Short name	T1674
Test name
Test status
Simulation time	50104428 ps
CPU time	0.92 seconds
Started	Jan 07 01:22:31 PM PST 24
Finished	Jan 07 01:22:38 PM PST 24
Peak memory	208520 kb
Host	smart-f5aaada6-a48c-48ff-930f-4c360d1740c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859467317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_async_fifo_reset.3859467317
Directory	/workspace/29.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/29.spi_device_rx_timeout.1369908576
Short name	T932
Test name
Test status
Simulation time	497208074 ps
CPU time	5.34 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	216820 kb
Host	smart-687efaa2-deac-400f-b3a7-290eafe50a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369908576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_rx_timeout.1369908576
Directory	/workspace/29.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/29.spi_device_smoke.2668993859
Short name	T1391
Test name
Test status
Simulation time	31509653 ps
CPU time	1.11 seconds
Started	Jan 07 01:22:33 PM PST 24
Finished	Jan 07 01:22:39 PM PST 24
Peak memory	208408 kb
Host	smart-72767c5d-bfbc-49b0-a02f-9b724cf283eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668993859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_smoke.2668993859
Directory	/workspace/29.spi_device_smoke/latest

Test location	/workspace/coverage/default/29.spi_device_stress_all.3929695975
Short name	T1102
Test name
Test status
Simulation time	186427676322 ps
CPU time	520.05 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:31:26 PM PST 24
Peak memory	334424 kb
Host	smart-c81ea25a-5ee2-47c6-a9b7-10809117a37d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929695975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre ss_all.3929695975
Directory	/workspace/29.spi_device_stress_all/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_all.1404051274
Short name	T1679
Test name
Test status
Simulation time	8287997454 ps
CPU time	32.37 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:23:12 PM PST 24
Peak memory	217108 kb
Host	smart-98b0f4d2-0489-43a1-9889-d9b00c37d98f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404051274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1404051274
Directory	/workspace/29.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.175622955
Short name	T1370
Test name
Test status
Simulation time	1066413636 ps
CPU time	2.38 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:42 PM PST 24
Peak memory	216580 kb
Host	smart-7ff4ce8a-9526-4e9f-942b-f89a0e0e97f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175622955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.175622955
Directory	/workspace/29.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_rw.4090877489
Short name	T897
Test name
Test status
Simulation time	585027270 ps
CPU time	2.66 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:43 PM PST 24
Peak memory	216772 kb
Host	smart-cefda8fb-d24f-44c1-bd87-99970f422233
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090877489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4090877489
Directory	/workspace/29.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_sts_read.2468842404
Short name	T519
Test name
Test status
Simulation time	214552996 ps
CPU time	0.99 seconds
Started	Jan 07 01:22:34 PM PST 24
Finished	Jan 07 01:22:40 PM PST 24
Peak memory	207996 kb
Host	smart-681a15a6-f740-4d61-bdec-9cbf9d4b7ec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468842404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2468842404
Directory	/workspace/29.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/29.spi_device_tx_async_fifo_reset.2916612028
Short name	T1108
Test name
Test status
Simulation time	23477812 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:35 PM PST 24
Finished	Jan 07 01:22:41 PM PST 24
Peak memory	208492 kb
Host	smart-e0643bb6-4c36-4dbf-a437-7ac41a186b47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916612028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tx_async_fifo_reset.2916612028
Directory	/workspace/29.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/29.spi_device_txrx.1513032033
Short name	T544
Test name
Test status
Simulation time	22928008227 ps
CPU time	207.88 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:26:20 PM PST 24
Peak memory	270168 kb
Host	smart-7e469663-320e-4fd6-8d18-b34210367cd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513032033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_txrx.1513032033
Directory	/workspace/29.spi_device_txrx/latest

Test location	/workspace/coverage/default/29.spi_device_upload.2016204088
Short name	T1244
Test name
Test status
Simulation time	2049518856 ps
CPU time	9.92 seconds
Started	Jan 07 01:22:45 PM PST 24
Finished	Jan 07 01:22:57 PM PST 24
Peak memory	218552 kb
Host	smart-b1642538-3cb0-4f55-a7e6-70ea0a69307c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016204088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2016204088
Directory	/workspace/29.spi_device_upload/latest

Test location	/workspace/coverage/default/3.spi_device_alert_test.3306679949
Short name	T631
Test name
Test status
Simulation time	10981674 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206540 kb
Host	smart-167161a5-bcb7-4509-9f35-6445737e65de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306679949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3 306679949
Directory	/workspace/3.spi_device_alert_test/latest

Test location	/workspace/coverage/default/3.spi_device_bit_transfer.1836996094
Short name	T1571
Test name
Test status
Simulation time	177360862 ps
CPU time	2.43 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:16 PM PST 24
Peak memory	216688 kb
Host	smart-5b3683d9-a80b-43cc-a188-7c2fcaa437bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836996094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_bit_transfer.1836996094
Directory	/workspace/3.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/3.spi_device_byte_transfer.2708868663
Short name	T1347
Test name
Test status
Simulation time	574615971 ps
CPU time	2.91 seconds
Started	Jan 07 01:19:09 PM PST 24
Finished	Jan 07 01:19:14 PM PST 24
Peak memory	216800 kb
Host	smart-112ace31-48de-47e2-9d1a-6b2830bd785b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708868663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_byte_transfer.2708868663
Directory	/workspace/3.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/3.spi_device_cfg_cmd.3102047869
Short name	T609
Test name
Test status
Simulation time	1701348268 ps
CPU time	4.52 seconds
Started	Jan 07 01:19:13 PM PST 24
Finished	Jan 07 01:19:21 PM PST 24
Peak memory	241416 kb
Host	smart-6c462354-c1b7-40e4-9d01-d50d5722ad61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102047869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3102047869
Directory	/workspace/3.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/3.spi_device_csb_read.1855539424
Short name	T512
Test name
Test status
Simulation time	66874716 ps
CPU time	0.75 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206544 kb
Host	smart-0ee4e097-5fac-460a-a939-401af407c121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855539424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1855539424
Directory	/workspace/3.spi_device_csb_read/latest

Test location	/workspace/coverage/default/3.spi_device_dummy_item_extra_dly.977180664
Short name	T1464
Test name
Test status
Simulation time	73780701677 ps
CPU time	616.53 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:29:32 PM PST 24
Peak memory	315020 kb
Host	smart-f52a11d3-724b-4446-8395-fe67206f7a65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977180664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_dummy_item_extra_dly.977180664
Directory	/workspace/3.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/3.spi_device_extreme_fifo_size.1529638757
Short name	T1140
Test name
Test status
Simulation time	59048123388 ps
CPU time	119.9 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:21:28 PM PST 24
Peak memory	219108 kb
Host	smart-ccf0ae6b-00ec-4823-b3e0-3549683d32be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529638757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_extreme_fifo_size.1529638757
Directory	/workspace/3.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/3.spi_device_fifo_full.1348471078
Short name	T506
Test name
Test status
Simulation time	52318424250 ps
CPU time	789.73 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:32:22 PM PST 24
Peak memory	298168 kb
Host	smart-a4499cd6-3d1e-4bea-8144-9957ca82a60a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348471078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_fifo_full.1348471078
Directory	/workspace/3.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/3.spi_device_flash_all.3555951136
Short name	T190
Test name
Test status
Simulation time	102655154765 ps
CPU time	160.65 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:22:05 PM PST 24
Peak memory	269768 kb
Host	smart-36278a78-e995-480d-b992-2ef4a9267929
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555951136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3555951136
Directory	/workspace/3.spi_device_flash_all/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm.1828076991
Short name	T1453
Test name
Test status
Simulation time	2929380824 ps
CPU time	59.64 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	251896 kb
Host	smart-0ea2bf30-9543-41e6-8180-441ae13f36cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828076991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1828076991
Directory	/workspace/3.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3104741354
Short name	T1753
Test name
Test status
Simulation time	6784607015 ps
CPU time	82.8 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:21:05 PM PST 24
Peak memory	266496 kb
Host	smart-1fb09b0f-56af-4b60-a5ab-75dfa13633a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104741354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle .3104741354
Directory	/workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/3.spi_device_flash_mode.819684160
Short name	T632
Test name
Test status
Simulation time	48850544402 ps
CPU time	60.57 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:20:13 PM PST 24
Peak memory	248892 kb
Host	smart-a3e077f5-ff74-4da1-a2cc-4655808410a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819684160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.819684160
Directory	/workspace/3.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/3.spi_device_intercept.2766474000
Short name	T818
Test name
Test status
Simulation time	5297534382 ps
CPU time	7.43 seconds
Started	Jan 07 01:19:23 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	241376 kb
Host	smart-ba1130e0-2815-452a-a138-956b89184b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766474000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2766474000
Directory	/workspace/3.spi_device_intercept/latest

Test location	/workspace/coverage/default/3.spi_device_intr.2247016706
Short name	T1163
Test name
Test status
Simulation time	16529250801 ps
CPU time	33.52 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:48 PM PST 24
Peak memory	225132 kb
Host	smart-eaabd78e-37bf-4bc6-af04-89baf00b3dd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247016706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intr.2247016706
Directory	/workspace/3.spi_device_intr/latest

Test location	/workspace/coverage/default/3.spi_device_mailbox.3501614788
Short name	T1325
Test name
Test status
Simulation time	48451354282 ps
CPU time	40.35 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:19:52 PM PST 24
Peak memory	255628 kb
Host	smart-44d8a314-ee16-4a41-a6e1-512ae43f6b6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501614788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3501614788
Directory	/workspace/3.spi_device_mailbox/latest

Test location	/workspace/coverage/default/3.spi_device_mem_parity.3541062413
Short name	T462
Test name
Test status
Simulation time	47962681 ps
CPU time	1.04 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	218832 kb
Host	smart-8ac95cf3-27b5-409d-8901-543483f482e4
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541062413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.spi_device_mem_parity.3541062413
Directory	/workspace/3.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3550121705
Short name	T985
Test name
Test status
Simulation time	5149172498 ps
CPU time	15.27 seconds
Started	Jan 07 01:19:32 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	221088 kb
Host	smart-5da5ce92-d42d-42f3-a405-4a13fe036eca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550121705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap .3550121705
Directory	/workspace/3.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/3.spi_device_pass_cmd_filtering.1100759663
Short name	T768
Test name
Test status
Simulation time	368301061 ps
CPU time	3.6 seconds
Started	Jan 07 01:19:13 PM PST 24
Finished	Jan 07 01:19:20 PM PST 24
Peak memory	218732 kb
Host	smart-ba5ba145-90c7-4fab-aec7-d4ebafca5f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100759663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1100759663
Directory	/workspace/3.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/3.spi_device_perf.336591989
Short name	T588
Test name
Test status
Simulation time	15736479636 ps
CPU time	357.85 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	249120 kb
Host	smart-7b940e02-94d2-44f3-83c2-d160117f357e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336591989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_perf.336591989
Directory	/workspace/3.spi_device_perf/latest

Test location	/workspace/coverage/default/3.spi_device_ram_cfg.148535292
Short name	T514
Test name
Test status
Simulation time	40005060 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:14 PM PST 24
Peak memory	216744 kb
Host	smart-053f787a-fdb6-413b-93b5-9b21c4b88da3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148535292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.148535292
Directory	/workspace/3.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/3.spi_device_read_buffer_direct.2076971436
Short name	T1480
Test name
Test status
Simulation time	1081716850 ps
CPU time	6.44 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:19:19 PM PST 24
Peak memory	218796 kb
Host	smart-22442101-decf-4798-b44d-b059537059d6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2076971436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.2076971436
Directory	/workspace/3.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/3.spi_device_rx_async_fifo_reset.1561190139
Short name	T994
Test name
Test status
Simulation time	20651332 ps
CPU time	0.86 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:28 PM PST 24
Peak memory	208444 kb
Host	smart-469a0326-edda-4e3b-aed4-98f875ad2474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561190139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_async_fifo_reset.1561190139
Directory	/workspace/3.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/3.spi_device_rx_timeout.1165288225
Short name	T1535
Test name
Test status
Simulation time	513733487 ps
CPU time	4.97 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:19:17 PM PST 24
Peak memory	216816 kb
Host	smart-f7200cd3-7454-4d63-aa89-203b14f224fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165288225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_rx_timeout.1165288225
Directory	/workspace/3.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/3.spi_device_sec_cm.4022338911
Short name	T88
Test name
Test status
Simulation time	76777786 ps
CPU time	1.09 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	238148 kb
Host	smart-158a5108-e667-458a-8e0a-6f2b68fd9828
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022338911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4022338911
Directory	/workspace/3.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/3.spi_device_smoke.1927232678
Short name	T1204
Test name
Test status
Simulation time	444853778 ps
CPU time	1.08 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:52 PM PST 24
Peak memory	208324 kb
Host	smart-469fff18-ba07-4eb6-aab8-acbf477c94f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927232678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_smoke.1927232678
Directory	/workspace/3.spi_device_smoke/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_all.2068115181
Short name	T1550
Test name
Test status
Simulation time	3502162324 ps
CPU time	31.44 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	216896 kb
Host	smart-056e7541-f425-4dd6-9f4a-37301c49e622
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068115181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2068115181
Directory	/workspace/3.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2710912914
Short name	T984
Test name
Test status
Simulation time	9595082798 ps
CPU time	12.23 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:49 PM PST 24
Peak memory	217988 kb
Host	smart-00339b60-b7a0-45e2-8a16-805de3a650a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2710912914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2710912914
Directory	/workspace/3.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_rw.1683586161
Short name	T1030
Test name
Test status
Simulation time	561966047 ps
CPU time	1.66 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:30 PM PST 24
Peak memory	216644 kb
Host	smart-1f6c8a6c-2079-4788-9782-b5732f93cb16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683586161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1683586161
Directory	/workspace/3.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_sts_read.1837538332
Short name	T464
Test name
Test status
Simulation time	30431548 ps
CPU time	0.79 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:15 PM PST 24
Peak memory	206892 kb
Host	smart-de6eddeb-c35f-4013-bfc8-ff8679103a66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837538332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1837538332
Directory	/workspace/3.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/3.spi_device_tx_async_fifo_reset.210775411
Short name	T559
Test name
Test status
Simulation time	19121222 ps
CPU time	0.82 seconds
Started	Jan 07 01:19:13 PM PST 24
Finished	Jan 07 01:19:18 PM PST 24
Peak memory	208412 kb
Host	smart-cf46a205-dc1c-4886-a328-cde9a7b538e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210775411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tx_async_fifo_reset.210775411
Directory	/workspace/3.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/3.spi_device_txrx.1819772997
Short name	T1362
Test name
Test status
Simulation time	27970407960 ps
CPU time	306.55 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:24:22 PM PST 24
Peak memory	285744 kb
Host	smart-61cc1258-393a-470d-998c-9324cdba13f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819772997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_txrx.1819772997
Directory	/workspace/3.spi_device_txrx/latest

Test location	/workspace/coverage/default/3.spi_device_upload.4043869003
Short name	T274
Test name
Test status
Simulation time	776795634 ps
CPU time	5.11 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	240652 kb
Host	smart-817b4632-3791-4958-8b63-c5d8dabde0a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043869003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4043869003
Directory	/workspace/3.spi_device_upload/latest

Test location	/workspace/coverage/default/30.spi_device_abort.414237894
Short name	T1
Test name
Test status
Simulation time	92714192 ps
CPU time	0.76 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	206580 kb
Host	smart-4467753b-0ea1-4f4b-b16c-db72fbb93b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414237894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_abort.414237894
Directory	/workspace/30.spi_device_abort/latest

Test location	/workspace/coverage/default/30.spi_device_alert_test.713069916
Short name	T502
Test name
Test status
Simulation time	39919707 ps
CPU time	0.72 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:54 PM PST 24
Peak memory	206480 kb
Host	smart-10aeabc8-6c9b-47c3-b816-8a986188eb88
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713069916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.713069916
Directory	/workspace/30.spi_device_alert_test/latest

Test location	/workspace/coverage/default/30.spi_device_bit_transfer.727659209
Short name	T813
Test name
Test status
Simulation time	952607336 ps
CPU time	2.65 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:22:54 PM PST 24
Peak memory	216900 kb
Host	smart-542107dd-2b5e-493c-9c58-75a79f6f9884
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727659209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_bit_transfer.727659209
Directory	/workspace/30.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/30.spi_device_byte_transfer.984455868
Short name	T1543
Test name
Test status
Simulation time	185747881 ps
CPU time	2.46 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:57 PM PST 24
Peak memory	216716 kb
Host	smart-5ca1f124-12ff-4b67-b206-564901c34045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984455868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_byte_transfer.984455868
Directory	/workspace/30.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/30.spi_device_cfg_cmd.4204064227
Short name	T873
Test name
Test status
Simulation time	265458005 ps
CPU time	2.7 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:22:52 PM PST 24
Peak memory	218656 kb
Host	smart-7eda97ca-e96d-453f-81c0-a4ec0512d742
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204064227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4204064227
Directory	/workspace/30.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/30.spi_device_csb_read.2547985424
Short name	T754
Test name
Test status
Simulation time	61056398 ps
CPU time	0.78 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	207640 kb
Host	smart-ceb5b3eb-47f6-4172-b637-1c8d76948e64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547985424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2547985424
Directory	/workspace/30.spi_device_csb_read/latest

Test location	/workspace/coverage/default/30.spi_device_dummy_item_extra_dly.3331152060
Short name	T1241
Test name
Test status
Simulation time	77052726204 ps
CPU time	1409.61 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:46:24 PM PST 24
Peak memory	298852 kb
Host	smart-e3b25a75-6357-4700-9199-e1141218be02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331152060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_dummy_item_extra_dly.3331152060
Directory	/workspace/30.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/30.spi_device_extreme_fifo_size.2127553091
Short name	T1505
Test name
Test status
Simulation time	49956607122 ps
CPU time	639.55 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:33:35 PM PST 24
Peak memory	218040 kb
Host	smart-3697d9c5-4d14-4342-8ae0-21faebfabc1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127553091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_extreme_fifo_size.2127553091
Directory	/workspace/30.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/30.spi_device_fifo_full.3492647789
Short name	T1121
Test name
Test status
Simulation time	51371444430 ps
CPU time	1074.31 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:40:44 PM PST 24
Peak memory	302756 kb
Host	smart-205ced31-2044-4119-b46f-460466deb3ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492647789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_full.3492647789
Directory	/workspace/30.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/30.spi_device_fifo_underflow_overflow.3331151595
Short name	T906
Test name
Test status
Simulation time	76720627016 ps
CPU time	149.48 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	294444 kb
Host	smart-3b71e216-41cd-433a-a03d-3b806803c1f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331151595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_fifo_underflow_overf low.3331151595
Directory	/workspace/30.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/30.spi_device_flash_all.2082126836
Short name	T270
Test name
Test status
Simulation time	6331962126 ps
CPU time	30.71 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:23:25 PM PST 24
Peak memory	249732 kb
Host	smart-6d8e14cb-471a-4b93-8ed6-4d1bec6f1ced
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082126836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2082126836
Directory	/workspace/30.spi_device_flash_all/latest

Test location	/workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1015412642
Short name	T29
Test name
Test status
Simulation time	8567794463 ps
CPU time	118.41 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:24:50 PM PST 24
Peak memory	265580 kb
Host	smart-81c55d51-d9d9-442c-9a98-d74e20a12310
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015412642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl e.1015412642
Directory	/workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/30.spi_device_flash_mode.1059879637
Short name	T587
Test name
Test status
Simulation time	13597220785 ps
CPU time	22.66 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:30 PM PST 24
Peak memory	238916 kb
Host	smart-764c79a0-b87e-42f7-ac96-d51778bdd9fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059879637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1059879637
Directory	/workspace/30.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/30.spi_device_intercept.643771766
Short name	T451
Test name
Test status
Simulation time	2552450155 ps
CPU time	10.7 seconds
Started	Jan 07 01:22:46 PM PST 24
Finished	Jan 07 01:22:59 PM PST 24
Peak memory	221100 kb
Host	smart-6d5df2cb-5c2e-415c-84df-588492d61bb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643771766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.643771766
Directory	/workspace/30.spi_device_intercept/latest

Test location	/workspace/coverage/default/30.spi_device_intr.2061467697
Short name	T1734
Test name
Test status
Simulation time	4679186383 ps
CPU time	26.01 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	232736 kb
Host	smart-404186fb-cc19-4cda-9c11-810440657061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061467697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intr.2061467697
Directory	/workspace/30.spi_device_intr/latest

Test location	/workspace/coverage/default/30.spi_device_mailbox.3326462444
Short name	T1412
Test name
Test status
Simulation time	347704130 ps
CPU time	6.33 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:23:12 PM PST 24
Peak memory	218020 kb
Host	smart-e8644b82-fff6-4c04-a677-9a442563d8b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326462444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3326462444
Directory	/workspace/30.spi_device_mailbox/latest

Test location	/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1064985274
Short name	T1542
Test name
Test status
Simulation time	4734767201 ps
CPU time	9.49 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	220544 kb
Host	smart-a878cbc4-7d8b-4385-a214-29a5476be788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064985274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa p.1064985274
Directory	/workspace/30.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/30.spi_device_pass_cmd_filtering.949682084
Short name	T936
Test name
Test status
Simulation time	6949125796 ps
CPU time	8.93 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:23:04 PM PST 24
Peak memory	218460 kb
Host	smart-4106dba2-d3d0-4f90-b7f6-442567d4dd71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949682084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.949682084
Directory	/workspace/30.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/30.spi_device_perf.2950254859
Short name	T664
Test name
Test status
Simulation time	15130104670 ps
CPU time	504.31 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:31:20 PM PST 24
Peak memory	282340 kb
Host	smart-56ed9d28-d046-49fc-a0c5-abf165e3167c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950254859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_perf.2950254859
Directory	/workspace/30.spi_device_perf/latest

Test location	/workspace/coverage/default/30.spi_device_read_buffer_direct.1604296053
Short name	T493
Test name
Test status
Simulation time	1133132324 ps
CPU time	6.23 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:15 PM PST 24
Peak memory	218832 kb
Host	smart-1f123326-a5cb-4195-a2aa-84fd797f0d7c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1604296053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir ect.1604296053
Directory	/workspace/30.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/30.spi_device_rx_async_fifo_reset.491026584
Short name	T579
Test name
Test status
Simulation time	44767624 ps
CPU time	0.93 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:22:51 PM PST 24
Peak memory	208428 kb
Host	smart-446058dd-34da-426f-974d-23baa5923b36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491026584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_async_fifo_reset.491026584
Directory	/workspace/30.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/30.spi_device_rx_timeout.2278203739
Short name	T950
Test name
Test status
Simulation time	694523985 ps
CPU time	6.67 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:23:01 PM PST 24
Peak memory	216892 kb
Host	smart-223f8742-fdd8-4a8b-9f38-d05921d3497c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278203739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_rx_timeout.2278203739
Directory	/workspace/30.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/30.spi_device_smoke.2164984338
Short name	T453
Test name
Test status
Simulation time	29600948 ps
CPU time	1.12 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:22:47 PM PST 24
Peak memory	207564 kb
Host	smart-4f002ff0-7f59-4f62-bd82-1cf9b081df95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164984338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_smoke.2164984338
Directory	/workspace/30.spi_device_smoke/latest

Test location	/workspace/coverage/default/30.spi_device_stress_all.1529208200
Short name	T1097
Test name
Test status
Simulation time	427643370225 ps
CPU time	3131.27 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 02:15:03 PM PST 24
Peak memory	616696 kb
Host	smart-1f7f9bdd-ea50-423f-b38d-0b10a3961846
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529208200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre ss_all.1529208200
Directory	/workspace/30.spi_device_stress_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_all.900754039
Short name	T341
Test name
Test status
Simulation time	49820885496 ps
CPU time	185.61 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:25:57 PM PST 24
Peak memory	221796 kb
Host	smart-ce8d22f4-f065-49dc-925f-115da9757cbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900754039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.900754039
Directory	/workspace/30.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3266239164
Short name	T1152
Test name
Test status
Simulation time	4628801593 ps
CPU time	9.32 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:18 PM PST 24
Peak memory	216812 kb
Host	smart-cc8e3ff5-8832-444d-8411-cf0459f5d4af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266239164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3266239164
Directory	/workspace/30.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_rw.2978239012
Short name	T1255
Test name
Test status
Simulation time	446878803 ps
CPU time	6.26 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:23:11 PM PST 24
Peak memory	216856 kb
Host	smart-c838d42b-cb2b-4704-a0dc-a3e620c771f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978239012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2978239012
Directory	/workspace/30.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_sts_read.3970025447
Short name	T1257
Test name
Test status
Simulation time	159176387 ps
CPU time	1 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	206856 kb
Host	smart-b9931763-6174-4761-b893-780c91610131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970025447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3970025447
Directory	/workspace/30.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/30.spi_device_tx_async_fifo_reset.1566737529
Short name	T1420
Test name
Test status
Simulation time	29183218 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	208392 kb
Host	smart-b48f6043-363c-40e0-935f-430d55dcba35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566737529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tx_async_fifo_reset.1566737529
Directory	/workspace/30.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/30.spi_device_txrx.3428201845
Short name	T863
Test name
Test status
Simulation time	39380629075 ps
CPU time	911.26 seconds
Started	Jan 07 01:22:44 PM PST 24
Finished	Jan 07 01:37:58 PM PST 24
Peak memory	263476 kb
Host	smart-80a9fa3d-5457-4e7a-95de-577056123d21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428201845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_txrx.3428201845
Directory	/workspace/30.spi_device_txrx/latest

Test location	/workspace/coverage/default/30.spi_device_upload.625818903
Short name	T1518
Test name
Test status
Simulation time	8187329677 ps
CPU time	28.5 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	230800 kb
Host	smart-772cf767-63c5-4bfd-abd2-6f5ae2ae3f07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625818903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.625818903
Directory	/workspace/30.spi_device_upload/latest

Test location	/workspace/coverage/default/31.spi_device_abort.4225894039
Short name	T577
Test name
Test status
Simulation time	17250299 ps
CPU time	0.76 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:22:51 PM PST 24
Peak memory	206580 kb
Host	smart-2c44bc5a-54a2-43a3-a0b1-14fe1d3d3e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225894039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_abort.4225894039
Directory	/workspace/31.spi_device_abort/latest

Test location	/workspace/coverage/default/31.spi_device_alert_test.74729790
Short name	T539
Test name
Test status
Simulation time	44200501 ps
CPU time	0.7 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	206416 kb
Host	smart-86555bae-6853-48e7-8db4-a95191d85950
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74729790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.74729790
Directory	/workspace/31.spi_device_alert_test/latest

Test location	/workspace/coverage/default/31.spi_device_bit_transfer.1082610568
Short name	T992
Test name
Test status
Simulation time	295614861 ps
CPU time	3.35 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	216828 kb
Host	smart-93a397fe-2b41-4f6a-9a5d-1130fff839c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082610568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_bit_transfer.1082610568
Directory	/workspace/31.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/31.spi_device_byte_transfer.4103175295
Short name	T728
Test name
Test status
Simulation time	218220279 ps
CPU time	2.99 seconds
Started	Jan 07 01:23:04 PM PST 24
Finished	Jan 07 01:23:07 PM PST 24
Peak memory	216784 kb
Host	smart-c4dc265c-6a37-47e4-9b3d-8733e15c367b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4103175295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_byte_transfer.4103175295
Directory	/workspace/31.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/31.spi_device_cfg_cmd.3389969635
Short name	T595
Test name
Test status
Simulation time	139844913 ps
CPU time	2.99 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	218712 kb
Host	smart-466f684e-9e57-43b5-bd0d-315d56393792
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389969635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3389969635
Directory	/workspace/31.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/31.spi_device_csb_read.2263197263
Short name	T1388
Test name
Test status
Simulation time	61383625 ps
CPU time	0.84 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	207612 kb
Host	smart-ff0ab033-2ea0-4e3f-99a4-a62cbcf1f91a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263197263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2263197263
Directory	/workspace/31.spi_device_csb_read/latest

Test location	/workspace/coverage/default/31.spi_device_dummy_item_extra_dly.2761778881
Short name	T554
Test name
Test status
Simulation time	133507836087 ps
CPU time	518.36 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:31:29 PM PST 24
Peak memory	282472 kb
Host	smart-18b3e1b1-cdec-4bd6-a016-18b029651a06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761778881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_dummy_item_extra_dly.2761778881
Directory	/workspace/31.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/31.spi_device_extreme_fifo_size.2546801803
Short name	T885
Test name
Test status
Simulation time	238054519567 ps
CPU time	494.29 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:31:05 PM PST 24
Peak memory	224600 kb
Host	smart-1987f181-0767-4da1-9076-be5b59b27622
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546801803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_extreme_fifo_size.2546801803
Directory	/workspace/31.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/31.spi_device_fifo_full.855898966
Short name	T975
Test name
Test status
Simulation time	229712298058 ps
CPU time	1268.72 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:43:58 PM PST 24
Peak memory	272776 kb
Host	smart-a2d26ca6-a057-45a7-871c-0bf99955baf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855898966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_full.855898966
Directory	/workspace/31.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/31.spi_device_fifo_underflow_overflow.4173418952
Short name	T1552
Test name
Test status
Simulation time	145118165040 ps
CPU time	370.02 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:29:05 PM PST 24
Peak memory	522100 kb
Host	smart-4a70d5a0-3021-4797-961a-0d5a3f243cb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173418952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_fifo_underflow_overf low.4173418952
Directory	/workspace/31.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/31.spi_device_flash_all.500696404
Short name	T1072
Test name
Test status
Simulation time	12360981144 ps
CPU time	68.95 seconds
Started	Jan 07 01:23:04 PM PST 24
Finished	Jan 07 01:24:14 PM PST 24
Peak memory	250488 kb
Host	smart-62e75f58-4bc4-40ee-b390-e244a94d3dbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500696404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.500696404
Directory	/workspace/31.spi_device_flash_all/latest

Test location	/workspace/coverage/default/31.spi_device_flash_and_tpm.258028537
Short name	T1432
Test name
Test status
Simulation time	111058783564 ps
CPU time	217.21 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:26:44 PM PST 24
Peak memory	254544 kb
Host	smart-6b4ac0a3-b712-4b17-9849-52ab2c937ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258028537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.258028537
Directory	/workspace/31.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/31.spi_device_flash_mode.3722466234
Short name	T1349
Test name
Test status
Simulation time	28948959182 ps
CPU time	38.53 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:46 PM PST 24
Peak memory	236632 kb
Host	smart-83c2e961-5241-4b5c-97b2-8bf81d009ece
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722466234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3722466234
Directory	/workspace/31.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/31.spi_device_intercept.2307728119
Short name	T249
Test name
Test status
Simulation time	2339646046 ps
CPU time	6.36 seconds
Started	Jan 07 01:22:48 PM PST 24
Finished	Jan 07 01:22:57 PM PST 24
Peak memory	219732 kb
Host	smart-a2072cbf-a65b-4da6-b9a2-75430e22ce1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307728119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2307728119
Directory	/workspace/31.spi_device_intercept/latest

Test location	/workspace/coverage/default/31.spi_device_intr.524898571
Short name	T509
Test name
Test status
Simulation time	53252470683 ps
CPU time	46.97 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:23:53 PM PST 24
Peak memory	224972 kb
Host	smart-7495351b-6503-404b-b0ef-cbb99c2015c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524898571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intr.524898571
Directory	/workspace/31.spi_device_intr/latest

Test location	/workspace/coverage/default/31.spi_device_mailbox.350340025
Short name	T982
Test name
Test status
Simulation time	25536047378 ps
CPU time	56.97 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:23:48 PM PST 24
Peak memory	219936 kb
Host	smart-87743a9c-53c0-4b61-8138-359bf73876ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350340025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.350340025
Directory	/workspace/31.spi_device_mailbox/latest

Test location	/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3422251301
Short name	T295
Test name
Test status
Simulation time	8209130366 ps
CPU time	39.73 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:48 PM PST 24
Peak memory	240844 kb
Host	smart-cc55498d-e854-4b18-9e45-93fab79c724d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422251301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa p.3422251301
Directory	/workspace/31.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/31.spi_device_pass_cmd_filtering.417942167
Short name	T673
Test name
Test status
Simulation time	19373847141 ps
CPU time	16.27 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	241504 kb
Host	smart-ae08ceb8-8665-4972-a447-52bd3bfa20be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417942167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.417942167
Directory	/workspace/31.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/31.spi_device_perf.2475983734
Short name	T472
Test name
Test status
Simulation time	12213088190 ps
CPU time	747.11 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:35:23 PM PST 24
Peak memory	249828 kb
Host	smart-4befba9f-ecb5-4944-9dc3-4e80a18be5bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475983734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_perf.2475983734
Directory	/workspace/31.spi_device_perf/latest

Test location	/workspace/coverage/default/31.spi_device_read_buffer_direct.3877137580
Short name	T1524
Test name
Test status
Simulation time	354488630 ps
CPU time	4.77 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:12 PM PST 24
Peak memory	234400 kb
Host	smart-dd054440-685b-4e22-ba56-d0ae291d8c19
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3877137580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir ect.3877137580
Directory	/workspace/31.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/31.spi_device_rx_async_fifo_reset.3013735774
Short name	T1690
Test name
Test status
Simulation time	38373628 ps
CPU time	0.92 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:22:52 PM PST 24
Peak memory	208404 kb
Host	smart-63364461-a843-4637-b5a6-0e6b0d0d4f88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013735774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_async_fifo_reset.3013735774
Directory	/workspace/31.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/31.spi_device_rx_timeout.2351171603
Short name	T860
Test name
Test status
Simulation time	619196348 ps
CPU time	5.75 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	216704 kb
Host	smart-c2815ba4-da69-46f8-b02e-7405ce67c90f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351171603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_rx_timeout.2351171603
Directory	/workspace/31.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/31.spi_device_smoke.643231901
Short name	T1496
Test name
Test status
Simulation time	25692664 ps
CPU time	1.01 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	207880 kb
Host	smart-2e8cdb0d-04db-491d-b61a-e750e12b4e3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643231901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_smoke.643231901
Directory	/workspace/31.spi_device_smoke/latest

Test location	/workspace/coverage/default/31.spi_device_stress_all.3088165645
Short name	T1169
Test name
Test status
Simulation time	148497623059 ps
CPU time	1974.74 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:56:02 PM PST 24
Peak memory	267104 kb
Host	smart-5d2f5459-1fab-4ad3-821d-ae86dec50b39
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088165645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre ss_all.3088165645
Directory	/workspace/31.spi_device_stress_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_all.1859569788
Short name	T1156
Test name
Test status
Simulation time	8051599636 ps
CPU time	36.49 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:23:26 PM PST 24
Peak memory	221808 kb
Host	smart-d96eb84c-6b7b-43fb-ae3c-29db55b8e014
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859569788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1859569788
Directory	/workspace/31.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2830601848
Short name	T1400
Test name
Test status
Simulation time	4252864833 ps
CPU time	3.87 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:23:11 PM PST 24
Peak memory	216884 kb
Host	smart-c23bdd81-f52e-445f-8526-9123c8bd6893
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830601848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2830601848
Directory	/workspace/31.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_rw.871633041
Short name	T1217
Test name
Test status
Simulation time	97822149 ps
CPU time	1.44 seconds
Started	Jan 07 01:22:47 PM PST 24
Finished	Jan 07 01:22:51 PM PST 24
Peak memory	216808 kb
Host	smart-bd3dca2f-e64c-485d-8996-2aa2dc6646b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871633041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.871633041
Directory	/workspace/31.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_sts_read.1382642628
Short name	T1356
Test name
Test status
Simulation time	326980100 ps
CPU time	0.97 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:12 PM PST 24
Peak memory	207008 kb
Host	smart-bfaf56de-521b-46f3-8803-d8f7e5aa825c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382642628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1382642628
Directory	/workspace/31.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/31.spi_device_tx_async_fifo_reset.622501197
Short name	T14
Test name
Test status
Simulation time	15379068 ps
CPU time	0.77 seconds
Started	Jan 07 01:22:50 PM PST 24
Finished	Jan 07 01:22:53 PM PST 24
Peak memory	208440 kb
Host	smart-d5c13bca-ca6c-4e8f-ba93-4dd3a7c6575b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622501197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tx_async_fifo_reset.622501197
Directory	/workspace/31.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/31.spi_device_txrx.778204022
Short name	T774
Test name
Test status
Simulation time	21350650711 ps
CPU time	195.15 seconds
Started	Jan 07 01:23:08 PM PST 24
Finished	Jan 07 01:26:24 PM PST 24
Peak memory	296384 kb
Host	smart-dbaf6ef4-c386-42bb-80d8-a29071f9a390
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778204022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_txrx.778204022
Directory	/workspace/31.spi_device_txrx/latest

Test location	/workspace/coverage/default/31.spi_device_upload.2036932766
Short name	T1170
Test name
Test status
Simulation time	24532647391 ps
CPU time	39.43 seconds
Started	Jan 07 01:22:49 PM PST 24
Finished	Jan 07 01:23:30 PM PST 24
Peak memory	241472 kb
Host	smart-fc1052f6-b288-4232-806d-9e29b65e924b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036932766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2036932766
Directory	/workspace/31.spi_device_upload/latest

Test location	/workspace/coverage/default/32.spi_device_abort.637313342
Short name	T1731
Test name
Test status
Simulation time	23175330 ps
CPU time	0.77 seconds
Started	Jan 07 01:23:08 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	206664 kb
Host	smart-ddcd0fd9-9c8e-4b90-8df2-3b4965557c4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637313342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_abort.637313342
Directory	/workspace/32.spi_device_abort/latest

Test location	/workspace/coverage/default/32.spi_device_alert_test.1399751002
Short name	T1651
Test name
Test status
Simulation time	23176486 ps
CPU time	0.68 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:14 PM PST 24
Peak memory	206484 kb
Host	smart-519a5586-daca-4b63-8169-046f6fd433f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399751002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 1399751002
Directory	/workspace/32.spi_device_alert_test/latest

Test location	/workspace/coverage/default/32.spi_device_bit_transfer.3648182389
Short name	T963
Test name
Test status
Simulation time	250441370 ps
CPU time	2.98 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	216820 kb
Host	smart-85e9cc00-7cb9-436d-9980-4865e41227c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648182389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_bit_transfer.3648182389
Directory	/workspace/32.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/32.spi_device_byte_transfer.1231469319
Short name	T1153
Test name
Test status
Simulation time	69591237 ps
CPU time	2.55 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:22:58 PM PST 24
Peak memory	216728 kb
Host	smart-8427534e-898f-4e3a-a80c-2239d3387576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231469319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_byte_transfer.1231469319
Directory	/workspace/32.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/32.spi_device_cfg_cmd.384110093
Short name	T1541
Test name
Test status
Simulation time	2538075232 ps
CPU time	3.2 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:11 PM PST 24
Peak memory	218788 kb
Host	smart-4734a83a-4e5c-4e75-b110-f0e23cb5e577
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384110093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.384110093
Directory	/workspace/32.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/32.spi_device_csb_read.2554808904
Short name	T1118
Test name
Test status
Simulation time	117906728 ps
CPU time	0.82 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:08 PM PST 24
Peak memory	207560 kb
Host	smart-156096be-b4c5-47c4-9fc6-404545cda34e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554808904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2554808904
Directory	/workspace/32.spi_device_csb_read/latest

Test location	/workspace/coverage/default/32.spi_device_dummy_item_extra_dly.438539272
Short name	T1310
Test name
Test status
Simulation time	53964054520 ps
CPU time	432.32 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:30:19 PM PST 24
Peak memory	272712 kb
Host	smart-b343aac8-0d2b-4442-b985-eb3fea597177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438539272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_dummy_item_extra_dly.438539272
Directory	/workspace/32.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/32.spi_device_extreme_fifo_size.178898918
Short name	T1660
Test name
Test status
Simulation time	91446348867 ps
CPU time	960.54 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:39:08 PM PST 24
Peak memory	223252 kb
Host	smart-abe0bbf5-9c55-4c36-8fa5-06fbe3b3803d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178898918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_extreme_fifo_size.178898918
Directory	/workspace/32.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/32.spi_device_fifo_full.2956780194
Short name	T969
Test name
Test status
Simulation time	23685924893 ps
CPU time	338.74 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:28:37 PM PST 24
Peak memory	256812 kb
Host	smart-ee7c49ef-1a80-4e2b-bbbd-b96b9ee20df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956780194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_full.2956780194
Directory	/workspace/32.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/32.spi_device_fifo_underflow_overflow.2456539724
Short name	T111
Test name
Test status
Simulation time	1087786428838 ps
CPU time	370.52 seconds
Started	Jan 07 01:23:05 PM PST 24
Finished	Jan 07 01:29:17 PM PST 24
Peak memory	397400 kb
Host	smart-f5bd0ad9-5a31-4dd4-a2aa-32fa5f57b247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456539724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_fifo_underflow_overf low.2456539724
Directory	/workspace/32.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/32.spi_device_flash_all.663097374
Short name	T645
Test name
Test status
Simulation time	13427239807 ps
CPU time	32.78 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:41 PM PST 24
Peak memory	238020 kb
Host	smart-f84d3f1e-a61b-468b-88a2-81b135277c24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663097374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.663097374
Directory	/workspace/32.spi_device_flash_all/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm.2932106139
Short name	T236
Test name
Test status
Simulation time	89947818152 ps
CPU time	124.03 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	272832 kb
Host	smart-b9cadf3c-5f9c-4997-bdf8-307094404727
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932106139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2932106139
Directory	/workspace/32.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.252068631
Short name	T1741
Test name
Test status
Simulation time	195372819780 ps
CPU time	386.31 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:29:19 PM PST 24
Peak memory	265380 kb
Host	smart-d8482400-a74c-4f80-b060-bf8ff073d92d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252068631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle .252068631
Directory	/workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/32.spi_device_flash_mode.2671493406
Short name	T167
Test name
Test status
Simulation time	552808761 ps
CPU time	17.24 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:25 PM PST 24
Peak memory	234532 kb
Host	smart-e56de7c1-58b9-4a1e-ba3f-4d9d2eb977f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671493406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2671493406
Directory	/workspace/32.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/32.spi_device_intercept.4212820419
Short name	T1143
Test name
Test status
Simulation time	6144925711 ps
CPU time	9.95 seconds
Started	Jan 07 01:22:51 PM PST 24
Finished	Jan 07 01:23:04 PM PST 24
Peak memory	225064 kb
Host	smart-7fc0b828-423c-4657-9f0a-3b20b060d8d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212820419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4212820419
Directory	/workspace/32.spi_device_intercept/latest

Test location	/workspace/coverage/default/32.spi_device_intr.2265767028
Short name	T1389
Test name
Test status
Simulation time	53487572789 ps
CPU time	68.8 seconds
Started	Jan 07 01:22:54 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	238648 kb
Host	smart-190fe649-decd-4a98-a522-20d9fbf1531d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265767028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intr.2265767028
Directory	/workspace/32.spi_device_intr/latest

Test location	/workspace/coverage/default/32.spi_device_mailbox.4175259760
Short name	T933
Test name
Test status
Simulation time	8725685737 ps
CPU time	28 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:23:24 PM PST 24
Peak memory	247216 kb
Host	smart-9fcc1762-5a85-4175-836b-72b72af6f4e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175259760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4175259760
Directory	/workspace/32.spi_device_mailbox/latest

Test location	/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1112305811
Short name	T705
Test name
Test status
Simulation time	6290957741 ps
CPU time	11.87 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	247612 kb
Host	smart-e13b2728-578a-4b8f-afa4-a68752ffbfbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112305811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.1112305811
Directory	/workspace/32.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2320381880
Short name	T937
Test name
Test status
Simulation time	11786518093 ps
CPU time	33.06 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:23:29 PM PST 24
Peak memory	230784 kb
Host	smart-78c35f18-3485-45f0-b994-99735ea9cebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320381880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2320381880
Directory	/workspace/32.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/32.spi_device_perf.1427646763
Short name	T45
Test name
Test status
Simulation time	166122248344 ps
CPU time	1997.15 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:56:26 PM PST 24
Peak memory	252820 kb
Host	smart-754e0563-bffa-4552-9290-cc04c2e34115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427646763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_perf.1427646763
Directory	/workspace/32.spi_device_perf/latest

Test location	/workspace/coverage/default/32.spi_device_read_buffer_direct.559522271
Short name	T170
Test name
Test status
Simulation time	930444313 ps
CPU time	5.85 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:13 PM PST 24
Peak memory	220100 kb
Host	smart-d5525c45-15d6-41c2-abe9-6d9fa6af49e1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=559522271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire ct.559522271
Directory	/workspace/32.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/32.spi_device_rx_async_fifo_reset.1568340328
Short name	T894
Test name
Test status
Simulation time	102224065 ps
CPU time	0.91 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:22:59 PM PST 24
Peak memory	208432 kb
Host	smart-612b1a0e-43ee-40b8-b649-8d6606ecc0b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568340328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_async_fifo_reset.1568340328
Directory	/workspace/32.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/32.spi_device_rx_timeout.329778431
Short name	T628
Test name
Test status
Simulation time	746906091 ps
CPU time	5.91 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	216812 kb
Host	smart-dfe8744a-9883-48f5-a38f-7da1a032466b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329778431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_rx_timeout.329778431
Directory	/workspace/32.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/32.spi_device_smoke.2909627583
Short name	T1739
Test name
Test status
Simulation time	34166712 ps
CPU time	1.09 seconds
Started	Jan 07 01:22:52 PM PST 24
Finished	Jan 07 01:22:56 PM PST 24
Peak memory	216448 kb
Host	smart-00bd9459-7069-47e8-b11a-631da14fcc91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909627583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_smoke.2909627583
Directory	/workspace/32.spi_device_smoke/latest

Test location	/workspace/coverage/default/32.spi_device_stress_all.3933899514
Short name	T1653
Test name
Test status
Simulation time	1246243032230 ps
CPU time	1515.73 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:48:13 PM PST 24
Peak memory	493756 kb
Host	smart-2bf5be7d-8156-4573-927a-f699221a10ba
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933899514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre ss_all.3933899514
Directory	/workspace/32.spi_device_stress_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_all.2078207389
Short name	T1104
Test name
Test status
Simulation time	3483366683 ps
CPU time	28.46 seconds
Started	Jan 07 01:22:53 PM PST 24
Finished	Jan 07 01:23:25 PM PST 24
Peak memory	216848 kb
Host	smart-fb4cd69c-af87-4c94-9b2f-b9e6690fec1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078207389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2078207389
Directory	/workspace/32.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3692376012
Short name	T695
Test name
Test status
Simulation time	1744888841 ps
CPU time	8.67 seconds
Started	Jan 07 01:23:04 PM PST 24
Finished	Jan 07 01:23:13 PM PST 24
Peak memory	216776 kb
Host	smart-f299e510-772d-42a4-b99b-a0dc7d975b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692376012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3692376012
Directory	/workspace/32.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_rw.3883238468
Short name	T100
Test name
Test status
Simulation time	97877994 ps
CPU time	2.33 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:23:00 PM PST 24
Peak memory	216980 kb
Host	smart-7f2d459f-866d-4bdb-9c53-657005ff1f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883238468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3883238468
Directory	/workspace/32.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_sts_read.3485367439
Short name	T1200
Test name
Test status
Simulation time	178666782 ps
CPU time	0.94 seconds
Started	Jan 07 01:23:08 PM PST 24
Finished	Jan 07 01:23:10 PM PST 24
Peak memory	206772 kb
Host	smart-e4106fdb-6724-4aa8-a566-aa51f094c7ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485367439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3485367439
Directory	/workspace/32.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/32.spi_device_tx_async_fifo_reset.1563378634
Short name	T872
Test name
Test status
Simulation time	49655384 ps
CPU time	0.77 seconds
Started	Jan 07 01:23:07 PM PST 24
Finished	Jan 07 01:23:09 PM PST 24
Peak memory	208480 kb
Host	smart-73c29447-0e8b-4964-a3dc-f3646844a384
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563378634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tx_async_fifo_reset.1563378634
Directory	/workspace/32.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/32.spi_device_txrx.4018041828
Short name	T1544
Test name
Test status
Simulation time	48599619140 ps
CPU time	375.62 seconds
Started	Jan 07 01:22:55 PM PST 24
Finished	Jan 07 01:29:14 PM PST 24
Peak memory	290340 kb
Host	smart-073e4bcc-a67b-441a-b0e9-57e855e7c206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018041828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_txrx.4018041828
Directory	/workspace/32.spi_device_txrx/latest

Test location	/workspace/coverage/default/32.spi_device_upload.289773396
Short name	T1309
Test name
Test status
Simulation time	4691265543 ps
CPU time	9.71 seconds
Started	Jan 07 01:23:06 PM PST 24
Finished	Jan 07 01:23:17 PM PST 24
Peak memory	225076 kb
Host	smart-7103971e-a874-4977-b157-80d4a2ac8986
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289773396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.289773396
Directory	/workspace/32.spi_device_upload/latest

Test location	/workspace/coverage/default/33.spi_device_abort.1729800492
Short name	T941
Test name
Test status
Simulation time	16419195 ps
CPU time	0.74 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:14 PM PST 24
Peak memory	206588 kb
Host	smart-0b9987b1-4838-42b2-8ec6-e60de5ebe56a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729800492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_abort.1729800492
Directory	/workspace/33.spi_device_abort/latest

Test location	/workspace/coverage/default/33.spi_device_alert_test.1887359872
Short name	T1351
Test name
Test status
Simulation time	31683024 ps
CPU time	0.74 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:23:15 PM PST 24
Peak memory	206444 kb
Host	smart-19e07209-7651-4e1a-9e69-742d9e5c3035
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887359872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 1887359872
Directory	/workspace/33.spi_device_alert_test/latest

Test location	/workspace/coverage/default/33.spi_device_bit_transfer.3448368193
Short name	T444
Test name
Test status
Simulation time	540423183 ps
CPU time	2.21 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:16 PM PST 24
Peak memory	216872 kb
Host	smart-32ce0859-2f8b-4c77-be35-b02d764e603e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448368193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_bit_transfer.3448368193
Directory	/workspace/33.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/33.spi_device_byte_transfer.2983824698
Short name	T605
Test name
Test status
Simulation time	581974494 ps
CPU time	2.93 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:17 PM PST 24
Peak memory	216744 kb
Host	smart-b99a8085-3000-4bb7-8146-b8bb48f6468f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983824698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_byte_transfer.2983824698
Directory	/workspace/33.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/33.spi_device_cfg_cmd.3639752714
Short name	T782
Test name
Test status
Simulation time	69309898493 ps
CPU time	13.21 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:27 PM PST 24
Peak memory	241556 kb
Host	smart-52fc8434-da3c-49fd-99b8-09035f746ef7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639752714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3639752714
Directory	/workspace/33.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/33.spi_device_csb_read.1381444036
Short name	T871
Test name
Test status
Simulation time	28073179 ps
CPU time	0.76 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:14 PM PST 24
Peak memory	206616 kb
Host	smart-43e3226c-ee68-43ed-886a-e971139dbe64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381444036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1381444036
Directory	/workspace/33.spi_device_csb_read/latest

Test location	/workspace/coverage/default/33.spi_device_dummy_item_extra_dly.2926739455
Short name	T110
Test name
Test status
Simulation time	50228907546 ps
CPU time	398.71 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:29:53 PM PST 24
Peak memory	281864 kb
Host	smart-292769d0-ac4b-440d-8199-39b3453ee040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926739455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_dummy_item_extra_dly.2926739455
Directory	/workspace/33.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/33.spi_device_extreme_fifo_size.2993884241
Short name	T428
Test name
Test status
Simulation time	2785262597 ps
CPU time	24.89 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:37 PM PST 24
Peak memory	232864 kb
Host	smart-9fc03070-cb48-471b-bd62-091c7d883c10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993884241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_extreme_fifo_size.2993884241
Directory	/workspace/33.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/33.spi_device_fifo_full.2609502665
Short name	T684
Test name
Test status
Simulation time	27400886302 ps
CPU time	273.18 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:27:47 PM PST 24
Peak memory	274228 kb
Host	smart-29d29e37-f992-4629-a09b-192c161259f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609502665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_full.2609502665
Directory	/workspace/33.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/33.spi_device_fifo_underflow_overflow.885941965
Short name	T1440
Test name
Test status
Simulation time	57650791833 ps
CPU time	160.17 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:25:54 PM PST 24
Peak memory	308652 kb
Host	smart-223a9522-8038-4d56-88d4-be7a2fefd6e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885941965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_fifo_underflow_overfl ow.885941965
Directory	/workspace/33.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/33.spi_device_flash_all.172129996
Short name	T192
Test name
Test status
Simulation time	76780753160 ps
CPU time	194.32 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:26:28 PM PST 24
Peak memory	257976 kb
Host	smart-078c921a-87b3-4a49-a800-7b64c70bef5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172129996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.172129996
Directory	/workspace/33.spi_device_flash_all/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm.1125564983
Short name	T1263
Test name
Test status
Simulation time	8073255582 ps
CPU time	114.05 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:25:07 PM PST 24
Peak memory	257072 kb
Host	smart-61d1b991-5b5c-4108-9cf3-922bc5303416
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125564983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1125564983
Directory	/workspace/33.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2212328553
Short name	T893
Test name
Test status
Simulation time	7511704743 ps
CPU time	93.84 seconds
Started	Jan 07 01:23:17 PM PST 24
Finished	Jan 07 01:24:52 PM PST 24
Peak memory	255084 kb
Host	smart-f80afb6e-c976-4251-a76e-7bcb658f445d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212328553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl e.2212328553
Directory	/workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/33.spi_device_flash_mode.148198164
Short name	T598
Test name
Test status
Simulation time	7523215063 ps
CPU time	42.49 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	254852 kb
Host	smart-dde0dae2-84ce-4da0-a100-4b9fc207a181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148198164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.148198164
Directory	/workspace/33.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/33.spi_device_intercept.4105037776
Short name	T1695
Test name
Test status
Simulation time	664348511 ps
CPU time	4.26 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:18 PM PST 24
Peak memory	239444 kb
Host	smart-aac8af98-0fc9-4671-aef3-18a5ec22e95d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105037776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4105037776
Directory	/workspace/33.spi_device_intercept/latest

Test location	/workspace/coverage/default/33.spi_device_intr.297955132
Short name	T441
Test name
Test status
Simulation time	41154601332 ps
CPU time	44.22 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	220932 kb
Host	smart-dd082686-8008-4d03-9fef-992fa6db3127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297955132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intr.297955132
Directory	/workspace/33.spi_device_intr/latest

Test location	/workspace/coverage/default/33.spi_device_mailbox.2970237351
Short name	T1489
Test name
Test status
Simulation time	16699357222 ps
CPU time	32.42 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:46 PM PST 24
Peak memory	266132 kb
Host	smart-352e96ba-73f9-4c85-b0df-8793d3469a79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970237351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2970237351
Directory	/workspace/33.spi_device_mailbox/latest

Test location	/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1097702705
Short name	T290
Test name
Test status
Simulation time	885892655 ps
CPU time	6.51 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	240788 kb
Host	smart-ba766b46-86e2-4608-9346-243fd6a4af41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097702705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa p.1097702705
Directory	/workspace/33.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/33.spi_device_pass_cmd_filtering.1909952732
Short name	T1076
Test name
Test status
Simulation time	1668319006 ps
CPU time	10.3 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:24 PM PST 24
Peak memory	223840 kb
Host	smart-2ba10186-f63c-463d-8840-96542112c84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909952732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1909952732
Directory	/workspace/33.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/33.spi_device_perf.246857015
Short name	T603
Test name
Test status
Simulation time	27275522883 ps
CPU time	465.83 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:30:59 PM PST 24
Peak memory	238544 kb
Host	smart-d4da19fb-e924-4eed-967c-5b63821ac3bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246857015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_perf.246857015
Directory	/workspace/33.spi_device_perf/latest

Test location	/workspace/coverage/default/33.spi_device_read_buffer_direct.1056514708
Short name	T1470
Test name
Test status
Simulation time	1243371832 ps
CPU time	6.07 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	220840 kb
Host	smart-04b8c3e9-b416-4e31-871b-084a3acd05fb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1056514708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.1056514708
Directory	/workspace/33.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/33.spi_device_rx_async_fifo_reset.1671741137
Short name	T1433
Test name
Test status
Simulation time	185513179 ps
CPU time	0.85 seconds
Started	Jan 07 01:23:10 PM PST 24
Finished	Jan 07 01:23:12 PM PST 24
Peak memory	208524 kb
Host	smart-6c2c9b75-d2e5-4d90-9849-94171278e74b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671741137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_async_fifo_reset.1671741137
Directory	/workspace/33.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/33.spi_device_rx_timeout.2134908022
Short name	T1338
Test name
Test status
Simulation time	673339314 ps
CPU time	5.62 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:23:20 PM PST 24
Peak memory	216848 kb
Host	smart-a1c1cdeb-7cd5-4ce5-9414-9bf168b7549a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134908022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_rx_timeout.2134908022
Directory	/workspace/33.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/33.spi_device_smoke.2709502886
Short name	T879
Test name
Test status
Simulation time	597611192 ps
CPU time	1.17 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:15 PM PST 24
Peak memory	217744 kb
Host	smart-22a33500-38dd-4d4d-8370-c67ca12132d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709502886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_smoke.2709502886
Directory	/workspace/33.spi_device_smoke/latest

Test location	/workspace/coverage/default/33.spi_device_stress_all.2832554300
Short name	T1106
Test name
Test status
Simulation time	62743216324 ps
CPU time	702.7 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:34:57 PM PST 24
Peak memory	329060 kb
Host	smart-2fdb15c6-1216-4bc1-8a7a-e617158bc7ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832554300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre ss_all.2832554300
Directory	/workspace/33.spi_device_stress_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_all.4274853614
Short name	T1656
Test name
Test status
Simulation time	2613492522 ps
CPU time	43.45 seconds
Started	Jan 07 01:23:10 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	216856 kb
Host	smart-15183983-d1d8-4929-be8d-8cabbcefd60e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274853614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4274853614
Directory	/workspace/33.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.516482981
Short name	T1000
Test name
Test status
Simulation time	7614210029 ps
CPU time	23.57 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:38 PM PST 24
Peak memory	216924 kb
Host	smart-da58f5b3-e53d-4860-aaa6-8e29897628af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516482981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.516482981
Directory	/workspace/33.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_rw.119811044
Short name	T1428
Test name
Test status
Simulation time	82254870 ps
CPU time	0.99 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:23:16 PM PST 24
Peak memory	208020 kb
Host	smart-b315805e-9b11-4cce-88ab-c55733d1d2c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119811044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.119811044
Directory	/workspace/33.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_sts_read.2377297373
Short name	T875
Test name
Test status
Simulation time	613866946 ps
CPU time	0.9 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:23:15 PM PST 24
Peak memory	206936 kb
Host	smart-6c759382-9396-480c-858c-297fe4dbb635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377297373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2377297373
Directory	/workspace/33.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/33.spi_device_tx_async_fifo_reset.3560912354
Short name	T1029
Test name
Test status
Simulation time	16054946 ps
CPU time	0.79 seconds
Started	Jan 07 01:23:15 PM PST 24
Finished	Jan 07 01:23:18 PM PST 24
Peak memory	208392 kb
Host	smart-f7d07216-6197-4181-8523-3b8175bff1d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560912354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tx_async_fifo_reset.3560912354
Directory	/workspace/33.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/33.spi_device_txrx.1567994249
Short name	T1504
Test name
Test status
Simulation time	9632256947 ps
CPU time	119.5 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	268360 kb
Host	smart-9019d944-85af-4ec9-8bf8-756ba25bb92b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567994249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_txrx.1567994249
Directory	/workspace/33.spi_device_txrx/latest

Test location	/workspace/coverage/default/33.spi_device_upload.59781191
Short name	T237
Test name
Test status
Simulation time	2202469538 ps
CPU time	11.53 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:24 PM PST 24
Peak memory	237784 kb
Host	smart-b02494bd-6435-4e30-b92f-203981e2a52d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59781191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.59781191
Directory	/workspace/33.spi_device_upload/latest

Test location	/workspace/coverage/default/34.spi_device_abort.758204650
Short name	T437
Test name
Test status
Simulation time	46861777 ps
CPU time	0.76 seconds
Started	Jan 07 01:23:42 PM PST 24
Finished	Jan 07 01:23:44 PM PST 24
Peak memory	206680 kb
Host	smart-b9ac8edc-baac-4496-a563-8df1a924e54b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758204650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_abort.758204650
Directory	/workspace/34.spi_device_abort/latest

Test location	/workspace/coverage/default/34.spi_device_alert_test.1762204983
Short name	T1237
Test name
Test status
Simulation time	36634641 ps
CPU time	0.7 seconds
Started	Jan 07 01:23:41 PM PST 24
Finished	Jan 07 01:23:43 PM PST 24
Peak memory	206380 kb
Host	smart-514a08a4-c13c-433e-ae6f-592b45c81502
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762204983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 1762204983
Directory	/workspace/34.spi_device_alert_test/latest

Test location	/workspace/coverage/default/34.spi_device_bit_transfer.3567404210
Short name	T593
Test name
Test status
Simulation time	258730295 ps
CPU time	2.69 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	216756 kb
Host	smart-a7b04a79-06d6-4c9f-bd33-43d54892e43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567404210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_bit_transfer.3567404210
Directory	/workspace/34.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/34.spi_device_byte_transfer.1880099031
Short name	T931
Test name
Test status
Simulation time	981090193 ps
CPU time	2.97 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:17 PM PST 24
Peak memory	216816 kb
Host	smart-f431d2ea-d367-4b85-b02a-0a690993b655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880099031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_byte_transfer.1880099031
Directory	/workspace/34.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/34.spi_device_cfg_cmd.2408070535
Short name	T1469
Test name
Test status
Simulation time	2065534925 ps
CPU time	5.32 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:23:58 PM PST 24
Peak memory	222176 kb
Host	smart-77bf2b3b-a79b-418d-bffc-1025d482eadd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408070535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2408070535
Directory	/workspace/34.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/34.spi_device_csb_read.313461842
Short name	T1199
Test name
Test status
Simulation time	21602121 ps
CPU time	0.78 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:23:15 PM PST 24
Peak memory	206556 kb
Host	smart-cd5d15b6-0a71-4845-a3ad-4f227610fc49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313461842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.313461842
Directory	/workspace/34.spi_device_csb_read/latest

Test location	/workspace/coverage/default/34.spi_device_dummy_item_extra_dly.2116367243
Short name	T442
Test name
Test status
Simulation time	205503605262 ps
CPU time	357.32 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:29:11 PM PST 24
Peak memory	272856 kb
Host	smart-b81b9749-ec46-4d28-92a5-4bc3addd31e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116367243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_dummy_item_extra_dly.2116367243
Directory	/workspace/34.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/34.spi_device_extreme_fifo_size.96299096
Short name	T524
Test name
Test status
Simulation time	4045054927 ps
CPU time	31.39 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:44 PM PST 24
Peak memory	223712 kb
Host	smart-22395804-7d49-4704-b86e-aee3a1e85121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96299096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_extreme_fifo_size.96299096
Directory	/workspace/34.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/34.spi_device_fifo_full.3205461791
Short name	T795
Test name
Test status
Simulation time	38088922652 ps
CPU time	594.34 seconds
Started	Jan 07 01:23:15 PM PST 24
Finished	Jan 07 01:33:11 PM PST 24
Peak memory	273744 kb
Host	smart-b07603ff-9ff8-4e16-a020-8a0f43ed7b74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205461791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_full.3205461791
Directory	/workspace/34.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/34.spi_device_fifo_underflow_overflow.3550158909
Short name	T1483
Test name
Test status
Simulation time	743637330882 ps
CPU time	1248.05 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:44:02 PM PST 24
Peak memory	507932 kb
Host	smart-558367c0-7ae3-4ff5-911e-286ad8f744f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550158909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_fifo_underflow_overf low.3550158909
Directory	/workspace/34.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/34.spi_device_flash_all.2547595900
Short name	T30
Test name
Test status
Simulation time	16089796999 ps
CPU time	89.6 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	255836 kb
Host	smart-60c1e867-639c-419f-a0e8-7ec9c2d49e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547595900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2547595900
Directory	/workspace/34.spi_device_flash_all/latest

Test location	/workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2460384975
Short name	T326
Test name
Test status
Simulation time	33875916265 ps
CPU time	103.21 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:25:34 PM PST 24
Peak memory	264852 kb
Host	smart-7a420755-742f-494c-a34c-756f95dc406b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460384975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl e.2460384975
Directory	/workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/34.spi_device_flash_mode.3749988425
Short name	T904
Test name
Test status
Simulation time	10963184796 ps
CPU time	49.83 seconds
Started	Jan 07 01:23:41 PM PST 24
Finished	Jan 07 01:24:32 PM PST 24
Peak memory	237824 kb
Host	smart-07fc6a4d-0ec7-4e4b-a44c-96eac8b58d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749988425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3749988425
Directory	/workspace/34.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/34.spi_device_intercept.2497714991
Short name	T899
Test name
Test status
Simulation time	5770492405 ps
CPU time	8.38 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	221628 kb
Host	smart-9dcf747d-d20e-4327-8df7-aaa6ace5ba07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497714991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2497714991
Directory	/workspace/34.spi_device_intercept/latest

Test location	/workspace/coverage/default/34.spi_device_intr.148162304
Short name	T830
Test name
Test status
Simulation time	41853174921 ps
CPU time	65.55 seconds
Started	Jan 07 01:23:12 PM PST 24
Finished	Jan 07 01:24:19 PM PST 24
Peak memory	240764 kb
Host	smart-af220845-93a6-4fe0-87a9-62196d1fe82d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=148162304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intr.148162304
Directory	/workspace/34.spi_device_intr/latest

Test location	/workspace/coverage/default/34.spi_device_mailbox.684082979
Short name	T1271
Test name
Test status
Simulation time	2150149955 ps
CPU time	14.23 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	230940 kb
Host	smart-3acfdb3d-2bb0-4673-ab9c-75504675e5b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684082979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.684082979
Directory	/workspace/34.spi_device_mailbox/latest

Test location	/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.151141209
Short name	T324
Test name
Test status
Simulation time	482286551 ps
CPU time	2.67 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	218152 kb
Host	smart-a9452546-cbb4-41da-9830-37964d87b4ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151141209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap .151141209
Directory	/workspace/34.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/34.spi_device_pass_cmd_filtering.3824975314
Short name	T1061
Test name
Test status
Simulation time	38057923205 ps
CPU time	22.93 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:23 PM PST 24
Peak memory	246268 kb
Host	smart-184c74ec-df25-44ee-a0d6-6265b36c200b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824975314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3824975314
Directory	/workspace/34.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/34.spi_device_perf.2563163170
Short name	T562
Test name
Test status
Simulation time	224485350856 ps
CPU time	2877.64 seconds
Started	Jan 07 01:23:13 PM PST 24
Finished	Jan 07 02:11:13 PM PST 24
Peak memory	288364 kb
Host	smart-717d1715-48bd-4e6e-8c2a-27eb1469d0ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2563163170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_perf.2563163170
Directory	/workspace/34.spi_device_perf/latest

Test location	/workspace/coverage/default/34.spi_device_read_buffer_direct.1514201382
Short name	T834
Test name
Test status
Simulation time	724630135 ps
CPU time	5.19 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:58 PM PST 24
Peak memory	218880 kb
Host	smart-0a0b1835-4e0c-45d3-b3a7-aba660e2f921
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1514201382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.1514201382
Directory	/workspace/34.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/34.spi_device_rx_async_fifo_reset.4273909970
Short name	T1465
Test name
Test status
Simulation time	17803360 ps
CPU time	0.88 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	208516 kb
Host	smart-4e5025df-4659-410f-9255-b6e7ebf59df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273909970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_async_fifo_reset.4273909970
Directory	/workspace/34.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/34.spi_device_rx_timeout.2480220705
Short name	T943
Test name
Test status
Simulation time	2397967060 ps
CPU time	5.77 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:02 PM PST 24
Peak memory	216964 kb
Host	smart-e53b87bd-ba60-48a1-bb5b-54e0183732f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480220705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_rx_timeout.2480220705
Directory	/workspace/34.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/34.spi_device_smoke.3490293076
Short name	T1314
Test name
Test status
Simulation time	41629348 ps
CPU time	1.13 seconds
Started	Jan 07 01:23:11 PM PST 24
Finished	Jan 07 01:23:13 PM PST 24
Peak memory	216752 kb
Host	smart-77e0678e-04e3-4015-9a7e-68f11997bf37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490293076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_smoke.3490293076
Directory	/workspace/34.spi_device_smoke/latest

Test location	/workspace/coverage/default/34.spi_device_stress_all.3271862263
Short name	T161
Test name
Test status
Simulation time	104102686468 ps
CPU time	838.74 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:37:54 PM PST 24
Peak memory	287484 kb
Host	smart-3ba0791d-97fe-413d-a155-221baf32b76d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271862263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre ss_all.3271862263
Directory	/workspace/34.spi_device_stress_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_all.2328438150
Short name	T346
Test name
Test status
Simulation time	4343670894 ps
CPU time	10.01 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	216880 kb
Host	smart-d7088ad8-abfe-4c03-aaf5-bdd52f9be1d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328438150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2328438150
Directory	/workspace/34.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2001291260
Short name	T1145
Test name
Test status
Simulation time	1117986236 ps
CPU time	7.65 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:24:02 PM PST 24
Peak memory	216752 kb
Host	smart-66c65536-2fba-4a10-9af5-f28c344df35c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001291260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2001291260
Directory	/workspace/34.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_rw.3751139156
Short name	T347
Test name
Test status
Simulation time	221385995 ps
CPU time	2.44 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:53 PM PST 24
Peak memory	216900 kb
Host	smart-e3c47138-eebf-4e4c-8e12-45505954cf44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751139156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3751139156
Directory	/workspace/34.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_sts_read.1873452961
Short name	T734
Test name
Test status
Simulation time	68481858 ps
CPU time	0.96 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	207980 kb
Host	smart-bf2f9c62-9177-44a3-ada3-e078ccd0971c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873452961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1873452961
Directory	/workspace/34.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/34.spi_device_tx_async_fifo_reset.391009309
Short name	T1583
Test name
Test status
Simulation time	52703607 ps
CPU time	0.78 seconds
Started	Jan 07 01:23:41 PM PST 24
Finished	Jan 07 01:23:43 PM PST 24
Peak memory	208392 kb
Host	smart-c940f50a-65fe-4b84-906b-d8475fa716a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391009309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tx_async_fifo_reset.391009309
Directory	/workspace/34.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/34.spi_device_txrx.1381867321
Short name	T914
Test name
Test status
Simulation time	119421572379 ps
CPU time	614.83 seconds
Started	Jan 07 01:23:16 PM PST 24
Finished	Jan 07 01:33:33 PM PST 24
Peak memory	250372 kb
Host	smart-1d034a4e-8710-40db-85db-4e6100a800f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381867321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_txrx.1381867321
Directory	/workspace/34.spi_device_txrx/latest

Test location	/workspace/coverage/default/34.spi_device_upload.2574960983
Short name	T286
Test name
Test status
Simulation time	501861628 ps
CPU time	3.67 seconds
Started	Jan 07 01:23:42 PM PST 24
Finished	Jan 07 01:23:49 PM PST 24
Peak memory	221068 kb
Host	smart-1aea190b-7952-43f4-9c99-bc78cd4ec353
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574960983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2574960983
Directory	/workspace/34.spi_device_upload/latest

Test location	/workspace/coverage/default/35.spi_device_abort.2547711725
Short name	T1701
Test name
Test status
Simulation time	91564369 ps
CPU time	0.74 seconds
Started	Jan 07 01:23:42 PM PST 24
Finished	Jan 07 01:23:45 PM PST 24
Peak memory	206680 kb
Host	smart-b3ba8585-66d8-4b78-959a-557e44d897d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547711725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_abort.2547711725
Directory	/workspace/35.spi_device_abort/latest

Test location	/workspace/coverage/default/35.spi_device_alert_test.42817538
Short name	T1551
Test name
Test status
Simulation time	31440313 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	206544 kb
Host	smart-c619d790-fab4-4d33-9818-91a3a4ab24d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42817538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.42817538
Directory	/workspace/35.spi_device_alert_test/latest

Test location	/workspace/coverage/default/35.spi_device_bit_transfer.2995740604
Short name	T793
Test name
Test status
Simulation time	173874303 ps
CPU time	2.58 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:56 PM PST 24
Peak memory	216712 kb
Host	smart-b7b2f91b-51b9-4298-8368-b7d405ee5d8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995740604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_bit_transfer.2995740604
Directory	/workspace/35.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/35.spi_device_byte_transfer.2391166915
Short name	T776
Test name
Test status
Simulation time	1065793868 ps
CPU time	2.32 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	216768 kb
Host	smart-1161a28e-46e6-4925-a1d2-6b949fc46ba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391166915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_byte_transfer.2391166915
Directory	/workspace/35.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/35.spi_device_cfg_cmd.455384384
Short name	T638
Test name
Test status
Simulation time	731375971 ps
CPU time	3.18 seconds
Started	Jan 07 01:23:41 PM PST 24
Finished	Jan 07 01:23:47 PM PST 24
Peak memory	218164 kb
Host	smart-e438234f-0162-49b6-a60f-17dfd825fc9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455384384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.455384384
Directory	/workspace/35.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/35.spi_device_csb_read.3618402135
Short name	T566
Test name
Test status
Simulation time	50188681 ps
CPU time	0.77 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	206532 kb
Host	smart-bb62d81c-a53f-4beb-90ff-8fefa809b006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618402135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3618402135
Directory	/workspace/35.spi_device_csb_read/latest

Test location	/workspace/coverage/default/35.spi_device_dummy_item_extra_dly.1907501501
Short name	T465
Test name
Test status
Simulation time	79471089198 ps
CPU time	184.99 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:26:58 PM PST 24
Peak memory	257304 kb
Host	smart-d408b1c4-e82a-4ed6-b9f5-d9445afd20a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907501501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_dummy_item_extra_dly.1907501501
Directory	/workspace/35.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/35.spi_device_extreme_fifo_size.1715716407
Short name	T1627
Test name
Test status
Simulation time	355120535299 ps
CPU time	800.73 seconds
Started	Jan 07 01:23:41 PM PST 24
Finished	Jan 07 01:37:03 PM PST 24
Peak memory	221044 kb
Host	smart-e79fdb7b-cb59-4c42-9b44-7200915166ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715716407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_extreme_fifo_size.1715716407
Directory	/workspace/35.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/35.spi_device_fifo_full.414148566
Short name	T1715
Test name
Test status
Simulation time	119124641003 ps
CPU time	235.9 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:27:48 PM PST 24
Peak memory	267376 kb
Host	smart-f4b29929-74cb-49f0-b13f-2f768a28b253
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414148566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_full.414148566
Directory	/workspace/35.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/35.spi_device_fifo_underflow_overflow.2217395909
Short name	T736
Test name
Test status
Simulation time	978621163726 ps
CPU time	1171.4 seconds
Started	Jan 07 01:23:39 PM PST 24
Finished	Jan 07 01:43:12 PM PST 24
Peak memory	606324 kb
Host	smart-b686f42b-a981-49df-892b-e962ce2664e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217395909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_fifo_underflow_overf low.2217395909
Directory	/workspace/35.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/35.spi_device_flash_and_tpm.137182522
Short name	T268
Test name
Test status
Simulation time	9053440873 ps
CPU time	31.94 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:24:24 PM PST 24
Peak memory	225248 kb
Host	smart-136d281a-6eac-4a94-a9cf-627b9af1ce05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137182522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.137182522
Directory	/workspace/35.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/35.spi_device_flash_mode.3594203685
Short name	T981
Test name
Test status
Simulation time	56701413050 ps
CPU time	54.86 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:51 PM PST 24
Peak memory	250344 kb
Host	smart-5e6b338c-5dbf-4368-b354-3715568477b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594203685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3594203685
Directory	/workspace/35.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/35.spi_device_intercept.3797922862
Short name	T214
Test name
Test status
Simulation time	15532365933 ps
CPU time	14.17 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:24:07 PM PST 24
Peak memory	221896 kb
Host	smart-267f0700-10c9-43d2-b9bc-a9ed4fcdf4c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797922862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3797922862
Directory	/workspace/35.spi_device_intercept/latest

Test location	/workspace/coverage/default/35.spi_device_intr.3488717586
Short name	T1129
Test name
Test status
Simulation time	28836043852 ps
CPU time	66.23 seconds
Started	Jan 07 01:23:48 PM PST 24
Finished	Jan 07 01:24:55 PM PST 24
Peak memory	241588 kb
Host	smart-9ec89422-d5b6-48a4-8507-fedd07a8ca59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488717586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intr.3488717586
Directory	/workspace/35.spi_device_intr/latest

Test location	/workspace/coverage/default/35.spi_device_mailbox.1027367706
Short name	T741
Test name
Test status
Simulation time	557562189 ps
CPU time	5.31 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:03 PM PST 24
Peak memory	218416 kb
Host	smart-d7b32e65-28b6-42d3-b530-94019e3f8832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027367706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1027367706
Directory	/workspace/35.spi_device_mailbox/latest

Test location	/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2132858124
Short name	T292
Test name
Test status
Simulation time	66375117 ps
CPU time	2.97 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:54 PM PST 24
Peak memory	234276 kb
Host	smart-3cd3843e-40c0-4fba-84f8-b7964a463708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132858124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.2132858124
Directory	/workspace/35.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/35.spi_device_pass_cmd_filtering.3325285345
Short name	T245
Test name
Test status
Simulation time	1109325674 ps
CPU time	6.08 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	240220 kb
Host	smart-722dffde-485c-422c-81b1-4b7ca979ef63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325285345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3325285345
Directory	/workspace/35.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/35.spi_device_perf.460681829
Short name	T1431
Test name
Test status
Simulation time	33132945844 ps
CPU time	348.83 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:29:45 PM PST 24
Peak memory	249700 kb
Host	smart-8eacb543-30f2-4bad-98da-6d57851f8e38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460681829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_perf.460681829
Directory	/workspace/35.spi_device_perf/latest

Test location	/workspace/coverage/default/35.spi_device_read_buffer_direct.4127247260
Short name	T1404
Test name
Test status
Simulation time	7660303629 ps
CPU time	7.93 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:24:03 PM PST 24
Peak memory	218944 kb
Host	smart-802a54cf-a7d6-4a87-8d64-3beadad16aa8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4127247260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir ect.4127247260
Directory	/workspace/35.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/35.spi_device_rx_async_fifo_reset.35018099
Short name	T901
Test name
Test status
Simulation time	18741944 ps
CPU time	0.87 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:51 PM PST 24
Peak memory	208476 kb
Host	smart-93fbbd1b-febc-4239-8ead-45ba5eb634f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35018099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_async_fifo_reset.35018099
Directory	/workspace/35.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/35.spi_device_rx_timeout.3399425128
Short name	T1557
Test name
Test status
Simulation time	4503884071 ps
CPU time	5.48 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:56 PM PST 24
Peak memory	216956 kb
Host	smart-b3393aa5-6f51-4e39-aece-33cf1b500e3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399425128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_rx_timeout.3399425128
Directory	/workspace/35.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/35.spi_device_smoke.3330391341
Short name	T650
Test name
Test status
Simulation time	131866207 ps
CPU time	0.92 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:59 PM PST 24
Peak memory	207844 kb
Host	smart-f8cb6f69-ff6b-4dae-a005-ea4d13678070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330391341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_smoke.3330391341
Directory	/workspace/35.spi_device_smoke/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_all.1144528166
Short name	T637
Test name
Test status
Simulation time	1186744959 ps
CPU time	19.84 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	220088 kb
Host	smart-e72909d2-2b73-4423-b8c6-5372d9290e39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144528166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1144528166
Directory	/workspace/35.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3968807626
Short name	T1589
Test name
Test status
Simulation time	22542511938 ps
CPU time	35.62 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:33 PM PST 24
Peak memory	216708 kb
Host	smart-8fd1870f-5b9a-478f-80e2-2f9f5be12162
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968807626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3968807626
Directory	/workspace/35.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_rw.3810599795
Short name	T450
Test name
Test status
Simulation time	54189582 ps
CPU time	1.78 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	218532 kb
Host	smart-3ff4aee5-9fbd-4608-b19a-d5f6062b0190
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810599795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3810599795
Directory	/workspace/35.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_sts_read.3288043616
Short name	T1188
Test name
Test status
Simulation time	174234397 ps
CPU time	0.88 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:54 PM PST 24
Peak memory	206928 kb
Host	smart-862aec32-85a9-40c2-a1d0-39af0e4f843c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288043616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3288043616
Directory	/workspace/35.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/35.spi_device_tx_async_fifo_reset.1632595488
Short name	T1203
Test name
Test status
Simulation time	26576086 ps
CPU time	0.82 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	208572 kb
Host	smart-878b6f5d-8588-4408-8955-e0bb096861eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632595488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tx_async_fifo_reset.1632595488
Directory	/workspace/35.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/35.spi_device_txrx.82641136
Short name	T538
Test name
Test status
Simulation time	11127075419 ps
CPU time	139.36 seconds
Started	Jan 07 01:23:50 PM PST 24
Finished	Jan 07 01:26:11 PM PST 24
Peak memory	275476 kb
Host	smart-d922103b-164b-4f4b-b936-34f74604b23c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82641136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_txrx.82641136
Directory	/workspace/35.spi_device_txrx/latest

Test location	/workspace/coverage/default/35.spi_device_upload.1717910353
Short name	T727
Test name
Test status
Simulation time	1251679411 ps
CPU time	6.83 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:24:02 PM PST 24
Peak memory	241316 kb
Host	smart-cd96e383-74f0-4fa1-bb73-80698fa92068
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717910353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1717910353
Directory	/workspace/35.spi_device_upload/latest

Test location	/workspace/coverage/default/36.spi_device_abort.3389431395
Short name	T1008
Test name
Test status
Simulation time	28793006 ps
CPU time	0.74 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	206648 kb
Host	smart-b5d66d59-b277-4514-b69d-ae835460061e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389431395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_abort.3389431395
Directory	/workspace/36.spi_device_abort/latest

Test location	/workspace/coverage/default/36.spi_device_alert_test.467732369
Short name	T820
Test name
Test status
Simulation time	32195941 ps
CPU time	0.71 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:24:15 PM PST 24
Peak memory	206416 kb
Host	smart-2f457673-5801-4690-bd1f-333db8ed15ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467732369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.467732369
Directory	/workspace/36.spi_device_alert_test/latest

Test location	/workspace/coverage/default/36.spi_device_bit_transfer.3924522242
Short name	T529
Test name
Test status
Simulation time	207780437 ps
CPU time	1.82 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	216804 kb
Host	smart-d5125dec-9151-472d-80dd-e78830a6b39e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924522242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_bit_transfer.3924522242
Directory	/workspace/36.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/36.spi_device_byte_transfer.2100809148
Short name	T812
Test name
Test status
Simulation time	1573762778 ps
CPU time	3.18 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	216752 kb
Host	smart-80fc6474-de90-453c-9f1c-adfbbaf9e7bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100809148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_byte_transfer.2100809148
Directory	/workspace/36.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/36.spi_device_cfg_cmd.654337231
Short name	T1700
Test name
Test status
Simulation time	67962406 ps
CPU time	2.55 seconds
Started	Jan 07 01:24:41 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	237380 kb
Host	smart-c07dd1c2-ed5d-4c83-b69e-96e8ec90291a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654337231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.654337231
Directory	/workspace/36.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/36.spi_device_csb_read.3000760709
Short name	T1035
Test name
Test status
Simulation time	18611607 ps
CPU time	0.78 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	206412 kb
Host	smart-637f6351-3dde-463b-9ba7-98a8e1466011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3000760709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3000760709
Directory	/workspace/36.spi_device_csb_read/latest

Test location	/workspace/coverage/default/36.spi_device_dummy_item_extra_dly.3456626227
Short name	T1238
Test name
Test status
Simulation time	88897031057 ps
CPU time	396.02 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:30:39 PM PST 24
Peak memory	244512 kb
Host	smart-6ee073ce-749b-42a9-b1e5-5fb8b082f188
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456626227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_dummy_item_extra_dly.3456626227
Directory	/workspace/36.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/36.spi_device_extreme_fifo_size.3562952053
Short name	T1296
Test name
Test status
Simulation time	143802577795 ps
CPU time	1201.81 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:44:02 PM PST 24
Peak memory	220172 kb
Host	smart-a08b2cb2-a22a-4f5a-9866-88d82c4914ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562952053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_extreme_fifo_size.3562952053
Directory	/workspace/36.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/36.spi_device_fifo_full.1072029990
Short name	T1687
Test name
Test status
Simulation time	201220079642 ps
CPU time	2557.85 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 02:06:37 PM PST 24
Peak memory	319816 kb
Host	smart-4c3c89f3-6afc-40f4-993a-b404f8500426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072029990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_full.1072029990
Directory	/workspace/36.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/36.spi_device_fifo_underflow_overflow.4198149119
Short name	T1618
Test name
Test status
Simulation time	67644514470 ps
CPU time	355.86 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:29:55 PM PST 24
Peak memory	393016 kb
Host	smart-de1770a9-bf10-4581-8494-9100ef1157a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198149119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_fifo_underflow_overf low.4198149119
Directory	/workspace/36.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/36.spi_device_flash_all.1059732083
Short name	T19
Test name
Test status
Simulation time	11304254514 ps
CPU time	40.48 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:44 PM PST 24
Peak memory	224632 kb
Host	smart-1c621599-6e17-4f16-9e99-6a9562f80695
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059732083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1059732083
Directory	/workspace/36.spi_device_flash_all/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm.3820792409
Short name	T1024
Test name
Test status
Simulation time	9562806356 ps
CPU time	114.5 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:25:58 PM PST 24
Peak memory	264248 kb
Host	smart-93f996d4-b723-4f2c-8475-fba2314afc87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820792409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3820792409
Directory	/workspace/36.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4016257218
Short name	T1099
Test name
Test status
Simulation time	13070124152 ps
CPU time	51.54 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	241564 kb
Host	smart-916ffc98-509f-4819-81c6-81815e8b2ff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016257218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl e.4016257218
Directory	/workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/36.spi_device_flash_mode.689184729
Short name	T334
Test name
Test status
Simulation time	18453697218 ps
CPU time	26.26 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:37 PM PST 24
Peak memory	237324 kb
Host	smart-8157785a-4750-436b-9690-8fe00b120afa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689184729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.689184729
Directory	/workspace/36.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/36.spi_device_intercept.732383410
Short name	T1214
Test name
Test status
Simulation time	3272911961 ps
CPU time	8.5 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:22 PM PST 24
Peak memory	220928 kb
Host	smart-47fba1eb-f69e-48c3-9a53-628e4ea46273
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732383410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.732383410
Directory	/workspace/36.spi_device_intercept/latest

Test location	/workspace/coverage/default/36.spi_device_intr.2708317927
Short name	T546
Test name
Test status
Simulation time	18853706485 ps
CPU time	46.16 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:46 PM PST 24
Peak memory	221212 kb
Host	smart-2cd6ec9f-26a5-4648-adcc-a1512599d586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708317927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intr.2708317927
Directory	/workspace/36.spi_device_intr/latest

Test location	/workspace/coverage/default/36.spi_device_mailbox.2705410622
Short name	T1151
Test name
Test status
Simulation time	76555800186 ps
CPU time	21.15 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:25 PM PST 24
Peak memory	235588 kb
Host	smart-dc9546d2-03d3-4f0a-886b-e5a35fb952f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705410622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2705410622
Directory	/workspace/36.spi_device_mailbox/latest

Test location	/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1277487699
Short name	T1301
Test name
Test status
Simulation time	4551688740 ps
CPU time	8.56 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:09 PM PST 24
Peak memory	218380 kb
Host	smart-44e4e189-b27e-442e-97c1-924156e0a83c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277487699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa p.1277487699
Directory	/workspace/36.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/36.spi_device_pass_cmd_filtering.1184944598
Short name	T1197
Test name
Test status
Simulation time	203941647 ps
CPU time	4.02 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	239400 kb
Host	smart-ae6a8cce-4454-499e-b97a-40fe52460803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184944598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1184944598
Directory	/workspace/36.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/36.spi_device_perf.1852706472
Short name	T528
Test name
Test status
Simulation time	83174132828 ps
CPU time	259.42 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:28:18 PM PST 24
Peak memory	300168 kb
Host	smart-3e8bae17-9898-46e3-92e8-cf8dbe545aaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852706472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_perf.1852706472
Directory	/workspace/36.spi_device_perf/latest

Test location	/workspace/coverage/default/36.spi_device_read_buffer_direct.1637183208
Short name	T784
Test name
Test status
Simulation time	4713372078 ps
CPU time	5.93 seconds
Started	Jan 07 01:24:26 PM PST 24
Finished	Jan 07 01:24:55 PM PST 24
Peak memory	218992 kb
Host	smart-8bdb5843-b2d2-436a-8ac3-22e8b9cf190c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1637183208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.1637183208
Directory	/workspace/36.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/36.spi_device_rx_async_fifo_reset.1357402600
Short name	T900
Test name
Test status
Simulation time	45211985 ps
CPU time	0.85 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	208452 kb
Host	smart-ec4a8074-364d-40fe-b7bc-55e348f943df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357402600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_async_fifo_reset.1357402600
Directory	/workspace/36.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/36.spi_device_rx_timeout.2186734917
Short name	T1114
Test name
Test status
Simulation time	2447248864 ps
CPU time	5.61 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:06 PM PST 24
Peak memory	216872 kb
Host	smart-4a7f4b9c-5839-4ff0-a8d8-00aec158affe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186734917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_rx_timeout.2186734917
Directory	/workspace/36.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/36.spi_device_smoke.1466345752
Short name	T202
Test name
Test status
Simulation time	277367783 ps
CPU time	1.27 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	216896 kb
Host	smart-88e9bf80-f4e8-4ef7-9dd7-fa88f0a23dbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466345752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_smoke.1466345752
Directory	/workspace/36.spi_device_smoke/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_all.440262725
Short name	T704
Test name
Test status
Simulation time	1044568846 ps
CPU time	13.69 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:15 PM PST 24
Peak memory	216912 kb
Host	smart-265f0df1-e33d-416b-9e53-1348b910d6c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440262725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.440262725
Directory	/workspace/36.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.314609226
Short name	T1201
Test name
Test status
Simulation time	7452082587 ps
CPU time	12.12 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:12 PM PST 24
Peak memory	216952 kb
Host	smart-6dfc5bc7-1413-45f9-8821-6049e31062cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=314609226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.314609226
Directory	/workspace/36.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_rw.989078131
Short name	T49
Test name
Test status
Simulation time	62406878 ps
CPU time	3.53 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	216800 kb
Host	smart-8bae31af-6ccc-4eb9-85a7-92f992180def
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989078131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.989078131
Directory	/workspace/36.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_sts_read.2644131750
Short name	T1673
Test name
Test status
Simulation time	143284114 ps
CPU time	1.2 seconds
Started	Jan 07 01:23:58 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	207952 kb
Host	smart-721f0610-d951-476b-926f-3f0e0b418f93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644131750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2644131750
Directory	/workspace/36.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/36.spi_device_tx_async_fifo_reset.472443725
Short name	T701
Test name
Test status
Simulation time	56441887 ps
CPU time	0.81 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	208428 kb
Host	smart-2ba1ef23-7337-4534-bac2-da48f52ddda0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472443725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tx_async_fifo_reset.472443725
Directory	/workspace/36.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/36.spi_device_txrx.2454812386
Short name	T1149
Test name
Test status
Simulation time	15309405829 ps
CPU time	170.69 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:26:52 PM PST 24
Peak memory	301124 kb
Host	smart-fc2f8863-51ed-4ddf-89f6-66fe9e2375d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454812386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_txrx.2454812386
Directory	/workspace/36.spi_device_txrx/latest

Test location	/workspace/coverage/default/36.spi_device_upload.3475621886
Short name	T954
Test name
Test status
Simulation time	1696236470 ps
CPU time	13.96 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:18 PM PST 24
Peak memory	233324 kb
Host	smart-25e9854e-4c02-44ec-bdff-dd412f55e5ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475621886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3475621886
Directory	/workspace/36.spi_device_upload/latest

Test location	/workspace/coverage/default/37.spi_device_abort.2041905439
Short name	T1216
Test name
Test status
Simulation time	14810617 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:55 PM PST 24
Peak memory	206616 kb
Host	smart-eec09889-0064-4e52-9867-fcbb12118ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041905439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_abort.2041905439
Directory	/workspace/37.spi_device_abort/latest

Test location	/workspace/coverage/default/37.spi_device_alert_test.3942437266
Short name	T789
Test name
Test status
Simulation time	15755598 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	206424 kb
Host	smart-0ebeb6f5-797e-4106-90d6-fb0e5b59a021
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942437266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test. 3942437266
Directory	/workspace/37.spi_device_alert_test/latest

Test location	/workspace/coverage/default/37.spi_device_bit_transfer.2486511558
Short name	T707
Test name
Test status
Simulation time	1011444385 ps
CPU time	2.48 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:54 PM PST 24
Peak memory	216768 kb
Host	smart-7e3d4fe2-0cc1-4101-ab88-1caf194ad7b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486511558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_bit_transfer.2486511558
Directory	/workspace/37.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/37.spi_device_byte_transfer.2763582847
Short name	T710
Test name
Test status
Simulation time	77092976 ps
CPU time	2.72 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	216768 kb
Host	smart-1992f7bb-9dfa-40ef-89dd-6b2a6daf4c52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763582847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_byte_transfer.2763582847
Directory	/workspace/37.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/37.spi_device_cfg_cmd.2071445488
Short name	T1427
Test name
Test status
Simulation time	23593996594 ps
CPU time	10.81 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:11 PM PST 24
Peak memory	222756 kb
Host	smart-aa1d0d61-ecfd-4ed3-ac3d-fa1799be6f95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071445488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2071445488
Directory	/workspace/37.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/37.spi_device_csb_read.1823190655
Short name	T1171
Test name
Test status
Simulation time	23580437 ps
CPU time	0.79 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	207580 kb
Host	smart-35285e60-0de3-4420-943a-9b0d8a4b3bfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823190655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1823190655
Directory	/workspace/37.spi_device_csb_read/latest

Test location	/workspace/coverage/default/37.spi_device_dummy_item_extra_dly.3080659677
Short name	T606
Test name
Test status
Simulation time	367399951258 ps
CPU time	149.76 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:27:27 PM PST 24
Peak memory	263160 kb
Host	smart-00f7a394-030f-4094-846a-473f7a4c380c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080659677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_dummy_item_extra_dly.3080659677
Directory	/workspace/37.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/37.spi_device_extreme_fifo_size.3838452419
Short name	T1682
Test name
Test status
Simulation time	51621676140 ps
CPU time	684.02 seconds
Started	Jan 07 01:24:21 PM PST 24
Finished	Jan 07 01:35:52 PM PST 24
Peak memory	218084 kb
Host	smart-550930d7-22f5-4b8d-a137-2bd09e641cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838452419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_extreme_fifo_size.3838452419
Directory	/workspace/37.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/37.spi_device_fifo_full.3114050426
Short name	T597
Test name
Test status
Simulation time	25385478019 ps
CPU time	462.56 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:31:56 PM PST 24
Peak memory	274344 kb
Host	smart-9d812b7f-05ef-4fc6-ae14-7476a0976941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114050426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_full.3114050426
Directory	/workspace/37.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/37.spi_device_fifo_underflow_overflow.1960700740
Short name	T58
Test name
Test status
Simulation time	109844035937 ps
CPU time	358.72 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:31:08 PM PST 24
Peak memory	414928 kb
Host	smart-fb4cb678-9fc3-4574-ad29-6437cacfc227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960700740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_fifo_underflow_overf low.1960700740
Directory	/workspace/37.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/37.spi_device_flash_all.1409989490
Short name	T1615
Test name
Test status
Simulation time	21550352346 ps
CPU time	14.03 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:10 PM PST 24
Peak memory	240692 kb
Host	smart-2caecbda-3aae-4d71-a2af-a659b7c49392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409989490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1409989490
Directory	/workspace/37.spi_device_flash_all/latest

Test location	/workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2626058561
Short name	T256
Test name
Test status
Simulation time	30899011886 ps
CPU time	284.66 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:28:41 PM PST 24
Peak memory	266080 kb
Host	smart-9f85c574-90cc-4ef7-b693-9424eb1a9ae7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626058561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl e.2626058561
Directory	/workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/37.spi_device_flash_mode.947750523
Short name	T1187
Test name
Test status
Simulation time	1221264697 ps
CPU time	12.52 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:10 PM PST 24
Peak memory	240716 kb
Host	smart-b564c21c-095c-4cdb-86c0-e91548e27cc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947750523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.947750523
Directory	/workspace/37.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/37.spi_device_intercept.989879120
Short name	T1253
Test name
Test status
Simulation time	2587791345 ps
CPU time	6.93 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	238764 kb
Host	smart-74437b5b-a7d5-4b96-add7-46ff394f5035
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989879120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.989879120
Directory	/workspace/37.spi_device_intercept/latest

Test location	/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1139280977
Short name	T24
Test name
Test status
Simulation time	597176797 ps
CPU time	2.59 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:58 PM PST 24
Peak memory	218188 kb
Host	smart-acc20991-88d6-49e0-9e6d-11bba00129e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139280977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa p.1139280977
Directory	/workspace/37.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/37.spi_device_pass_cmd_filtering.2635305167
Short name	T1074
Test name
Test status
Simulation time	259092558 ps
CPU time	4.67 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:56 PM PST 24
Peak memory	236788 kb
Host	smart-799f2f32-ccf6-437a-8ae3-ee6df4d3c638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635305167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2635305167
Directory	/workspace/37.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/37.spi_device_perf.2503417571
Short name	T1706
Test name
Test status
Simulation time	12158075765 ps
CPU time	289.08 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:29:03 PM PST 24
Peak memory	273008 kb
Host	smart-2cdf36c4-587e-48e9-8fb1-192c3d790031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503417571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_perf.2503417571
Directory	/workspace/37.spi_device_perf/latest

Test location	/workspace/coverage/default/37.spi_device_read_buffer_direct.1477342511
Short name	T829
Test name
Test status
Simulation time	1898715986 ps
CPU time	8.77 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	234548 kb
Host	smart-7279d049-1867-43e0-9e69-899cf0288a8f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1477342511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.1477342511
Directory	/workspace/37.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/37.spi_device_rx_async_fifo_reset.1744420163
Short name	T850
Test name
Test status
Simulation time	22669285 ps
CPU time	0.88 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	208540 kb
Host	smart-6f5901b5-b97b-4754-84c1-ab3dade0ddcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744420163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_async_fifo_reset.1744420163
Directory	/workspace/37.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/37.spi_device_rx_timeout.210060006
Short name	T1576
Test name
Test status
Simulation time	2208090808 ps
CPU time	5.24 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	216812 kb
Host	smart-7273b999-5e59-4601-868e-663b5310b013
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210060006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_rx_timeout.210060006
Directory	/workspace/37.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/37.spi_device_smoke.2515312774
Short name	T504
Test name
Test status
Simulation time	46592773 ps
CPU time	0.91 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:24:15 PM PST 24
Peak memory	208080 kb
Host	smart-ee57aa67-afd3-4851-97df-4c6642d9a115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515312774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_smoke.2515312774
Directory	/workspace/37.spi_device_smoke/latest

Test location	/workspace/coverage/default/37.spi_device_stress_all.3627488378
Short name	T1626
Test name
Test status
Simulation time	73645933879 ps
CPU time	2179.86 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 02:00:19 PM PST 24
Peak memory	388948 kb
Host	smart-4ddf7a26-b418-49ac-8e4b-8e36eecc6963
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627488378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre ss_all.3627488378
Directory	/workspace/37.spi_device_stress_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_all.1859070221
Short name	T1523
Test name
Test status
Simulation time	5279101534 ps
CPU time	22.31 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:20 PM PST 24
Peak memory	220412 kb
Host	smart-892f4b81-c3f0-4a08-a527-2a7423820223
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859070221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1859070221
Directory	/workspace/37.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3630680837
Short name	T921
Test name
Test status
Simulation time	206770794 ps
CPU time	1.51 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	208360 kb
Host	smart-2d9aefdc-c8c4-428e-bda7-fd7006dca7c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630680837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3630680837
Directory	/workspace/37.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_rw.4273406115
Short name	T767
Test name
Test status
Simulation time	265943449 ps
CPU time	3.17 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:58 PM PST 24
Peak memory	216820 kb
Host	smart-d7094feb-ac2c-4d12-aa58-b3654eca6c13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273406115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4273406115
Directory	/workspace/37.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_sts_read.2181519651
Short name	T1512
Test name
Test status
Simulation time	138161463 ps
CPU time	0.77 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:58 PM PST 24
Peak memory	206940 kb
Host	smart-0d8b637f-e8d1-4da9-9274-73751ecb232d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181519651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2181519651
Directory	/workspace/37.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/37.spi_device_tx_async_fifo_reset.1390096862
Short name	T1326
Test name
Test status
Simulation time	116050531 ps
CPU time	0.78 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	208420 kb
Host	smart-eb5eef38-d712-428f-a454-118125447bda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390096862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tx_async_fifo_reset.1390096862
Directory	/workspace/37.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/37.spi_device_txrx.3770781416
Short name	T1048
Test name
Test status
Simulation time	72550616948 ps
CPU time	138.45 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:26:29 PM PST 24
Peak memory	240980 kb
Host	smart-c1a5d4f4-7134-460b-94ef-815a1fc7d755
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770781416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_txrx.3770781416
Directory	/workspace/37.spi_device_txrx/latest

Test location	/workspace/coverage/default/37.spi_device_upload.1202218905
Short name	T1445
Test name
Test status
Simulation time	410244580 ps
CPU time	3.31 seconds
Started	Jan 07 01:23:48 PM PST 24
Finished	Jan 07 01:23:53 PM PST 24
Peak memory	239188 kb
Host	smart-7b138b8c-05d7-435f-8e45-a2b0f027bb2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202218905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1202218905
Directory	/workspace/37.spi_device_upload/latest

Test location	/workspace/coverage/default/38.spi_device_abort.4229848657
Short name	T481
Test name
Test status
Simulation time	79259075 ps
CPU time	0.74 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	206656 kb
Host	smart-2caf79a9-9869-415b-ae6a-c9948ef4eef0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229848657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_abort.4229848657
Directory	/workspace/38.spi_device_abort/latest

Test location	/workspace/coverage/default/38.spi_device_alert_test.2454588033
Short name	T77
Test name
Test status
Simulation time	14252883 ps
CPU time	0.71 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:10 PM PST 24
Peak memory	206464 kb
Host	smart-ceb4fc0c-e2e9-46e5-982f-c8c71efbd429
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454588033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test. 2454588033
Directory	/workspace/38.spi_device_alert_test/latest

Test location	/workspace/coverage/default/38.spi_device_bit_transfer.3599075524
Short name	T1318
Test name
Test status
Simulation time	698103959 ps
CPU time	2.05 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:11 PM PST 24
Peak memory	216764 kb
Host	smart-c1df5f41-2305-4e6c-967b-ac9af8e98656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599075524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_bit_transfer.3599075524
Directory	/workspace/38.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/38.spi_device_byte_transfer.2075692764
Short name	T1233
Test name
Test status
Simulation time	81845357 ps
CPU time	2.09 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	216816 kb
Host	smart-f6680de3-4e5b-473d-9daa-2591ca1667a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075692764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_byte_transfer.2075692764
Directory	/workspace/38.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/38.spi_device_cfg_cmd.1674274537
Short name	T787
Test name
Test status
Simulation time	39809232 ps
CPU time	2.46 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	218884 kb
Host	smart-ac35f26d-f633-4a0b-bd8d-3a124f4bb47a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674274537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1674274537
Directory	/workspace/38.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/38.spi_device_csb_read.3856976116
Short name	T1352
Test name
Test status
Simulation time	35069721 ps
CPU time	0.78 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	207476 kb
Host	smart-f30da0bd-f89b-4d54-8ff4-c57cca223d7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856976116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3856976116
Directory	/workspace/38.spi_device_csb_read/latest

Test location	/workspace/coverage/default/38.spi_device_dummy_item_extra_dly.3050623591
Short name	T788
Test name
Test status
Simulation time	94084202711 ps
CPU time	233.48 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:27:56 PM PST 24
Peak memory	288756 kb
Host	smart-f02e6a38-d2cd-4c0e-b3dd-c3d22ba04244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050623591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_dummy_item_extra_dly.3050623591
Directory	/workspace/38.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/38.spi_device_extreme_fifo_size.1778550302
Short name	T639
Test name
Test status
Simulation time	73954611838 ps
CPU time	3480.69 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 02:22:04 PM PST 24
Peak memory	225092 kb
Host	smart-729b53e9-b474-4b41-83e8-068c9ada9545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778550302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_extreme_fifo_size.1778550302
Directory	/workspace/38.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/38.spi_device_fifo_full.2332342442
Short name	T501
Test name
Test status
Simulation time	193616673717 ps
CPU time	1725.59 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:52:46 PM PST 24
Peak memory	271508 kb
Host	smart-27becbbc-4353-4e1c-b196-53b3e815ed46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332342442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_full.2332342442
Directory	/workspace/38.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/38.spi_device_fifo_underflow_overflow.3510375346
Short name	T916
Test name
Test status
Simulation time	631361890800 ps
CPU time	263.46 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:28:26 PM PST 24
Peak memory	323420 kb
Host	smart-d94836ec-12fe-40e5-a668-7585a1c012e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510375346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_fifo_underflow_overf low.3510375346
Directory	/workspace/38.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/38.spi_device_flash_all.1061338246
Short name	T1655
Test name
Test status
Simulation time	18622087471 ps
CPU time	71.27 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	257888 kb
Host	smart-6fac828f-f5ea-4310-b479-4e589167cb6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061338246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1061338246
Directory	/workspace/38.spi_device_flash_all/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm.644172816
Short name	T319
Test name
Test status
Simulation time	101125206119 ps
CPU time	371.19 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:30:14 PM PST 24
Peak memory	254580 kb
Host	smart-c7934087-9f4e-423b-9558-a3dbf64d8322
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644172816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.644172816
Directory	/workspace/38.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.555312842
Short name	T1667
Test name
Test status
Simulation time	98208129948 ps
CPU time	193.19 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:27:27 PM PST 24
Peak memory	253388 kb
Host	smart-124f7b67-cb8d-49bf-b969-523eb4a7188e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555312842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle .555312842
Directory	/workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/38.spi_device_intercept.2802382840
Short name	T1716
Test name
Test status
Simulation time	430534226 ps
CPU time	3.63 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	218656 kb
Host	smart-f3931b3e-f5ba-4545-8b48-bf0b11407788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802382840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2802382840
Directory	/workspace/38.spi_device_intercept/latest

Test location	/workspace/coverage/default/38.spi_device_intr.3824994484
Short name	T183
Test name
Test status
Simulation time	5072422911 ps
CPU time	50.65 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:53 PM PST 24
Peak memory	239932 kb
Host	smart-d9904526-336a-43a9-b1cc-d0d286448d30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824994484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intr.3824994484
Directory	/workspace/38.spi_device_intr/latest

Test location	/workspace/coverage/default/38.spi_device_mailbox.2985222067
Short name	T608
Test name
Test status
Simulation time	924436451 ps
CPU time	10.42 seconds
Started	Jan 07 01:24:06 PM PST 24
Finished	Jan 07 01:24:19 PM PST 24
Peak memory	233092 kb
Host	smart-04946383-ae0a-4fdc-b09a-7aff7999013d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985222067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2985222067
Directory	/workspace/38.spi_device_mailbox/latest

Test location	/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1016000279
Short name	T1515
Test name
Test status
Simulation time	3754677483 ps
CPU time	12.26 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:22 PM PST 24
Peak memory	241472 kb
Host	smart-2e252717-afe5-40a7-8d5a-9c397caa0576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016000279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.1016000279
Directory	/workspace/38.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/38.spi_device_pass_cmd_filtering.3396469231
Short name	T1308
Test name
Test status
Simulation time	398030574 ps
CPU time	4.25 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	225008 kb
Host	smart-3b8cdce0-36b4-4295-aa99-e30e667fc7ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396469231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3396469231
Directory	/workspace/38.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/38.spi_device_perf.2782644283
Short name	T1012
Test name
Test status
Simulation time	72952253800 ps
CPU time	2375.28 seconds
Started	Jan 07 01:23:59 PM PST 24
Finished	Jan 07 02:03:40 PM PST 24
Peak memory	289668 kb
Host	smart-78eb3a9c-78e2-4350-9907-d64fe53c86ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782644283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_perf.2782644283
Directory	/workspace/38.spi_device_perf/latest

Test location	/workspace/coverage/default/38.spi_device_read_buffer_direct.361753569
Short name	T1028
Test name
Test status
Simulation time	1073980159 ps
CPU time	4.14 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	218824 kb
Host	smart-3921b7fd-72b2-49ac-a2b2-09ba2c6727ca
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=361753569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire ct.361753569
Directory	/workspace/38.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/38.spi_device_rx_async_fifo_reset.1354597396
Short name	T1084
Test name
Test status
Simulation time	93562198 ps
CPU time	0.97 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:14 PM PST 24
Peak memory	208456 kb
Host	smart-1b06211e-2fe5-4b56-b8e4-f4349ab901ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354597396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_async_fifo_reset.1354597396
Directory	/workspace/38.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/38.spi_device_rx_timeout.1788085851
Short name	T1383
Test name
Test status
Simulation time	3872683560 ps
CPU time	5.64 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:07 PM PST 24
Peak memory	216812 kb
Host	smart-accf0aec-491f-43fd-ae3f-d9837c435957
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788085851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_rx_timeout.1788085851
Directory	/workspace/38.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/38.spi_device_smoke.1169208220
Short name	T430
Test name
Test status
Simulation time	109347261 ps
CPU time	0.94 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:59 PM PST 24
Peak memory	207860 kb
Host	smart-38f80c23-88f5-4f55-98ba-54bb7c98269c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169208220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_smoke.1169208220
Directory	/workspace/38.spi_device_smoke/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_all.3693024993
Short name	T869
Test name
Test status
Simulation time	2346046834 ps
CPU time	3.62 seconds
Started	Jan 07 01:23:58 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	216948 kb
Host	smart-3736e1f6-77c4-4f21-95a4-d93c5476bb90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693024993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3693024993
Directory	/workspace/38.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2730768402
Short name	T1598
Test name
Test status
Simulation time	2787481651 ps
CPU time	11.24 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:12 PM PST 24
Peak memory	216948 kb
Host	smart-33b3f3ab-6be4-4bbb-a5a5-d9cb2667978c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730768402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2730768402
Directory	/workspace/38.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_rw.3151852556
Short name	T1686
Test name
Test status
Simulation time	110682142 ps
CPU time	1.45 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:11 PM PST 24
Peak memory	208552 kb
Host	smart-79f0ebd6-3d2a-4b50-a369-e32c896eb5e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151852556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3151852556
Directory	/workspace/38.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_sts_read.1188320941
Short name	T1634
Test name
Test status
Simulation time	565770352 ps
CPU time	1.07 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:04 PM PST 24
Peak memory	207996 kb
Host	smart-9ac9363e-706d-4689-9967-242e849dde04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188320941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1188320941
Directory	/workspace/38.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/38.spi_device_tx_async_fifo_reset.2774680480
Short name	T1510
Test name
Test status
Simulation time	18725517 ps
CPU time	0.81 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:03 PM PST 24
Peak memory	208468 kb
Host	smart-9fa3fd4c-8a24-4b4f-861a-214f6c07f131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774680480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tx_async_fifo_reset.2774680480
Directory	/workspace/38.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/38.spi_device_txrx.980969403
Short name	T1612
Test name
Test status
Simulation time	54565624659 ps
CPU time	176.52 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:26:50 PM PST 24
Peak memory	262008 kb
Host	smart-a2836cee-d93f-4c6d-a721-8381f998651c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980969403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_txrx.980969403
Directory	/workspace/38.spi_device_txrx/latest

Test location	/workspace/coverage/default/38.spi_device_upload.4085084852
Short name	T22
Test name
Test status
Simulation time	9632061715 ps
CPU time	4.22 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	241396 kb
Host	smart-9a787f57-7285-4348-9c2e-46f15f74964f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085084852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4085084852
Directory	/workspace/38.spi_device_upload/latest

Test location	/workspace/coverage/default/39.spi_device_abort.4131764964
Short name	T911
Test name
Test status
Simulation time	175246077 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	206608 kb
Host	smart-4d4d45a3-ed37-469d-ab8d-93e27139645f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131764964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_abort.4131764964
Directory	/workspace/39.spi_device_abort/latest

Test location	/workspace/coverage/default/39.spi_device_alert_test.2373011307
Short name	T1456
Test name
Test status
Simulation time	93699926 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:03 PM PST 24
Peak memory	206388 kb
Host	smart-d0070969-0a5b-41b6-951b-9c49e67d11ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373011307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test. 2373011307
Directory	/workspace/39.spi_device_alert_test/latest

Test location	/workspace/coverage/default/39.spi_device_bit_transfer.2630177626
Short name	T1624
Test name
Test status
Simulation time	74821959 ps
CPU time	1.9 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	216804 kb
Host	smart-0c610173-2728-4742-a012-e11f16e3641e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630177626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_bit_transfer.2630177626
Directory	/workspace/39.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/39.spi_device_byte_transfer.1469303730
Short name	T508
Test name
Test status
Simulation time	217643953 ps
CPU time	3.34 seconds
Started	Jan 07 01:23:49 PM PST 24
Finished	Jan 07 01:23:54 PM PST 24
Peak memory	216712 kb
Host	smart-75add2ee-8e96-4081-bc6e-12ace5c8f3fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469303730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_byte_transfer.1469303730
Directory	/workspace/39.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/39.spi_device_cfg_cmd.1749069054
Short name	T1604
Test name
Test status
Simulation time	18766576746 ps
CPU time	15.45 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	222016 kb
Host	smart-6feac774-4a38-4929-95e1-170c9becc973
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749069054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1749069054
Directory	/workspace/39.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/39.spi_device_csb_read.4039821120
Short name	T473
Test name
Test status
Simulation time	19310382 ps
CPU time	0.81 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:03 PM PST 24
Peak memory	207640 kb
Host	smart-78a0c4e7-6de2-4ce1-8cd8-7c03e4ab1aca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039821120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4039821120
Directory	/workspace/39.spi_device_csb_read/latest

Test location	/workspace/coverage/default/39.spi_device_dummy_item_extra_dly.1368734347
Short name	T198
Test name
Test status
Simulation time	110780703059 ps
CPU time	2403.22 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 02:03:58 PM PST 24
Peak memory	282324 kb
Host	smart-a2a1cd00-da82-4c82-a9ce-18700a3d78cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368734347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_dummy_item_extra_dly.1368734347
Directory	/workspace/39.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/39.spi_device_extreme_fifo_size.1564589712
Short name	T1418
Test name
Test status
Simulation time	22468064969 ps
CPU time	40.12 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:38 PM PST 24
Peak memory	232680 kb
Host	smart-9d957526-3780-425e-b749-eab84d25597d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564589712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_extreme_fifo_size.1564589712
Directory	/workspace/39.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/39.spi_device_fifo_full.2945379819
Short name	T1439
Test name
Test status
Simulation time	185768884850 ps
CPU time	856.07 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:39:12 PM PST 24
Peak memory	292972 kb
Host	smart-b79c778d-260b-46af-b5f2-dd92b915c4de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945379819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_full.2945379819
Directory	/workspace/39.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/39.spi_device_fifo_underflow_overflow.3556497370
Short name	T1274
Test name
Test status
Simulation time	6127421120 ps
CPU time	110.44 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:25:49 PM PST 24
Peak memory	298964 kb
Host	smart-bfe04d77-4e17-4b51-b3b5-f93317aa46af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3556497370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_fifo_underflow_overf low.3556497370
Directory	/workspace/39.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/39.spi_device_flash_all.3862821821
Short name	T323
Test name
Test status
Simulation time	172773335189 ps
CPU time	411.34 seconds
Started	Jan 07 01:23:59 PM PST 24
Finished	Jan 07 01:30:56 PM PST 24
Peak memory	271032 kb
Host	smart-a6c8f8be-0fc6-48f6-bee4-ecd0aa2f51c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862821821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3862821821
Directory	/workspace/39.spi_device_flash_all/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm.289935166
Short name	T1593
Test name
Test status
Simulation time	28029103732 ps
CPU time	59.26 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	249664 kb
Host	smart-1d1246d6-c298-482b-9f2a-66d3505660a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289935166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.289935166
Directory	/workspace/39.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.289037948
Short name	T207
Test name
Test status
Simulation time	10676378232 ps
CPU time	70.13 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	240096 kb
Host	smart-e9c6f5f8-40dc-4ee4-9b41-e9abb120f863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289037948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle .289037948
Directory	/workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/39.spi_device_flash_mode.1876737781
Short name	T1594
Test name
Test status
Simulation time	4261637076 ps
CPU time	31.52 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:24:29 PM PST 24
Peak memory	241244 kb
Host	smart-29a2eda1-6c48-4946-b01e-5f389df284b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876737781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1876737781
Directory	/workspace/39.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/39.spi_device_intercept.2776228358
Short name	T942
Test name
Test status
Simulation time	621675316 ps
CPU time	5.89 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	218628 kb
Host	smart-20396072-7f2d-4d14-a99c-f502112eb776
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776228358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2776228358
Directory	/workspace/39.spi_device_intercept/latest

Test location	/workspace/coverage/default/39.spi_device_intr.3648423906
Short name	T163
Test name
Test status
Simulation time	3061971378 ps
CPU time	13.59 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	217948 kb
Host	smart-1e314b71-78dd-46dc-82c4-df657c474df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648423906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intr.3648423906
Directory	/workspace/39.spi_device_intr/latest

Test location	/workspace/coverage/default/39.spi_device_mailbox.4118982279
Short name	T1071
Test name
Test status
Simulation time	26792006667 ps
CPU time	27.07 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:24:29 PM PST 24
Peak memory	235840 kb
Host	smart-a79b10dd-94f9-47af-8f38-8db5dc436584
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118982279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4118982279
Directory	/workspace/39.spi_device_mailbox/latest

Test location	/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2794654034
Short name	T1735
Test name
Test status
Simulation time	2337019864 ps
CPU time	9.05 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:08 PM PST 24
Peak memory	239560 kb
Host	smart-6572d161-a7cc-4927-a1cb-ca3db4276cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794654034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa p.2794654034
Directory	/workspace/39.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/39.spi_device_pass_cmd_filtering.1867931636
Short name	T267
Test name
Test status
Simulation time	566173007 ps
CPU time	2.89 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:02 PM PST 24
Peak memory	218436 kb
Host	smart-d0bf2243-f343-489d-bcff-85fac27cbbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867931636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1867931636
Directory	/workspace/39.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/39.spi_device_perf.4016095853
Short name	T792
Test name
Test status
Simulation time	102200827875 ps
CPU time	667.81 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:35:03 PM PST 24
Peak memory	265996 kb
Host	smart-bf4e8a95-b6c1-4826-a334-88875f01985f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016095853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_perf.4016095853
Directory	/workspace/39.spi_device_perf/latest

Test location	/workspace/coverage/default/39.spi_device_read_buffer_direct.311626396
Short name	T1302
Test name
Test status
Simulation time	456349702 ps
CPU time	4.16 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:05 PM PST 24
Peak memory	221240 kb
Host	smart-904f1861-282e-4ca7-876c-0be76e1975aa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=311626396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire ct.311626396
Directory	/workspace/39.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/39.spi_device_rx_async_fifo_reset.4147225643
Short name	T1473
Test name
Test status
Simulation time	64500780 ps
CPU time	0.91 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	208428 kb
Host	smart-db15e303-a753-4eb0-9863-e47da9d67698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147225643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_async_fifo_reset.4147225643
Directory	/workspace/39.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/39.spi_device_rx_timeout.70457860
Short name	T109
Test name
Test status
Simulation time	4809617369 ps
CPU time	5.57 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:06 PM PST 24
Peak memory	216872 kb
Host	smart-14b0a961-8b5d-4990-b0fb-58f9a565e4f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70457860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_rx_timeout.70457860
Directory	/workspace/39.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/39.spi_device_smoke.2962204151
Short name	T582
Test name
Test status
Simulation time	48916757 ps
CPU time	1.13 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	216604 kb
Host	smart-308702b4-fc6e-4bf9-ad78-5f4d93802331
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962204151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_smoke.2962204151
Directory	/workspace/39.spi_device_smoke/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_all.788826438
Short name	T1225
Test name
Test status
Simulation time	15263218180 ps
CPU time	61.06 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:25:00 PM PST 24
Peak memory	216840 kb
Host	smart-f2fd9c52-1fc0-4d1b-8fdf-6347d6ee3d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788826438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.788826438
Directory	/workspace/39.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2573543306
Short name	T1581
Test name
Test status
Simulation time	824391497 ps
CPU time	2.7 seconds
Started	Jan 07 01:23:51 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	216664 kb
Host	smart-b54d2580-6e86-4636-a7aa-d1921ea360f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573543306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2573543306
Directory	/workspace/39.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_rw.673470444
Short name	T348
Test name
Test status
Simulation time	76643500 ps
CPU time	1.43 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:24:00 PM PST 24
Peak memory	217020 kb
Host	smart-19f774cf-1d5c-4824-9779-63e711fff770
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673470444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.673470444
Directory	/workspace/39.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_sts_read.1915991490
Short name	T1053
Test name
Test status
Simulation time	326005144 ps
CPU time	0.95 seconds
Started	Jan 07 01:23:52 PM PST 24
Finished	Jan 07 01:23:57 PM PST 24
Peak memory	207968 kb
Host	smart-d040160d-757f-4a1c-b89c-7e7bc557e7d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915991490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1915991490
Directory	/workspace/39.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/39.spi_device_tx_async_fifo_reset.1894677092
Short name	T995
Test name
Test status
Simulation time	84464237 ps
CPU time	0.75 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:01 PM PST 24
Peak memory	208440 kb
Host	smart-b7d95c76-32a4-489e-baba-e21d2a55a27b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894677092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tx_async_fifo_reset.1894677092
Directory	/workspace/39.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/39.spi_device_txrx.3565376082
Short name	T1665
Test name
Test status
Simulation time	64254327653 ps
CPU time	355.77 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:30:10 PM PST 24
Peak memory	251956 kb
Host	smart-5affeddb-854e-4ae2-84e6-671ef177dde0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565376082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_txrx.3565376082
Directory	/workspace/39.spi_device_txrx/latest

Test location	/workspace/coverage/default/39.spi_device_upload.3013918835
Short name	T1564
Test name
Test status
Simulation time	227563009 ps
CPU time	3.28 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:24:06 PM PST 24
Peak memory	219428 kb
Host	smart-89c5ae7e-0bdd-434f-b008-45307f217e22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013918835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3013918835
Directory	/workspace/39.spi_device_upload/latest

Test location	/workspace/coverage/default/4.spi_device_abort.1181978862
Short name	T518
Test name
Test status
Simulation time	223200692 ps
CPU time	0.74 seconds
Started	Jan 07 01:19:09 PM PST 24
Finished	Jan 07 01:19:12 PM PST 24
Peak memory	206604 kb
Host	smart-b1bf8323-41a1-4e16-8821-c4b2d637033f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181978862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_abort.1181978862
Directory	/workspace/4.spi_device_abort/latest

Test location	/workspace/coverage/default/4.spi_device_alert_test.3685076238
Short name	T670
Test name
Test status
Simulation time	71911087 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:10 PM PST 24
Finished	Jan 07 01:19:12 PM PST 24
Peak memory	206492 kb
Host	smart-f42f6097-1d6d-4f51-ae9b-4c1f0539debf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685076238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3 685076238
Directory	/workspace/4.spi_device_alert_test/latest

Test location	/workspace/coverage/default/4.spi_device_bit_transfer.79538740
Short name	T836
Test name
Test status
Simulation time	106796001 ps
CPU time	2.47 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:19:39 PM PST 24
Peak memory	216884 kb
Host	smart-365e20ba-d771-4690-a39b-0d6052822b95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79538740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_bit_transfer.79538740
Directory	/workspace/4.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/4.spi_device_byte_transfer.2150445113
Short name	T1474
Test name
Test status
Simulation time	308862676 ps
CPU time	2.02 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:30 PM PST 24
Peak memory	216780 kb
Host	smart-c5b15a7a-9874-429d-a36b-797ebb04b7cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150445113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_byte_transfer.2150445113
Directory	/workspace/4.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/4.spi_device_cfg_cmd.609559370
Short name	T612
Test name
Test status
Simulation time	304559038 ps
CPU time	4.15 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:32 PM PST 24
Peak memory	225160 kb
Host	smart-30a1192d-8c3e-436a-abde-d4aa31031854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609559370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.609559370
Directory	/workspace/4.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/4.spi_device_csb_read.745836235
Short name	T1173
Test name
Test status
Simulation time	57023947 ps
CPU time	0.78 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	207556 kb
Host	smart-70523dfd-2f9d-417d-a66b-bf6cee4ebf58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745836235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.745836235
Directory	/workspace/4.spi_device_csb_read/latest

Test location	/workspace/coverage/default/4.spi_device_dummy_item_extra_dly.927113515
Short name	T1443
Test name
Test status
Simulation time	87725558082 ps
CPU time	200.89 seconds
Started	Jan 07 01:19:09 PM PST 24
Finished	Jan 07 01:22:32 PM PST 24
Peak memory	304720 kb
Host	smart-c62789fe-78c0-4fc2-ab28-608fb785c101
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927113515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_dummy_item_extra_dly.927113515
Directory	/workspace/4.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/4.spi_device_fifo_full.3564448690
Short name	T1022
Test name
Test status
Simulation time	35645605359 ps
CPU time	343.28 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	304168 kb
Host	smart-4a5da172-36ee-4648-9121-9b965985bd02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564448690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_full.3564448690
Directory	/workspace/4.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/4.spi_device_fifo_underflow_overflow.2207132425
Short name	T1226
Test name
Test status
Simulation time	757213856732 ps
CPU time	844.34 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:33:29 PM PST 24
Peak memory	700420 kb
Host	smart-c4c4a62a-6978-43b4-914b-86c768ce3aa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207132425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_fifo_underflow_overfl ow.2207132425
Directory	/workspace/4.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/4.spi_device_flash_all.3021421376
Short name	T851
Test name
Test status
Simulation time	241778709773 ps
CPU time	161.42 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:22:09 PM PST 24
Peak memory	268804 kb
Host	smart-c2c4ab60-5370-4f90-8ac8-d163c0b30979
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021421376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3021421376
Directory	/workspace/4.spi_device_flash_all/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm.3592762679
Short name	T852
Test name
Test status
Simulation time	87419804569 ps
CPU time	175.34 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:22:23 PM PST 24
Peak memory	250784 kb
Host	smart-6ebe00e9-f6eb-446c-9499-dd2d8922bb66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592762679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3592762679
Directory	/workspace/4.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2722314505
Short name	T187
Test name
Test status
Simulation time	51258373493 ps
CPU time	351.56 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:25:45 PM PST 24
Peak memory	256212 kb
Host	smart-93d2ec1f-4656-4375-a930-c5c942cfc8a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722314505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle .2722314505
Directory	/workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/4.spi_device_intercept.3023375679
Short name	T1057
Test name
Test status
Simulation time	4319834849 ps
CPU time	9.82 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	225148 kb
Host	smart-c915577e-97c3-483d-8b54-ee8f19786a77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023375679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3023375679
Directory	/workspace/4.spi_device_intercept/latest

Test location	/workspace/coverage/default/4.spi_device_intr.1461479840
Short name	T62
Test name
Test status
Simulation time	10577320253 ps
CPU time	19.36 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:20:10 PM PST 24
Peak memory	217972 kb
Host	smart-9cd3e1c2-33bc-4f2e-b0ed-10688b66127a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461479840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intr.1461479840
Directory	/workspace/4.spi_device_intr/latest

Test location	/workspace/coverage/default/4.spi_device_mailbox.1696831415
Short name	T302
Test name
Test status
Simulation time	1944282983 ps
CPU time	14.26 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	228844 kb
Host	smart-64330148-8a62-4ff3-8c31-7bc0500fca36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696831415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1696831415
Directory	/workspace/4.spi_device_mailbox/latest

Test location	/workspace/coverage/default/4.spi_device_mem_parity.1330580861
Short name	T1354
Test name
Test status
Simulation time	91407603 ps
CPU time	1.09 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:15 PM PST 24
Peak memory	218864 kb
Host	smart-744d651d-c1e6-4f98-bac8-46b2270ad9bc
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330580861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.spi_device_mem_parity.1330580861
Directory	/workspace/4.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2805560241
Short name	T1732
Test name
Test status
Simulation time	2528694977 ps
CPU time	8.74 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:19:50 PM PST 24
Peak memory	239244 kb
Host	smart-4e697009-fbe3-4c17-87d5-15bf488036b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805560241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap .2805560241
Directory	/workspace/4.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/4.spi_device_pass_cmd_filtering.157253513
Short name	T1520
Test name
Test status
Simulation time	6579120041 ps
CPU time	9.03 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:19:50 PM PST 24
Peak memory	238404 kb
Host	smart-7979bbd9-15bf-4562-80f0-c7bb11504aed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157253513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.157253513
Directory	/workspace/4.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_perf.2227102281
Short name	T642
Test name
Test status
Simulation time	22454043555 ps
CPU time	875.05 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:34:03 PM PST 24
Peak memory	273868 kb
Host	smart-15d029a3-24a7-4db1-96ca-f2523b11bac1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227102281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_perf.2227102281
Directory	/workspace/4.spi_device_perf/latest

Test location	/workspace/coverage/default/4.spi_device_ram_cfg.2880623362
Short name	T1597
Test name
Test status
Simulation time	28119911 ps
CPU time	0.73 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:19:17 PM PST 24
Peak memory	216696 kb
Host	smart-326f04e9-7c07-4de6-8730-831914a2d7a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880623362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2880623362
Directory	/workspace/4.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/4.spi_device_read_buffer_direct.2198396587
Short name	T1064
Test name
Test status
Simulation time	4990151973 ps
CPU time	7.46 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:22 PM PST 24
Peak memory	237128 kb
Host	smart-5c4cd7c0-1a3f-4d25-a694-43b0ac3f5a03
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2198396587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.2198396587
Directory	/workspace/4.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/4.spi_device_rx_async_fifo_reset.3057904940
Short name	T1112
Test name
Test status
Simulation time	43938397 ps
CPU time	0.94 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:53 PM PST 24
Peak memory	208456 kb
Host	smart-aad43b9c-78f8-4c44-9f10-13f727f235f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057904940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_async_fifo_reset.3057904940
Directory	/workspace/4.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/4.spi_device_rx_timeout.4169475597
Short name	T1438
Test name
Test status
Simulation time	2566201647 ps
CPU time	5.29 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:19:30 PM PST 24
Peak memory	216904 kb
Host	smart-8d2277b3-cec8-47a4-955f-a6ee99dc252c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169475597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_rx_timeout.4169475597
Directory	/workspace/4.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/4.spi_device_sec_cm.1827780173
Short name	T90
Test name
Test status
Simulation time	258949967 ps
CPU time	1.07 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	238168 kb
Host	smart-f454597f-4457-46ba-8bd3-bfe8ea12620b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827780173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1827780173
Directory	/workspace/4.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/4.spi_device_smoke.2777193069
Short name	T1180
Test name
Test status
Simulation time	58204060 ps
CPU time	1.13 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	216424 kb
Host	smart-9ea9ce50-cccf-4a5a-8eeb-775a42010f34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777193069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_smoke.2777193069
Directory	/workspace/4.spi_device_smoke/latest

Test location	/workspace/coverage/default/4.spi_device_stress_all.3769411619
Short name	T126
Test name
Test status
Simulation time	74908554899 ps
CPU time	1186.43 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:39:15 PM PST 24
Peak memory	342840 kb
Host	smart-b4c71ff2-4508-4090-af96-8017f5c2d88a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769411619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres s_all.3769411619
Directory	/workspace/4.spi_device_stress_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_all.1020559509
Short name	T845
Test name
Test status
Simulation time	2517267901 ps
CPU time	19.27 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:19:36 PM PST 24
Peak memory	217188 kb
Host	smart-f514cd28-e7bd-40c7-bce0-94a4c55d5d7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020559509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1020559509
Directory	/workspace/4.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3085455630
Short name	T1304
Test name
Test status
Simulation time	1701171663 ps
CPU time	3.63 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:47 PM PST 24
Peak memory	216808 kb
Host	smart-38008646-7ba5-43fa-b5d8-79c7344ab8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085455630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3085455630
Directory	/workspace/4.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_rw.2281392031
Short name	T988
Test name
Test status
Simulation time	119874954 ps
CPU time	1.01 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	208176 kb
Host	smart-4cca998e-6b1d-480f-b46b-1a3707e1ca12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281392031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2281392031
Directory	/workspace/4.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_sts_read.2316706052
Short name	T770
Test name
Test status
Simulation time	20599680 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206820 kb
Host	smart-43d7facb-4472-4e4b-901c-f327bee64629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2316706052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2316706052
Directory	/workspace/4.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/4.spi_device_tx_async_fifo_reset.2414368501
Short name	T923
Test name
Test status
Simulation time	51744584 ps
CPU time	0.78 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	208444 kb
Host	smart-0d4e9890-ac8f-4c55-94f1-e59111f5765c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2414368501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tx_async_fifo_reset.2414368501
Directory	/workspace/4.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/4.spi_device_txrx.2161946669
Short name	T1020
Test name
Test status
Simulation time	23175445123 ps
CPU time	234.59 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:23:07 PM PST 24
Peak memory	256996 kb
Host	smart-dde3f6a1-c2dd-4da5-b55d-eabb768d1e35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161946669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_txrx.2161946669
Directory	/workspace/4.spi_device_txrx/latest

Test location	/workspace/coverage/default/4.spi_device_upload.3309858268
Short name	T1307
Test name
Test status
Simulation time	2945738974 ps
CPU time	10.35 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:59 PM PST 24
Peak memory	218988 kb
Host	smart-f3672d4b-63b0-41d3-96b0-fa53fd1bf90d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309858268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3309858268
Directory	/workspace/4.spi_device_upload/latest

Test location	/workspace/coverage/default/40.spi_device_abort.1248354455
Short name	T1135
Test name
Test status
Simulation time	25557785 ps
CPU time	0.75 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:24:15 PM PST 24
Peak memory	206584 kb
Host	smart-07d5cf1a-e083-445e-8cdc-37c59fe08ff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248354455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_abort.1248354455
Directory	/workspace/40.spi_device_abort/latest

Test location	/workspace/coverage/default/40.spi_device_alert_test.2271865198
Short name	T503
Test name
Test status
Simulation time	43293241 ps
CPU time	0.69 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	206468 kb
Host	smart-21365da1-0237-4945-88b0-f64a0b0f58e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271865198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test. 2271865198
Directory	/workspace/40.spi_device_alert_test/latest

Test location	/workspace/coverage/default/40.spi_device_bit_transfer.793787860
Short name	T1477
Test name
Test status
Simulation time	358715261 ps
CPU time	2.99 seconds
Started	Jan 07 01:24:26 PM PST 24
Finished	Jan 07 01:24:52 PM PST 24
Peak memory	216828 kb
Host	smart-08606bf4-a7ab-4c8b-b00f-5ea00cebc9fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793787860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_bit_transfer.793787860
Directory	/workspace/40.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/40.spi_device_byte_transfer.891597360
Short name	T1441
Test name
Test status
Simulation time	269017838 ps
CPU time	2.75 seconds
Started	Jan 07 01:24:06 PM PST 24
Finished	Jan 07 01:24:11 PM PST 24
Peak memory	216816 kb
Host	smart-c4b9c5b3-fa62-4b85-8cbf-43fe391ede7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891597360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_byte_transfer.891597360
Directory	/workspace/40.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/40.spi_device_cfg_cmd.3719665210
Short name	T299
Test name
Test status
Simulation time	357976994 ps
CPU time	3.37 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	219672 kb
Host	smart-0c4e6e5c-1698-44cc-acc4-039d41a72971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719665210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3719665210
Directory	/workspace/40.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/40.spi_device_csb_read.3553507392
Short name	T499
Test name
Test status
Simulation time	40877480 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:11 PM PST 24
Peak memory	206396 kb
Host	smart-0199aeb8-3859-4fab-a59a-8856102b9ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553507392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3553507392
Directory	/workspace/40.spi_device_csb_read/latest

Test location	/workspace/coverage/default/40.spi_device_dummy_item_extra_dly.949952638
Short name	T1586
Test name
Test status
Simulation time	78978788084 ps
CPU time	1747.66 seconds
Started	Jan 07 01:23:55 PM PST 24
Finished	Jan 07 01:53:10 PM PST 24
Peak memory	257376 kb
Host	smart-867fc230-1c2d-4268-bd20-21b9c20d40c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949952638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_dummy_item_extra_dly.949952638
Directory	/workspace/40.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/40.spi_device_extreme_fifo_size.2088834209
Short name	T261
Test name
Test status
Simulation time	119713127232 ps
CPU time	841.88 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:38:15 PM PST 24
Peak memory	225140 kb
Host	smart-6dabc3cb-05ab-4c31-90b0-1302f7d25888
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088834209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_extreme_fifo_size.2088834209
Directory	/workspace/40.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/40.spi_device_fifo_full.2777322783
Short name	T1254
Test name
Test status
Simulation time	83763864725 ps
CPU time	446.38 seconds
Started	Jan 07 01:23:57 PM PST 24
Finished	Jan 07 01:31:30 PM PST 24
Peak memory	275852 kb
Host	smart-9dbe9fd8-ff78-4a9f-92a0-517eb48f7c11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777322783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_full.2777322783
Directory	/workspace/40.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/40.spi_device_fifo_underflow_overflow.4271995899
Short name	T1157
Test name
Test status
Simulation time	201973124335 ps
CPU time	419.65 seconds
Started	Jan 07 01:23:53 PM PST 24
Finished	Jan 07 01:31:00 PM PST 24
Peak memory	374776 kb
Host	smart-05bd7752-a2cd-48fa-8fe5-0eddff6699ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271995899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_fifo_underflow_overf low.4271995899
Directory	/workspace/40.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/40.spi_device_flash_all.2796525773
Short name	T1283
Test name
Test status
Simulation time	1119501948 ps
CPU time	7.69 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:19 PM PST 24
Peak memory	219168 kb
Host	smart-3196ffaa-b16d-4b59-97c7-f25a67f9054d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796525773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2796525773
Directory	/workspace/40.spi_device_flash_all/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm.3708267422
Short name	T104
Test name
Test status
Simulation time	38207352547 ps
CPU time	98.93 seconds
Started	Jan 07 01:24:41 PM PST 24
Finished	Jan 07 01:26:35 PM PST 24
Peak memory	241204 kb
Host	smart-af6dfff2-f03b-4e4a-8fa6-15e1ec160bab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708267422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3708267422
Directory	/workspace/40.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2291792216
Short name	T1353
Test name
Test status
Simulation time	18563799406 ps
CPU time	138.99 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:26:29 PM PST 24
Peak memory	257968 kb
Host	smart-14d15343-3793-420e-a351-4f9cb98da5cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291792216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl e.2291792216
Directory	/workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/40.spi_device_flash_mode.2562524112
Short name	T1055
Test name
Test status
Simulation time	905441757 ps
CPU time	14.02 seconds
Started	Jan 07 01:24:41 PM PST 24
Finished	Jan 07 01:25:10 PM PST 24
Peak memory	241476 kb
Host	smart-4384fe5f-7fc1-48c1-abfa-314690b29f2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562524112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2562524112
Directory	/workspace/40.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/40.spi_device_intercept.1454938939
Short name	T1672
Test name
Test status
Simulation time	11085739228 ps
CPU time	9.64 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:20 PM PST 24
Peak memory	219576 kb
Host	smart-d17a238d-14a4-43a8-9cc8-979ed8dd1369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454938939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1454938939
Directory	/workspace/40.spi_device_intercept/latest

Test location	/workspace/coverage/default/40.spi_device_intr.3182238107
Short name	T1232
Test name
Test status
Simulation time	26876805764 ps
CPU time	67.5 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:26:04 PM PST 24
Peak memory	231880 kb
Host	smart-ed47cbb2-829b-4be1-9653-9e13d3f0a8ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182238107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intr.3182238107
Directory	/workspace/40.spi_device_intr/latest

Test location	/workspace/coverage/default/40.spi_device_mailbox.1090655496
Short name	T1442
Test name
Test status
Simulation time	52781263956 ps
CPU time	37.64 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:50 PM PST 24
Peak memory	241404 kb
Host	smart-fbf8d685-052a-43b4-a20b-e3c793674b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090655496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1090655496
Directory	/workspace/40.spi_device_mailbox/latest

Test location	/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2823855323
Short name	T296
Test name
Test status
Simulation time	96151023 ps
CPU time	3.35 seconds
Started	Jan 07 01:24:25 PM PST 24
Finished	Jan 07 01:24:52 PM PST 24
Peak memory	239236 kb
Host	smart-5b638734-cb3a-4fd4-b01d-cb3a184a44e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823855323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa p.2823855323
Directory	/workspace/40.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/40.spi_device_pass_cmd_filtering.1859728625
Short name	T224
Test name
Test status
Simulation time	1053652095 ps
CPU time	3.68 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	218720 kb
Host	smart-9b331936-a202-48f0-899c-46b954e31c8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859728625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1859728625
Directory	/workspace/40.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/40.spi_device_perf.1632799314
Short name	T1625
Test name
Test status
Simulation time	81013267996 ps
CPU time	1088.37 seconds
Started	Jan 07 01:24:12 PM PST 24
Finished	Jan 07 01:42:27 PM PST 24
Peak memory	283732 kb
Host	smart-c639e62a-eb60-4219-bb01-999cbb949185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632799314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_perf.1632799314
Directory	/workspace/40.spi_device_perf/latest

Test location	/workspace/coverage/default/40.spi_device_read_buffer_direct.2854951905
Short name	T1122
Test name
Test status
Simulation time	1525531293 ps
CPU time	3.73 seconds
Started	Jan 07 01:24:28 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	218760 kb
Host	smart-a4303b6a-6ec6-4710-8b65-f49497a994bc
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2854951905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir ect.2854951905
Directory	/workspace/40.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/40.spi_device_rx_async_fifo_reset.2559166959
Short name	T1536
Test name
Test status
Simulation time	82260759 ps
CPU time	0.85 seconds
Started	Jan 07 01:24:40 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	208532 kb
Host	smart-b1f5a764-6a83-493e-94b3-42ef6c10d90e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559166959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_async_fifo_reset.2559166959
Directory	/workspace/40.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/40.spi_device_rx_timeout.2136082659
Short name	T775
Test name
Test status
Simulation time	961936220 ps
CPU time	6.66 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:17 PM PST 24
Peak memory	216780 kb
Host	smart-def332c9-0c1f-4054-abe6-d9e501ee28f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136082659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_rx_timeout.2136082659
Directory	/workspace/40.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/40.spi_device_smoke.798372980
Short name	T1460
Test name
Test status
Simulation time	50006618 ps
CPU time	1.27 seconds
Started	Jan 07 01:23:54 PM PST 24
Finished	Jan 07 01:24:02 PM PST 24
Peak memory	216892 kb
Host	smart-5b4c3586-0408-4e80-bfe6-804b926b33fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798372980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_smoke.798372980
Directory	/workspace/40.spi_device_smoke/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_all.2461416507
Short name	T823
Test name
Test status
Simulation time	3117747507 ps
CPU time	43.2 seconds
Started	Jan 07 01:24:07 PM PST 24
Finished	Jan 07 01:24:52 PM PST 24
Peak memory	216764 kb
Host	smart-49c0c3a4-a780-4d90-bebe-69c7eba3f498
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461416507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2461416507
Directory	/workspace/40.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.329679928
Short name	T498
Test name
Test status
Simulation time	1154701279 ps
CPU time	7.7 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:25:04 PM PST 24
Peak memory	216612 kb
Host	smart-82deaa2c-0bc2-4c51-b1f3-6b556dd681ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329679928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.329679928
Directory	/workspace/40.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_rw.2613375680
Short name	T1046
Test name
Test status
Simulation time	93531878 ps
CPU time	1.47 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	216740 kb
Host	smart-693dcb52-880a-4c42-b887-d1d58d5efad2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613375680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2613375680
Directory	/workspace/40.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_sts_read.3676736474
Short name	T496
Test name
Test status
Simulation time	112653473 ps
CPU time	0.76 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	206952 kb
Host	smart-42b87ced-c639-420c-a5b1-bc47cb208bbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676736474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3676736474
Directory	/workspace/40.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/40.spi_device_tx_async_fifo_reset.3178227523
Short name	T1240
Test name
Test status
Simulation time	51133088 ps
CPU time	0.76 seconds
Started	Jan 07 01:24:40 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	208440 kb
Host	smart-273c5c64-edaa-4bcd-be9d-c2f4f6429fea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178227523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tx_async_fifo_reset.3178227523
Directory	/workspace/40.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/40.spi_device_txrx.846504223
Short name	T839
Test name
Test status
Simulation time	5609583032 ps
CPU time	65.41 seconds
Started	Jan 07 01:23:56 PM PST 24
Finished	Jan 07 01:25:09 PM PST 24
Peak memory	249084 kb
Host	smart-403e190e-27c1-4035-bbde-24f448d6d958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846504223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_txrx.846504223
Directory	/workspace/40.spi_device_txrx/latest

Test location	/workspace/coverage/default/40.spi_device_upload.2551230378
Short name	T581
Test name
Test status
Simulation time	32762761481 ps
CPU time	15.96 seconds
Started	Jan 07 01:24:27 PM PST 24
Finished	Jan 07 01:25:07 PM PST 24
Peak memory	220048 kb
Host	smart-95c3fc9a-0d4b-4ef8-bca4-61da287c01ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551230378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2551230378
Directory	/workspace/40.spi_device_upload/latest

Test location	/workspace/coverage/default/41.spi_device_abort.2795565022
Short name	T478
Test name
Test status
Simulation time	38372983 ps
CPU time	0.73 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	206608 kb
Host	smart-ad974a03-9375-4b9c-bce2-a827ff6a1f97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795565022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_abort.2795565022
Directory	/workspace/41.spi_device_abort/latest

Test location	/workspace/coverage/default/41.spi_device_alert_test.925180632
Short name	T1342
Test name
Test status
Simulation time	15076050 ps
CPU time	0.7 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:14 PM PST 24
Peak memory	206476 kb
Host	smart-e45d8ddc-39f9-430a-9d93-62496bb3dc84
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925180632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.925180632
Directory	/workspace/41.spi_device_alert_test/latest

Test location	/workspace/coverage/default/41.spi_device_bit_transfer.874436610
Short name	T640
Test name
Test status
Simulation time	221874626 ps
CPU time	2.94 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	216756 kb
Host	smart-10f2f307-ebd9-40a6-bbfd-dd6183cb2090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874436610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_bit_transfer.874436610
Directory	/workspace/41.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/41.spi_device_byte_transfer.1201165656
Short name	T949
Test name
Test status
Simulation time	124697197 ps
CPU time	2.5 seconds
Started	Jan 07 01:24:22 PM PST 24
Finished	Jan 07 01:24:44 PM PST 24
Peak memory	216844 kb
Host	smart-2855f40f-4afb-47cc-ba50-5cd8a8ff5a78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201165656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_byte_transfer.1201165656
Directory	/workspace/41.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/41.spi_device_cfg_cmd.3379128929
Short name	T443
Test name
Test status
Simulation time	155532371 ps
CPU time	3.36 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:16 PM PST 24
Peak memory	218720 kb
Host	smart-e81e64c3-6d07-499b-86bd-e7d34bf366bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3379128929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3379128929
Directory	/workspace/41.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/41.spi_device_csb_read.2135008154
Short name	T572
Test name
Test status
Simulation time	17833998 ps
CPU time	0.77 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	207624 kb
Host	smart-7cc3e900-628a-4648-acf7-12ceb4dd1a7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135008154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2135008154
Directory	/workspace/41.spi_device_csb_read/latest

Test location	/workspace/coverage/default/41.spi_device_dummy_item_extra_dly.3251136690
Short name	T881
Test name
Test status
Simulation time	20297984361 ps
CPU time	142.08 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:27:21 PM PST 24
Peak memory	249832 kb
Host	smart-fefc1a64-7294-4003-9475-2d322097ad43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251136690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_dummy_item_extra_dly.3251136690
Directory	/workspace/41.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/41.spi_device_extreme_fifo_size.3851532138
Short name	T1575
Test name
Test status
Simulation time	640932454067 ps
CPU time	2084.42 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:59:44 PM PST 24
Peak memory	218292 kb
Host	smart-abc8b83d-986d-4c92-b6fe-f1e66e33471f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851532138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_extreme_fifo_size.3851532138
Directory	/workspace/41.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/41.spi_device_fifo_full.3225188208
Short name	T440
Test name
Test status
Simulation time	74088738875 ps
CPU time	406.22 seconds
Started	Jan 07 01:24:06 PM PST 24
Finished	Jan 07 01:30:55 PM PST 24
Peak memory	256408 kb
Host	smart-c03ef22d-df83-4c30-9518-e38cab414ee6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225188208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_full.3225188208
Directory	/workspace/41.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/41.spi_device_fifo_underflow_overflow.1671566120
Short name	T1738
Test name
Test status
Simulation time	33235577687 ps
CPU time	172 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:27:03 PM PST 24
Peak memory	354420 kb
Host	smart-cbabdbc9-3319-49b9-81ee-2af8a7d526eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671566120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_fifo_underflow_overf low.1671566120
Directory	/workspace/41.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/41.spi_device_flash_all.1311145885
Short name	T193
Test name
Test status
Simulation time	20975860273 ps
CPU time	119.41 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:26:10 PM PST 24
Peak memory	256328 kb
Host	smart-0b03f154-b119-4c97-883c-fe1a13d45142
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311145885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1311145885
Directory	/workspace/41.spi_device_flash_all/latest

Test location	/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3130505710
Short name	T344
Test name
Test status
Simulation time	1968165161 ps
CPU time	21.84 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	222808 kb
Host	smart-6de07eab-69f4-48b9-816b-a92bc8b23d4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130505710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl e.3130505710
Directory	/workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/41.spi_device_intercept.337208957
Short name	T282
Test name
Test status
Simulation time	194604823 ps
CPU time	4.44 seconds
Started	Jan 07 01:24:11 PM PST 24
Finished	Jan 07 01:24:18 PM PST 24
Peak memory	240388 kb
Host	smart-20e8cffd-7fe7-4590-b86b-e6eaf46ddbb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337208957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.337208957
Directory	/workspace/41.spi_device_intercept/latest

Test location	/workspace/coverage/default/41.spi_device_intr.581573732
Short name	T1527
Test name
Test status
Simulation time	4322568519 ps
CPU time	8.04 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:21 PM PST 24
Peak memory	217056 kb
Host	smart-d2a5ea3f-8bc2-4e2b-b289-485a0a81a7eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581573732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intr.581573732
Directory	/workspace/41.spi_device_intr/latest

Test location	/workspace/coverage/default/41.spi_device_mailbox.387499330
Short name	T1631
Test name
Test status
Simulation time	9201792046 ps
CPU time	27.63 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:37 PM PST 24
Peak memory	233352 kb
Host	smart-5480ace6-0807-47f5-bd3a-10d605c860c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387499330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.387499330
Directory	/workspace/41.spi_device_mailbox/latest

Test location	/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3658145930
Short name	T1162
Test name
Test status
Simulation time	7044481792 ps
CPU time	20.78 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:34 PM PST 24
Peak memory	231204 kb
Host	smart-c880db41-9b3d-410a-9610-9f206b811c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658145930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa p.3658145930
Directory	/workspace/41.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/41.spi_device_pass_cmd_filtering.536317403
Short name	T281
Test name
Test status
Simulation time	6374152321 ps
CPU time	24.66 seconds
Started	Jan 07 01:24:41 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	239016 kb
Host	smart-2943cf81-04ad-4c31-a5d8-6a161df9ee1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536317403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.536317403
Directory	/workspace/41.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/41.spi_device_perf.650361694
Short name	T98
Test name
Test status
Simulation time	29119758603 ps
CPU time	634.59 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:34:47 PM PST 24
Peak memory	290200 kb
Host	smart-bbc792be-9c3f-4034-8a43-064ff87db36b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650361694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_perf.650361694
Directory	/workspace/41.spi_device_perf/latest

Test location	/workspace/coverage/default/41.spi_device_read_buffer_direct.2056963495
Short name	T1630
Test name
Test status
Simulation time	101773244 ps
CPU time	3.85 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:25:00 PM PST 24
Peak memory	234564 kb
Host	smart-f3a6e3dc-13d3-4bed-8166-db1c398c994d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2056963495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir ect.2056963495
Directory	/workspace/41.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/41.spi_device_rx_async_fifo_reset.2721345114
Short name	T1513
Test name
Test status
Simulation time	18331128 ps
CPU time	0.85 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:24:12 PM PST 24
Peak memory	208284 kb
Host	smart-da5d2e19-1766-4664-bd9b-3455d6ca174b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721345114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_async_fifo_reset.2721345114
Directory	/workspace/41.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/41.spi_device_rx_timeout.4017952456
Short name	T1359
Test name
Test status
Simulation time	2007434161 ps
CPU time	5.94 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	216840 kb
Host	smart-9ddc83bd-f2c8-43a1-a5b7-ad0fd841ee91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017952456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_rx_timeout.4017952456
Directory	/workspace/41.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/41.spi_device_smoke.2236585230
Short name	T590
Test name
Test status
Simulation time	47844667 ps
CPU time	1.07 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	208144 kb
Host	smart-8b449f1e-4098-4dc4-a815-2aa1aa9ef23b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236585230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_smoke.2236585230
Directory	/workspace/41.spi_device_smoke/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_all.3900976324
Short name	T855
Test name
Test status
Simulation time	6948566282 ps
CPU time	18.75 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:31 PM PST 24
Peak memory	216824 kb
Host	smart-a225141a-955b-419d-b768-5eb17738ca1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900976324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3900976324
Directory	/workspace/41.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.572578933
Short name	T583
Test name
Test status
Simulation time	3440226469 ps
CPU time	13.15 seconds
Started	Jan 07 01:24:10 PM PST 24
Finished	Jan 07 01:24:26 PM PST 24
Peak memory	216808 kb
Host	smart-24d34b82-40a3-40e1-9922-832545922e1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572578933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.572578933
Directory	/workspace/41.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_rw.1037307815
Short name	T60
Test name
Test status
Simulation time	228056911 ps
CPU time	2.45 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	216768 kb
Host	smart-fadc3b09-2319-4b06-a0d0-64d6e6673806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037307815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1037307815
Directory	/workspace/41.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_sts_read.2625061383
Short name	T1167
Test name
Test status
Simulation time	173581337 ps
CPU time	1.07 seconds
Started	Jan 07 01:24:25 PM PST 24
Finished	Jan 07 01:24:48 PM PST 24
Peak memory	206960 kb
Host	smart-9e0ce85f-7b84-4c20-8130-8d87c6f24881
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625061383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2625061383
Directory	/workspace/41.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/41.spi_device_tx_async_fifo_reset.1009059560
Short name	T951
Test name
Test status
Simulation time	41367093 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:09 PM PST 24
Finished	Jan 07 01:24:13 PM PST 24
Peak memory	208432 kb
Host	smart-672b193b-80d9-4c8e-8872-2d964bde118b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009059560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tx_async_fifo_reset.1009059560
Directory	/workspace/41.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/41.spi_device_txrx.1640880918
Short name	T647
Test name
Test status
Simulation time	90415736275 ps
CPU time	196.09 seconds
Started	Jan 07 01:24:08 PM PST 24
Finished	Jan 07 01:27:27 PM PST 24
Peak memory	282568 kb
Host	smart-f5bc6d9d-b016-4c36-8f0c-5994b82e70c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640880918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_txrx.1640880918
Directory	/workspace/41.spi_device_txrx/latest

Test location	/workspace/coverage/default/41.spi_device_upload.665270133
Short name	T219
Test name
Test status
Simulation time	11845005978 ps
CPU time	14.87 seconds
Started	Jan 07 01:24:40 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	241536 kb
Host	smart-0e72e161-e208-47c8-b36f-c6cbbc084ff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665270133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.665270133
Directory	/workspace/41.spi_device_upload/latest

Test location	/workspace/coverage/default/42.spi_device_abort.2270825827
Short name	T1591
Test name
Test status
Simulation time	13959150 ps
CPU time	0.74 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	206612 kb
Host	smart-4d534249-0969-49d6-b1fc-3ef666ab7bb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270825827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_abort.2270825827
Directory	/workspace/42.spi_device_abort/latest

Test location	/workspace/coverage/default/42.spi_device_alert_test.3468042993
Short name	T935
Test name
Test status
Simulation time	29101484 ps
CPU time	0.81 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	206584 kb
Host	smart-f981bd75-5c58-48d5-af14-8f3ebaf40f9e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468042993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test. 3468042993
Directory	/workspace/42.spi_device_alert_test/latest

Test location	/workspace/coverage/default/42.spi_device_bit_transfer.2280516321
Short name	T1014
Test name
Test status
Simulation time	622962498 ps
CPU time	2.09 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	216800 kb
Host	smart-d81e533b-19d8-4487-a47a-50ed640cab4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280516321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_bit_transfer.2280516321
Directory	/workspace/42.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/42.spi_device_byte_transfer.751726004
Short name	T564
Test name
Test status
Simulation time	165622839 ps
CPU time	2.84 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	216896 kb
Host	smart-a40153ee-0159-46a0-a48d-23f337d03703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751726004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_byte_transfer.751726004
Directory	/workspace/42.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/42.spi_device_cfg_cmd.3577049862
Short name	T1174
Test name
Test status
Simulation time	2444497402 ps
CPU time	8 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:25:07 PM PST 24
Peak memory	240128 kb
Host	smart-e53fb66d-ac9a-4843-bb4c-9020a241d094
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577049862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3577049862
Directory	/workspace/42.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/42.spi_device_csb_read.3647078051
Short name	T730
Test name
Test status
Simulation time	93845776 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	207624 kb
Host	smart-4467de7c-f910-4d64-a6ff-c4b41a7187bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647078051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3647078051
Directory	/workspace/42.spi_device_csb_read/latest

Test location	/workspace/coverage/default/42.spi_device_dummy_item_extra_dly.1503032245
Short name	T1519
Test name
Test status
Simulation time	22871445850 ps
CPU time	126.45 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:27:25 PM PST 24
Peak memory	249152 kb
Host	smart-d3b943ef-b5e2-474a-9776-7190faa639ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503032245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_dummy_item_extra_dly.1503032245
Directory	/workspace/42.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/42.spi_device_extreme_fifo_size.2289041830
Short name	T177
Test name
Test status
Simulation time	164608826774 ps
CPU time	3286.93 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 02:19:57 PM PST 24
Peak memory	221504 kb
Host	smart-306f221e-a82b-4afd-9012-c3356d52735e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289041830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_extreme_fifo_size.2289041830
Directory	/workspace/42.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/42.spi_device_fifo_full.1471962698
Short name	T1196
Test name
Test status
Simulation time	16770922940 ps
CPU time	181.98 seconds
Started	Jan 07 01:24:40 PM PST 24
Finished	Jan 07 01:27:58 PM PST 24
Peak memory	276764 kb
Host	smart-187214d4-9de7-4c46-af5d-23fd546d7489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471962698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_full.1471962698
Directory	/workspace/42.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/42.spi_device_fifo_underflow_overflow.2587966115
Short name	T1415
Test name
Test status
Simulation time	468640664261 ps
CPU time	354.83 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:31:05 PM PST 24
Peak memory	516492 kb
Host	smart-96e6b08e-f16d-45f1-aa1d-a073225196ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587966115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_fifo_underflow_overf low.2587966115
Directory	/workspace/42.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/42.spi_device_flash_and_tpm.4162753645
Short name	T749
Test name
Test status
Simulation time	29037347239 ps
CPU time	88.41 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:26:38 PM PST 24
Peak memory	260424 kb
Host	smart-a7a3c559-6b68-4e7c-909a-708549cc8a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162753645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4162753645
Directory	/workspace/42.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/42.spi_device_flash_mode.2538925622
Short name	T331
Test name
Test status
Simulation time	25216706931 ps
CPU time	40.81 seconds
Started	Jan 07 01:24:45 PM PST 24
Finished	Jan 07 01:25:38 PM PST 24
Peak memory	238412 kb
Host	smart-0d61f040-1220-42ff-a94e-14cbb116d433
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538925622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2538925622
Directory	/workspace/42.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/42.spi_device_intercept.1102771991
Short name	T255
Test name
Test status
Simulation time	986736869 ps
CPU time	5.65 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:25:03 PM PST 24
Peak memory	237816 kb
Host	smart-94696fdb-3698-4043-99cf-c619909836f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102771991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1102771991
Directory	/workspace/42.spi_device_intercept/latest

Test location	/workspace/coverage/default/42.spi_device_intr.2652941821
Short name	T576
Test name
Test status
Simulation time	65536375542 ps
CPU time	23.05 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:39 PM PST 24
Peak memory	225164 kb
Host	smart-3baf074c-a5b0-4827-bcc5-9ca17d05b462
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652941821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intr.2652941821
Directory	/workspace/42.spi_device_intr/latest

Test location	/workspace/coverage/default/42.spi_device_mailbox.2827660145
Short name	T1722
Test name
Test status
Simulation time	685004029 ps
CPU time	6.33 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	222576 kb
Host	smart-a4d28630-a897-4cc5-ad1f-70748fbc4cb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827660145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2827660145
Directory	/workspace/42.spi_device_mailbox/latest

Test location	/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4144977703
Short name	T314
Test name
Test status
Simulation time	5123660661 ps
CPU time	18.97 seconds
Started	Jan 07 01:24:34 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	248048 kb
Host	smart-c007ab3e-2516-4d61-90e4-20ad32097bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144977703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa p.4144977703
Directory	/workspace/42.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/42.spi_device_pass_cmd_filtering.3461663528
Short name	T284
Test name
Test status
Simulation time	2300356670 ps
CPU time	5.82 seconds
Started	Jan 07 01:24:38 PM PST 24
Finished	Jan 07 01:25:03 PM PST 24
Peak memory	239928 kb
Host	smart-fe841139-7030-4151-bc64-c4dfa8039acb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461663528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3461663528
Directory	/workspace/42.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/42.spi_device_perf.3466931082
Short name	T958
Test name
Test status
Simulation time	31898347967 ps
CPU time	943.05 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:40:53 PM PST 24
Peak memory	260416 kb
Host	smart-3bb6c1ae-cf1d-4c82-8d51-c109a40d8bc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466931082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_perf.3466931082
Directory	/workspace/42.spi_device_perf/latest

Test location	/workspace/coverage/default/42.spi_device_read_buffer_direct.2098712461
Short name	T1688
Test name
Test status
Simulation time	1855551512 ps
CPU time	8.23 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:25:05 PM PST 24
Peak memory	236952 kb
Host	smart-69bf8381-464a-435e-bfde-1383e73c8ab3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2098712461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.2098712461
Directory	/workspace/42.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/42.spi_device_rx_async_fifo_reset.3950121930
Short name	T74
Test name
Test status
Simulation time	57990284 ps
CPU time	0.84 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:24:59 PM PST 24
Peak memory	208452 kb
Host	smart-365699ef-1fae-4454-bf00-9723063b14c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950121930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_async_fifo_reset.3950121930
Directory	/workspace/42.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/42.spi_device_rx_timeout.270617000
Short name	T1395
Test name
Test status
Simulation time	757178192 ps
CPU time	5.86 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:25:04 PM PST 24
Peak memory	216848 kb
Host	smart-7e196248-cb25-4e06-b65e-a697f923a439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270617000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_rx_timeout.270617000
Directory	/workspace/42.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/42.spi_device_smoke.2580438513
Short name	T1548
Test name
Test status
Simulation time	212033714 ps
CPU time	1.16 seconds
Started	Jan 07 01:24:21 PM PST 24
Finished	Jan 07 01:24:28 PM PST 24
Peak memory	216472 kb
Host	smart-cff21607-2a45-4ae9-a7ec-0b4d91ec64ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580438513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_smoke.2580438513
Directory	/workspace/42.spi_device_smoke/latest

Test location	/workspace/coverage/default/42.spi_device_stress_all.3313595698
Short name	T1482
Test name
Test status
Simulation time	2192170452164 ps
CPU time	2305.26 seconds
Started	Jan 07 01:24:35 PM PST 24
Finished	Jan 07 02:03:22 PM PST 24
Peak memory	617320 kb
Host	smart-82e5288e-c032-491d-aeb4-2571deb6c5f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313595698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre ss_all.3313595698
Directory	/workspace/42.spi_device_stress_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_all.4111802191
Short name	T107
Test name
Test status
Simulation time	3158220370 ps
CPU time	19.67 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:30 PM PST 24
Peak memory	220608 kb
Host	smart-d45e62f2-da33-4d49-b38e-51be6c2cbaa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111802191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4111802191
Directory	/workspace/42.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1052993713
Short name	T515
Test name
Test status
Simulation time	6240743581 ps
CPU time	15.47 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:25 PM PST 24
Peak memory	216824 kb
Host	smart-f7db94c3-abe8-4003-ad92-94130c61c50e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052993713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1052993713
Directory	/workspace/42.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_rw.2746355663
Short name	T742
Test name
Test status
Simulation time	100355696 ps
CPU time	1.37 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	216836 kb
Host	smart-38168c4f-34b6-47b3-b766-bd91cfd57caa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746355663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2746355663
Directory	/workspace/42.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_sts_read.3193503492
Short name	T630
Test name
Test status
Simulation time	140831047 ps
CPU time	0.93 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:10 PM PST 24
Peak memory	207068 kb
Host	smart-4b93186d-5787-453f-bb17-fcd14d496a56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193503492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3193503492
Directory	/workspace/42.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/42.spi_device_tx_async_fifo_reset.3777591203
Short name	T1137
Test name
Test status
Simulation time	44974780 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:34 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	208484 kb
Host	smart-ff58a78c-e181-47e8-9e63-9cf74b0dd730
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777591203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tx_async_fifo_reset.3777591203
Directory	/workspace/42.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/42.spi_device_txrx.551475512
Short name	T622
Test name
Test status
Simulation time	42080560366 ps
CPU time	317.51 seconds
Started	Jan 07 01:24:44 PM PST 24
Finished	Jan 07 01:30:14 PM PST 24
Peak memory	289564 kb
Host	smart-6678dee7-6aea-4f28-bda3-9b709ad4cfd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551475512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_txrx.551475512
Directory	/workspace/42.spi_device_txrx/latest

Test location	/workspace/coverage/default/42.spi_device_upload.1294842135
Short name	T272
Test name
Test status
Simulation time	673971543 ps
CPU time	9.67 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:25:06 PM PST 24
Peak memory	247800 kb
Host	smart-c468072e-afda-45a6-933c-4418f4fcc969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294842135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1294842135
Directory	/workspace/42.spi_device_upload/latest

Test location	/workspace/coverage/default/43.spi_device_abort.954891666
Short name	T1258
Test name
Test status
Simulation time	45681374 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:37 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	206680 kb
Host	smart-b7c37590-d81a-4dcf-9cd9-916fe6feacb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954891666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_abort.954891666
Directory	/workspace/43.spi_device_abort/latest

Test location	/workspace/coverage/default/43.spi_device_alert_test.2842595947
Short name	T1044
Test name
Test status
Simulation time	47942995 ps
CPU time	0.71 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	206364 kb
Host	smart-56262b90-3924-4e63-9cb9-6a9badbe1fef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842595947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test. 2842595947
Directory	/workspace/43.spi_device_alert_test/latest

Test location	/workspace/coverage/default/43.spi_device_bit_transfer.699902276
Short name	T569
Test name
Test status
Simulation time	432042747 ps
CPU time	2.2 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	216872 kb
Host	smart-9b3b9d66-3857-4f25-8250-52bbaa43d5e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699902276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_bit_transfer.699902276
Directory	/workspace/43.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/43.spi_device_byte_transfer.2730131561
Short name	T1463
Test name
Test status
Simulation time	750809500 ps
CPU time	2.85 seconds
Started	Jan 07 01:24:36 PM PST 24
Finished	Jan 07 01:25:03 PM PST 24
Peak memory	216832 kb
Host	smart-de41d3c7-ddcb-407e-b2fd-465e9c7fa460
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730131561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_byte_transfer.2730131561
Directory	/workspace/43.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/43.spi_device_cfg_cmd.3570871683
Short name	T1555
Test name
Test status
Simulation time	1878573713 ps
CPU time	4.11 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	220576 kb
Host	smart-63f857ab-ae14-42b8-9219-2cfda2838960
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570871683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3570871683
Directory	/workspace/43.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/43.spi_device_csb_read.3526722719
Short name	T1561
Test name
Test status
Simulation time	86811640 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	206524 kb
Host	smart-e17b9be4-229d-407e-bc3c-2f1566b80768
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526722719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3526722719
Directory	/workspace/43.spi_device_csb_read/latest

Test location	/workspace/coverage/default/43.spi_device_dummy_item_extra_dly.1959788925
Short name	T1642
Test name
Test status
Simulation time	15441295573 ps
CPU time	249.53 seconds
Started	Jan 07 01:24:45 PM PST 24
Finished	Jan 07 01:29:07 PM PST 24
Peak memory	231852 kb
Host	smart-8d999dbe-25cf-4f34-a0e9-a5b2bad8c1b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959788925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_dummy_item_extra_dly.1959788925
Directory	/workspace/43.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/43.spi_device_extreme_fifo_size.1812001341
Short name	T1004
Test name
Test status
Simulation time	11756214005 ps
CPU time	19.54 seconds
Started	Jan 07 01:24:36 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	221084 kb
Host	smart-38e6aa5f-c8b7-4f69-8a79-62a6bc0ed095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812001341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_extreme_fifo_size.1812001341
Directory	/workspace/43.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/43.spi_device_fifo_full.4141467670
Short name	T807
Test name
Test status
Simulation time	20868632645 ps
CPU time	1080.45 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:43:00 PM PST 24
Peak memory	298592 kb
Host	smart-9520ee9d-46c4-4c0e-b3ca-88cbaaae2ff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141467670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_full.4141467670
Directory	/workspace/43.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/43.spi_device_fifo_underflow_overflow.2393430583
Short name	T1330
Test name
Test status
Simulation time	81264772545 ps
CPU time	756.11 seconds
Started	Jan 07 01:24:34 PM PST 24
Finished	Jan 07 01:37:29 PM PST 24
Peak memory	458032 kb
Host	smart-05f422ef-dbc8-4c5c-87b5-d269a1fd5c7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393430583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_fifo_underflow_overf low.2393430583
Directory	/workspace/43.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/43.spi_device_flash_all.1887506146
Short name	T1332
Test name
Test status
Simulation time	2396565355 ps
CPU time	10.3 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	241392 kb
Host	smart-48030a71-6ff4-48cb-a43b-cd0921270247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887506146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1887506146
Directory	/workspace/43.spi_device_flash_all/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm.691250079
Short name	T23
Test name
Test status
Simulation time	24008448691 ps
CPU time	85.3 seconds
Started	Jan 07 01:24:34 PM PST 24
Finished	Jan 07 01:26:18 PM PST 24
Peak memory	269636 kb
Host	smart-00fe36ca-f72c-4727-aa1b-846805460f56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691250079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.691250079
Directory	/workspace/43.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.450350141
Short name	T1005
Test name
Test status
Simulation time	112011045860 ps
CPU time	457.78 seconds
Started	Jan 07 01:24:40 PM PST 24
Finished	Jan 07 01:32:34 PM PST 24
Peak memory	268272 kb
Host	smart-54216808-ef94-44e7-aaeb-56837136dcdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450350141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle .450350141
Directory	/workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/43.spi_device_flash_mode.2174109907
Short name	T636
Test name
Test status
Simulation time	400177233 ps
CPU time	17.01 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	223080 kb
Host	smart-1963aee3-b13d-4282-bb39-23c9be97bc41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174109907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2174109907
Directory	/workspace/43.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/43.spi_device_intercept.288367953
Short name	T1348
Test name
Test status
Simulation time	403047940 ps
CPU time	4.47 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:25:03 PM PST 24
Peak memory	219340 kb
Host	smart-2aa3808a-20b1-42b2-96c0-445fc24da644
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288367953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.288367953
Directory	/workspace/43.spi_device_intercept/latest

Test location	/workspace/coverage/default/43.spi_device_intr.1276906692
Short name	T468
Test name
Test status
Simulation time	30187311471 ps
CPU time	56.12 seconds
Started	Jan 07 01:24:45 PM PST 24
Finished	Jan 07 01:25:54 PM PST 24
Peak memory	236476 kb
Host	smart-655821e9-3dd6-4fcf-af62-43ddd7391c73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276906692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intr.1276906692
Directory	/workspace/43.spi_device_intr/latest

Test location	/workspace/coverage/default/43.spi_device_mailbox.4279012234
Short name	T1602
Test name
Test status
Simulation time	4829037087 ps
CPU time	27.78 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:38 PM PST 24
Peak memory	257040 kb
Host	smart-d89818de-f75a-4854-aa03-f42f82eebf40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279012234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4279012234
Directory	/workspace/43.spi_device_mailbox/latest

Test location	/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.82946632
Short name	T1677
Test name
Test status
Simulation time	2941734082 ps
CPU time	10.66 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	226804 kb
Host	smart-094d7208-8a07-4fc3-bb89-ff1670d46781
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82946632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.82946632
Directory	/workspace/43.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/43.spi_device_pass_cmd_filtering.3683656962
Short name	T189
Test name
Test status
Simulation time	16077026433 ps
CPU time	14.54 seconds
Started	Jan 07 01:24:45 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	234408 kb
Host	smart-867ed1c8-381e-4ae6-ae15-86a943c2ecc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683656962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3683656962
Directory	/workspace/43.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/43.spi_device_perf.3440591061
Short name	T1603
Test name
Test status
Simulation time	46851880993 ps
CPU time	282.62 seconds
Started	Jan 07 01:24:46 PM PST 24
Finished	Jan 07 01:29:41 PM PST 24
Peak memory	274184 kb
Host	smart-544f662d-0222-454c-890b-9db9febd0847
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440591061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_perf.3440591061
Directory	/workspace/43.spi_device_perf/latest

Test location	/workspace/coverage/default/43.spi_device_read_buffer_direct.564196969
Short name	T1303
Test name
Test status
Simulation time	538297537 ps
CPU time	5.48 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	234204 kb
Host	smart-88875476-e1f0-4ffe-8e04-4b08433a662e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=564196969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire ct.564196969
Directory	/workspace/43.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/43.spi_device_rx_async_fifo_reset.1287831369
Short name	T1363
Test name
Test status
Simulation time	425271311 ps
CPU time	0.95 seconds
Started	Jan 07 01:24:35 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	208476 kb
Host	smart-3f43d3f7-8e9f-46b1-b2c4-8719f21f879d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287831369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_async_fifo_reset.1287831369
Directory	/workspace/43.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/43.spi_device_rx_timeout.1856669470
Short name	T1661
Test name
Test status
Simulation time	3431300246 ps
CPU time	5.53 seconds
Started	Jan 07 01:24:33 PM PST 24
Finished	Jan 07 01:25:02 PM PST 24
Peak memory	216860 kb
Host	smart-3a0a8b65-4b4d-4455-872b-c28cbbbb1a16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856669470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_rx_timeout.1856669470
Directory	/workspace/43.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/43.spi_device_smoke.1079681571
Short name	T902
Test name
Test status
Simulation time	22646254 ps
CPU time	0.94 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:25:01 PM PST 24
Peak memory	207864 kb
Host	smart-a5f7da22-2a15-4d3a-9417-9688458b89d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079681571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_smoke.1079681571
Directory	/workspace/43.spi_device_smoke/latest

Test location	/workspace/coverage/default/43.spi_device_stress_all.2868768707
Short name	T1643
Test name
Test status
Simulation time	42798074868 ps
CPU time	383.75 seconds
Started	Jan 07 01:24:45 PM PST 24
Finished	Jan 07 01:31:21 PM PST 24
Peak memory	446980 kb
Host	smart-fde5d923-793e-4b7c-9258-b970f55c2776
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868768707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre ss_all.2868768707
Directory	/workspace/43.spi_device_stress_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_all.613825374
Short name	T733
Test name
Test status
Simulation time	7168198460 ps
CPU time	27.19 seconds
Started	Jan 07 01:24:43 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	221080 kb
Host	smart-48d3ef49-d02a-40cd-99c8-e15275024d1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613825374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.613825374
Directory	/workspace/43.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.488305540
Short name	T1503
Test name
Test status
Simulation time	15904199490 ps
CPU time	7.7 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	216828 kb
Host	smart-603aa723-e494-46b5-b646-e2b1a155fe30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488305540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.488305540
Directory	/workspace/43.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_rw.1649281068
Short name	T624
Test name
Test status
Simulation time	214661052 ps
CPU time	2.93 seconds
Started	Jan 07 01:24:47 PM PST 24
Finished	Jan 07 01:25:04 PM PST 24
Peak memory	216876 kb
Host	smart-d6b7e850-1021-424c-bc0c-8b8083fbdb72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649281068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1649281068
Directory	/workspace/43.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_sts_read.997809708
Short name	T1120
Test name
Test status
Simulation time	40065508 ps
CPU time	0.71 seconds
Started	Jan 07 01:24:38 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	206872 kb
Host	smart-bfe6d7e3-4064-4a38-b735-7a221eee58f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997809708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.997809708
Directory	/workspace/43.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/43.spi_device_tx_async_fifo_reset.4132232985
Short name	T1478
Test name
Test status
Simulation time	16833726 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:37 PM PST 24
Finished	Jan 07 01:24:58 PM PST 24
Peak memory	208412 kb
Host	smart-b7a15f3c-f953-46cd-820c-bdd77d9d66b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132232985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tx_async_fifo_reset.4132232985
Directory	/workspace/43.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/43.spi_device_txrx.1061681612
Short name	T947
Test name
Test status
Simulation time	48466915419 ps
CPU time	217.33 seconds
Started	Jan 07 01:24:39 PM PST 24
Finished	Jan 07 01:28:36 PM PST 24
Peak memory	249732 kb
Host	smart-ef77fc61-3984-4446-a4bf-fdb3097091d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061681612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_txrx.1061681612
Directory	/workspace/43.spi_device_txrx/latest

Test location	/workspace/coverage/default/43.spi_device_upload.3765026846
Short name	T273
Test name
Test status
Simulation time	11925991550 ps
CPU time	36.54 seconds
Started	Jan 07 01:24:42 PM PST 24
Finished	Jan 07 01:25:32 PM PST 24
Peak memory	219180 kb
Host	smart-579f6ba0-2f54-4c3a-a737-813d706dd88f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765026846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3765026846
Directory	/workspace/43.spi_device_upload/latest

Test location	/workspace/coverage/default/44.spi_device_abort.1466011803
Short name	T1242
Test name
Test status
Simulation time	14304633 ps
CPU time	0.8 seconds
Started	Jan 07 01:24:57 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	206704 kb
Host	smart-99269759-e933-44bc-83e1-3970f9a9f148
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466011803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_abort.1466011803
Directory	/workspace/44.spi_device_abort/latest

Test location	/workspace/coverage/default/44.spi_device_alert_test.1488364599
Short name	T1175
Test name
Test status
Simulation time	12023579 ps
CPU time	0.74 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	206532 kb
Host	smart-f0a20427-a24b-4aac-ade8-a38648071791
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488364599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 1488364599
Directory	/workspace/44.spi_device_alert_test/latest

Test location	/workspace/coverage/default/44.spi_device_bit_transfer.2262302429
Short name	T1645
Test name
Test status
Simulation time	1123861184 ps
CPU time	2.42 seconds
Started	Jan 07 01:24:57 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	216736 kb
Host	smart-c5258cf2-04fb-4bec-a7f6-fbee0d12d6b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262302429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_bit_transfer.2262302429
Directory	/workspace/44.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/44.spi_device_byte_transfer.3861065783
Short name	T435
Test name
Test status
Simulation time	269323426 ps
CPU time	3.38 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	216900 kb
Host	smart-29035437-df04-4f54-a80b-da0acabe5226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861065783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_byte_transfer.3861065783
Directory	/workspace/44.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/44.spi_device_cfg_cmd.3413809505
Short name	T1422
Test name
Test status
Simulation time	1829121442 ps
CPU time	5.88 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	239888 kb
Host	smart-b0735f73-c65c-41be-9ee9-899bf48213b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413809505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3413809505
Directory	/workspace/44.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/44.spi_device_csb_read.764574935
Short name	T1045
Test name
Test status
Simulation time	40585224 ps
CPU time	0.8 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:10 PM PST 24
Peak memory	207564 kb
Host	smart-78736cef-86b5-4799-bf9d-a3239b43d5a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764574935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.764574935
Directory	/workspace/44.spi_device_csb_read/latest

Test location	/workspace/coverage/default/44.spi_device_dummy_item_extra_dly.1062623227
Short name	T1080
Test name
Test status
Simulation time	17416077766 ps
CPU time	138.91 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:27:29 PM PST 24
Peak memory	233360 kb
Host	smart-56652879-37ff-4167-935a-607d5819d9cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062623227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_dummy_item_extra_dly.1062623227
Directory	/workspace/44.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/44.spi_device_extreme_fifo_size.947008500
Short name	T1522
Test name
Test status
Simulation time	54592692287 ps
CPU time	744.01 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:37:40 PM PST 24
Peak memory	218944 kb
Host	smart-adcb65d2-61fe-4782-8f63-d77c829f7b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947008500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_extreme_fifo_size.947008500
Directory	/workspace/44.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/44.spi_device_fifo_full.2537725750
Short name	T794
Test name
Test status
Simulation time	13756393027 ps
CPU time	324.68 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:30:35 PM PST 24
Peak memory	297040 kb
Host	smart-a194e014-ea89-4cf9-91ec-0bc344147d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537725750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_full.2537725750
Directory	/workspace/44.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/44.spi_device_fifo_underflow_overflow.1980809320
Short name	T1116
Test name
Test status
Simulation time	25777314239 ps
CPU time	414.63 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:32:10 PM PST 24
Peak memory	409860 kb
Host	smart-44271b77-d390-4440-8acc-96de95ffa43c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980809320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_fifo_underflow_overf low.1980809320
Directory	/workspace/44.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/44.spi_device_flash_all.1227375181
Short name	T1141
Test name
Test status
Simulation time	9425826000 ps
CPU time	51.48 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:26:06 PM PST 24
Peak memory	249740 kb
Host	smart-6cb7a89f-cf99-4c3a-a988-a43da1b5467f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227375181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1227375181
Directory	/workspace/44.spi_device_flash_all/latest

Test location	/workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.386960544
Short name	T1381
Test name
Test status
Simulation time	22593800054 ps
CPU time	51.04 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:26:01 PM PST 24
Peak memory	249584 kb
Host	smart-d07388af-aea7-426e-b723-8a6fe65f7087
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386960544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle .386960544
Directory	/workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/44.spi_device_flash_mode.1126962170
Short name	T1386
Test name
Test status
Simulation time	2792816388 ps
CPU time	14.01 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:28 PM PST 24
Peak memory	247860 kb
Host	smart-1627eba4-2475-448f-af64-b8efaf952cbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126962170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1126962170
Directory	/workspace/44.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/44.spi_device_intercept.1370511995
Short name	T1094
Test name
Test status
Simulation time	318841466 ps
CPU time	5.4 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	225128 kb
Host	smart-3ebef9e1-ae35-4837-b63d-0d54d58fa8a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370511995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1370511995
Directory	/workspace/44.spi_device_intercept/latest

Test location	/workspace/coverage/default/44.spi_device_intr.2259138253
Short name	T1743
Test name
Test status
Simulation time	74740767884 ps
CPU time	86.46 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:26:35 PM PST 24
Peak memory	238892 kb
Host	smart-edb70105-f7e8-4c0a-922b-bfd47ce78663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259138253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intr.2259138253
Directory	/workspace/44.spi_device_intr/latest

Test location	/workspace/coverage/default/44.spi_device_mailbox.3544240393
Short name	T783
Test name
Test status
Simulation time	547172019 ps
CPU time	4.29 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	218732 kb
Host	smart-f73a2c6d-1f45-48d1-a307-5e630649873c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544240393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3544240393
Directory	/workspace/44.spi_device_mailbox/latest

Test location	/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.280040800
Short name	T310
Test name
Test status
Simulation time	10435018613 ps
CPU time	34.63 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:25:43 PM PST 24
Peak memory	257396 kb
Host	smart-9740fce2-cddf-4e1e-9644-4dd53818ba83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280040800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap .280040800
Directory	/workspace/44.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/44.spi_device_pass_cmd_filtering.750384773
Short name	T915
Test name
Test status
Simulation time	6141190884 ps
CPU time	10.94 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	236396 kb
Host	smart-8a1bf031-d243-462a-8b3e-831070a8975d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750384773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.750384773
Directory	/workspace/44.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/44.spi_device_perf.656557995
Short name	T31
Test name
Test status
Simulation time	7695555795 ps
CPU time	203.92 seconds
Started	Jan 07 01:24:57 PM PST 24
Finished	Jan 07 01:28:34 PM PST 24
Peak memory	273840 kb
Host	smart-ba571159-49b0-420d-a2ac-acb662da2f32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656557995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_perf.656557995
Directory	/workspace/44.spi_device_perf/latest

Test location	/workspace/coverage/default/44.spi_device_read_buffer_direct.2797783035
Short name	T168
Test name
Test status
Simulation time	2845765240 ps
CPU time	6.11 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	221284 kb
Host	smart-6fb86c34-9cfa-4e83-89ae-2d6157e87d4e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2797783035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir ect.2797783035
Directory	/workspace/44.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/44.spi_device_rx_async_fifo_reset.1158186011
Short name	T679
Test name
Test status
Simulation time	57594907 ps
CPU time	0.88 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:18 PM PST 24
Peak memory	208400 kb
Host	smart-d53596a2-3abc-474c-8587-ad11bd403ad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158186011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_async_fifo_reset.1158186011
Directory	/workspace/44.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/44.spi_device_rx_timeout.210711100
Short name	T1712
Test name
Test status
Simulation time	629706593 ps
CPU time	5.34 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	216848 kb
Host	smart-c0dee7d5-4bfe-4889-a061-a97b281485f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210711100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_rx_timeout.210711100
Directory	/workspace/44.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/44.spi_device_smoke.1472373225
Short name	T452
Test name
Test status
Simulation time	40828325 ps
CPU time	1.07 seconds
Started	Jan 07 01:24:35 PM PST 24
Finished	Jan 07 01:24:57 PM PST 24
Peak memory	216604 kb
Host	smart-bba809d5-0fbc-42c6-ac4c-9e562f3b0eda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472373225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_smoke.1472373225
Directory	/workspace/44.spi_device_smoke/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_all.2124045619
Short name	T607
Test name
Test status
Simulation time	11979410352 ps
CPU time	28.46 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:25:37 PM PST 24
Peak memory	220644 kb
Host	smart-4b6693ab-da0c-41d1-a95c-fa2e0eab5816
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124045619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2124045619
Directory	/workspace/44.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2834598879
Short name	T1573
Test name
Test status
Simulation time	8263689455 ps
CPU time	12.15 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	216752 kb
Host	smart-0838b6a5-e41e-49c0-bf87-46f3f6ed4926
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834598879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2834598879
Directory	/workspace/44.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_rw.2172067984
Short name	T1726
Test name
Test status
Simulation time	197353910 ps
CPU time	1.43 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	216556 kb
Host	smart-887dad0f-a915-49e3-b522-7a1001d37edd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172067984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2172067984
Directory	/workspace/44.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_sts_read.2025300056
Short name	T476
Test name
Test status
Simulation time	23829016 ps
CPU time	0.76 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	206800 kb
Host	smart-e3d2fcd5-f112-40e0-bf87-55b804f335f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025300056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2025300056
Directory	/workspace/44.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/44.spi_device_tx_async_fifo_reset.3376271615
Short name	T627
Test name
Test status
Simulation time	50070496 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:10 PM PST 24
Peak memory	208328 kb
Host	smart-052381db-58e4-48d0-a057-786e2d5fbef6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376271615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tx_async_fifo_reset.3376271615
Directory	/workspace/44.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/44.spi_device_txrx.3165113556
Short name	T617
Test name
Test status
Simulation time	27353370748 ps
CPU time	443.22 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:32:40 PM PST 24
Peak memory	254536 kb
Host	smart-f3b4461f-08f7-4f2a-a3c0-596be67943db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165113556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_txrx.3165113556
Directory	/workspace/44.spi_device_txrx/latest

Test location	/workspace/coverage/default/44.spi_device_upload.1834049428
Short name	T1398
Test name
Test status
Simulation time	25927099353 ps
CPU time	11.24 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	219456 kb
Host	smart-42fd665e-1e0c-4a77-9d56-ce8672a03fbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834049428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1834049428
Directory	/workspace/44.spi_device_upload/latest

Test location	/workspace/coverage/default/45.spi_device_abort.2804397819
Short name	T1206
Test name
Test status
Simulation time	89361175 ps
CPU time	0.76 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	206580 kb
Host	smart-b1e16c6b-1ae2-4e59-a856-80516eab6470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804397819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_abort.2804397819
Directory	/workspace/45.spi_device_abort/latest

Test location	/workspace/coverage/default/45.spi_device_alert_test.2861429463
Short name	T1378
Test name
Test status
Simulation time	13039218 ps
CPU time	0.68 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	206296 kb
Host	smart-6220f91d-6afc-4bd9-ac5a-cdaa8a437573
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861429463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 2861429463
Directory	/workspace/45.spi_device_alert_test/latest

Test location	/workspace/coverage/default/45.spi_device_bit_transfer.1343834438
Short name	T649
Test name
Test status
Simulation time	1153272002 ps
CPU time	2.15 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	216812 kb
Host	smart-a0859611-f3a5-4989-bd78-8cfc754741d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343834438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_bit_transfer.1343834438
Directory	/workspace/45.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/45.spi_device_byte_transfer.2640928593
Short name	T39
Test name
Test status
Simulation time	182856003 ps
CPU time	2.43 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:12 PM PST 24
Peak memory	216772 kb
Host	smart-59866276-16c4-418d-ae98-418d894b046b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640928593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_byte_transfer.2640928593
Directory	/workspace/45.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/45.spi_device_cfg_cmd.2507356749
Short name	T791
Test name
Test status
Simulation time	107989007 ps
CPU time	2.57 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:18 PM PST 24
Peak memory	237996 kb
Host	smart-a9f4b0c3-db66-42de-8f2a-b6c8ced91431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507356749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2507356749
Directory	/workspace/45.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/45.spi_device_csb_read.820591193
Short name	T644
Test name
Test status
Simulation time	20981648 ps
CPU time	0.78 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	206616 kb
Host	smart-2614c0a3-ba89-417b-94e9-f55f9e293acf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820591193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.820591193
Directory	/workspace/45.spi_device_csb_read/latest

Test location	/workspace/coverage/default/45.spi_device_dummy_item_extra_dly.2818250760
Short name	T1410
Test name
Test status
Simulation time	70798195762 ps
CPU time	188.12 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:28:17 PM PST 24
Peak memory	299804 kb
Host	smart-00c4f84b-5024-43c4-a3c6-79e0b3091378
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818250760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_dummy_item_extra_dly.2818250760
Directory	/workspace/45.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/45.spi_device_extreme_fifo_size.3680020760
Short name	T259
Test name
Test status
Simulation time	594672540464 ps
CPU time	2359.65 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 02:04:35 PM PST 24
Peak memory	225172 kb
Host	smart-d57fc0ea-3901-4df3-8f31-2bf9a13222d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680020760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_extreme_fifo_size.3680020760
Directory	/workspace/45.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/45.spi_device_fifo_full.1603241387
Short name	T1131
Test name
Test status
Simulation time	62611523971 ps
CPU time	557.59 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:34:38 PM PST 24
Peak memory	285592 kb
Host	smart-49bd7989-be33-46b7-a833-ee492c94254a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603241387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_full.1603241387
Directory	/workspace/45.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/45.spi_device_fifo_underflow_overflow.3582018611
Short name	T993
Test name
Test status
Simulation time	75424547726 ps
CPU time	417.44 seconds
Started	Jan 07 01:24:52 PM PST 24
Finished	Jan 07 01:32:06 PM PST 24
Peak memory	405120 kb
Host	smart-883939b0-99e2-42ce-9084-2f7885a920de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582018611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_fifo_underflow_overf low.3582018611
Directory	/workspace/45.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/45.spi_device_flash_all.991470846
Short name	T912
Test name
Test status
Simulation time	25836135464 ps
CPU time	100.35 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:26:50 PM PST 24
Peak memory	255264 kb
Host	smart-71e37a4c-25d1-484a-9f07-eb505231c9da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991470846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.991470846
Directory	/workspace/45.spi_device_flash_all/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm.2764753079
Short name	T243
Test name
Test status
Simulation time	51184186976 ps
CPU time	378.9 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:31:29 PM PST 24
Peak memory	273420 kb
Host	smart-de2f0d58-4293-433b-bd3a-0938172ebf9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764753079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2764753079
Directory	/workspace/45.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3220581240
Short name	T1337
Test name
Test status
Simulation time	43636705093 ps
CPU time	151.44 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:27:42 PM PST 24
Peak memory	257444 kb
Host	smart-7e267809-0419-49a6-a327-10329e465754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220581240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl e.3220581240
Directory	/workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/45.spi_device_flash_mode.2157006163
Short name	T1146
Test name
Test status
Simulation time	3718057771 ps
CPU time	10.47 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	249424 kb
Host	smart-58733ebe-a1b5-42ab-8d42-f91cc9be3c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157006163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2157006163
Directory	/workspace/45.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/45.spi_device_intercept.3184676360
Short name	T1511
Test name
Test status
Simulation time	225799366 ps
CPU time	5.01 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	220760 kb
Host	smart-4915da47-0cf9-4f14-819c-55534cd1f2b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184676360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3184676360
Directory	/workspace/45.spi_device_intercept/latest

Test location	/workspace/coverage/default/45.spi_device_intr.3562455546
Short name	T1637
Test name
Test status
Simulation time	59936896079 ps
CPU time	33.91 seconds
Started	Jan 07 01:24:57 PM PST 24
Finished	Jan 07 01:25:44 PM PST 24
Peak memory	223708 kb
Host	smart-2d7c9012-4bb3-4080-a121-d3e7b3f44c33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562455546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intr.3562455546
Directory	/workspace/45.spi_device_intr/latest

Test location	/workspace/coverage/default/45.spi_device_mailbox.289167817
Short name	T1721
Test name
Test status
Simulation time	5364470861 ps
CPU time	16.34 seconds
Started	Jan 07 01:24:56 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	235492 kb
Host	smart-64db5555-55ae-4795-8ed4-bc28a9e41c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289167817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.289167817
Directory	/workspace/45.spi_device_mailbox/latest

Test location	/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1574101660
Short name	T304
Test name
Test status
Simulation time	7858609519 ps
CPU time	25.72 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:36 PM PST 24
Peak memory	249724 kb
Host	smart-c138894b-b18f-4157-9350-ce4a5c353ec5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574101660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa p.1574101660
Directory	/workspace/45.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/45.spi_device_pass_cmd_filtering.2484129956
Short name	T737
Test name
Test status
Simulation time	2481982822 ps
CPU time	11.87 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:27 PM PST 24
Peak memory	249664 kb
Host	smart-d85d9501-bcc7-40b9-88d3-046cb1755c93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484129956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2484129956
Directory	/workspace/45.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/45.spi_device_perf.1582956090
Short name	T510
Test name
Test status
Simulation time	94031529214 ps
CPU time	538.79 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:34:09 PM PST 24
Peak memory	250828 kb
Host	smart-77bdb8c9-62ba-4f11-ab34-40fbf6e23c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582956090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_perf.1582956090
Directory	/workspace/45.spi_device_perf/latest

Test location	/workspace/coverage/default/45.spi_device_read_buffer_direct.1029083787
Short name	T1646
Test name
Test status
Simulation time	292935674 ps
CPU time	3.92 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:18 PM PST 24
Peak memory	234120 kb
Host	smart-95b38077-7023-491a-a939-1be10d98473f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1029083787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir ect.1029083787
Directory	/workspace/45.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/45.spi_device_rx_async_fifo_reset.2872730410
Short name	T72
Test name
Test status
Simulation time	48006920 ps
CPU time	0.91 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	208440 kb
Host	smart-752ee704-433c-440e-89dd-3447a94b299a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872730410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_async_fifo_reset.2872730410
Directory	/workspace/45.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/45.spi_device_rx_timeout.3351434556
Short name	T585
Test name
Test status
Simulation time	2834051065 ps
CPU time	5.56 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	216848 kb
Host	smart-60286005-5685-488f-92e0-f140b47ab73a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351434556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_rx_timeout.3351434556
Directory	/workspace/45.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/45.spi_device_smoke.782001970
Short name	T1069
Test name
Test status
Simulation time	312288648 ps
CPU time	1.17 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	208028 kb
Host	smart-b88b0cb0-2e05-4362-88d6-cb6515f4333e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782001970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_smoke.782001970
Directory	/workspace/45.spi_device_smoke/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_all.312434705
Short name	T343
Test name
Test status
Simulation time	2760009538 ps
CPU time	17.18 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:30 PM PST 24
Peak memory	220672 kb
Host	smart-2b38d5de-cf08-45c6-82ee-252a81b8dd8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312434705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.312434705
Directory	/workspace/45.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.633386628
Short name	T1027
Test name
Test status
Simulation time	9173951668 ps
CPU time	5.11 seconds
Started	Jan 07 01:24:55 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	216804 kb
Host	smart-950d1684-b5e5-4670-b204-e14279409d38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633386628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.633386628
Directory	/workspace/45.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_rw.1348484112
Short name	T1191
Test name
Test status
Simulation time	248967810 ps
CPU time	1.8 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:12 PM PST 24
Peak memory	208580 kb
Host	smart-39c8d1ce-c545-49ac-8e19-0054c7087ec6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348484112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1348484112
Directory	/workspace/45.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_sts_read.3162462966
Short name	T491
Test name
Test status
Simulation time	121047596 ps
CPU time	1.15 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:25:11 PM PST 24
Peak memory	207976 kb
Host	smart-8d409e7d-e79f-4154-8760-1c2f914a7fd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162462966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3162462966
Directory	/workspace/45.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/45.spi_device_tx_async_fifo_reset.41418977
Short name	T1748
Test name
Test status
Simulation time	58134183 ps
CPU time	0.78 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	208412 kb
Host	smart-2a32021d-b06b-47c0-b8c9-f15b5e95a73e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41418977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tx_async_fifo_reset.41418977
Directory	/workspace/45.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/45.spi_device_txrx.2190578315
Short name	T1683
Test name
Test status
Simulation time	14446320882 ps
CPU time	261.42 seconds
Started	Jan 07 01:24:54 PM PST 24
Finished	Jan 07 01:29:31 PM PST 24
Peak memory	272644 kb
Host	smart-d9670f6e-cd1f-4e7f-acf5-1f563028635b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190578315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_txrx.2190578315
Directory	/workspace/45.spi_device_txrx/latest

Test location	/workspace/coverage/default/45.spi_device_upload.351569967
Short name	T516
Test name
Test status
Simulation time	10413689535 ps
CPU time	38.99 seconds
Started	Jan 07 01:24:53 PM PST 24
Finished	Jan 07 01:25:48 PM PST 24
Peak memory	251592 kb
Host	smart-b9f69398-808b-4d4e-b776-bbc67a1b3a51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351569967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.351569967
Directory	/workspace/45.spi_device_upload/latest

Test location	/workspace/coverage/default/46.spi_device_abort.3858873729
Short name	T753
Test name
Test status
Simulation time	14897531 ps
CPU time	0.78 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	206676 kb
Host	smart-3ac5f85f-6e47-43e1-816e-aa8220dace45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858873729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_abort.3858873729
Directory	/workspace/46.spi_device_abort/latest

Test location	/workspace/coverage/default/46.spi_device_alert_test.3908511420
Short name	T1650
Test name
Test status
Simulation time	14555355 ps
CPU time	0.7 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:18 PM PST 24
Peak memory	206512 kb
Host	smart-ab18a8ee-93c2-475f-847c-956d1dea8fb7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908511420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 3908511420
Directory	/workspace/46.spi_device_alert_test/latest

Test location	/workspace/coverage/default/46.spi_device_bit_transfer.3520732902
Short name	T866
Test name
Test status
Simulation time	127945541 ps
CPU time	2.34 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	216604 kb
Host	smart-d49c487b-a427-4dc9-9f3f-99a9d5a331f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520732902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_bit_transfer.3520732902
Directory	/workspace/46.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/46.spi_device_byte_transfer.1489209618
Short name	T1025
Test name
Test status
Simulation time	170021610 ps
CPU time	2.36 seconds
Started	Jan 07 01:25:10 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	216896 kb
Host	smart-db536f03-cea4-4c93-bba8-e4ddcba27cef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489209618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_byte_transfer.1489209618
Directory	/workspace/46.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/46.spi_device_cfg_cmd.2514601369
Short name	T1007
Test name
Test status
Simulation time	9035727908 ps
CPU time	4.29 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:25 PM PST 24
Peak memory	225124 kb
Host	smart-edcb36ae-f781-46a0-ad43-757659754c2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514601369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2514601369
Directory	/workspace/46.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/46.spi_device_csb_read.1298855101
Short name	T1720
Test name
Test status
Simulation time	24697819 ps
CPU time	0.77 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:18 PM PST 24
Peak memory	207556 kb
Host	smart-59528a62-92da-4cf7-8b1d-0cebeeeea497
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298855101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1298855101
Directory	/workspace/46.spi_device_csb_read/latest

Test location	/workspace/coverage/default/46.spi_device_dummy_item_extra_dly.2900594041
Short name	T552
Test name
Test status
Simulation time	153958530871 ps
CPU time	552.63 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:34:29 PM PST 24
Peak memory	282332 kb
Host	smart-5aec5289-834b-43ae-a0fe-3273de723cd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900594041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_dummy_item_extra_dly.2900594041
Directory	/workspace/46.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/46.spi_device_extreme_fifo_size.2133078461
Short name	T1494
Test name
Test status
Simulation time	23065085603 ps
CPU time	27.85 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:42 PM PST 24
Peak memory	231560 kb
Host	smart-f5893b47-40b2-4da9-abf8-5b5a19756421
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133078461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_extreme_fifo_size.2133078461
Directory	/workspace/46.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/46.spi_device_fifo_full.1150042333
Short name	T1001
Test name
Test status
Simulation time	216705678083 ps
CPU time	754.72 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:37:49 PM PST 24
Peak memory	290336 kb
Host	smart-b46da986-413e-4c27-997e-1e76a1be97c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150042333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_full.1150042333
Directory	/workspace/46.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/46.spi_device_fifo_underflow_overflow.2567547143
Short name	T1305
Test name
Test status
Simulation time	109197800923 ps
CPU time	393.78 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:31:50 PM PST 24
Peak memory	474656 kb
Host	smart-d3be0137-5449-4754-8835-08aa15526861
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567547143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_fifo_underflow_overf low.2567547143
Directory	/workspace/46.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/46.spi_device_flash_all.2955070702
Short name	T308
Test name
Test status
Simulation time	63071747610 ps
CPU time	143.2 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:27:40 PM PST 24
Peak memory	270556 kb
Host	smart-4b02c7f6-0a6b-44a1-81ee-aa8da31267a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955070702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2955070702
Directory	/workspace/46.spi_device_flash_all/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm.2173080217
Short name	T796
Test name
Test status
Simulation time	35795413972 ps
CPU time	326.39 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:30:47 PM PST 24
Peak memory	273496 kb
Host	smart-be774014-20d9-4079-aa68-3facb2135ed2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173080217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2173080217
Directory	/workspace/46.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.832079273
Short name	T215
Test name
Test status
Simulation time	213355256590 ps
CPU time	500.82 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:33:34 PM PST 24
Peak memory	274076 kb
Host	smart-1036e7b1-c922-4cb8-80bb-8d0c27b4f3f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832079273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle .832079273
Directory	/workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/46.spi_device_flash_mode.3096303642
Short name	T1371
Test name
Test status
Simulation time	39813274781 ps
CPU time	26.05 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:42 PM PST 24
Peak memory	240940 kb
Host	smart-e33b80c1-34a8-4b35-b5de-5bef4804be26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096303642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3096303642
Directory	/workspace/46.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/46.spi_device_intercept.3233158739
Short name	T287
Test name
Test status
Simulation time	671959721 ps
CPU time	6.89 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:24 PM PST 24
Peak memory	225060 kb
Host	smart-34bc2b11-ecaf-4e2e-b94d-698a31555c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233158739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3233158739
Directory	/workspace/46.spi_device_intercept/latest

Test location	/workspace/coverage/default/46.spi_device_intr.651377158
Short name	T846
Test name
Test status
Simulation time	14670937212 ps
CPU time	21.19 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:34 PM PST 24
Peak memory	224460 kb
Host	smart-f1901cc3-7992-4bda-8729-7faf7b085241
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651377158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intr.651377158
Directory	/workspace/46.spi_device_intr/latest

Test location	/workspace/coverage/default/46.spi_device_mailbox.1286520317
Short name	T1628
Test name
Test status
Simulation time	70657085117 ps
CPU time	17.18 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:36 PM PST 24
Peak memory	233256 kb
Host	smart-577d3df7-189a-4846-9a6d-20361df65a31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286520317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1286520317
Directory	/workspace/46.spi_device_mailbox/latest

Test location	/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2435017382
Short name	T95
Test name
Test status
Simulation time	3999160715 ps
CPU time	8.76 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	238248 kb
Host	smart-59d3eb65-c11c-4800-a098-b4890d4e2308
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435017382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa p.2435017382
Directory	/workspace/46.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/46.spi_device_pass_cmd_filtering.203075795
Short name	T1621
Test name
Test status
Simulation time	7508287181 ps
CPU time	23.01 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:38 PM PST 24
Peak memory	219604 kb
Host	smart-f0466a42-3b60-4733-bb19-397cd361908c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203075795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.203075795
Directory	/workspace/46.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/46.spi_device_perf.734186014
Short name	T1704
Test name
Test status
Simulation time	23471370953 ps
CPU time	273.1 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:29:46 PM PST 24
Peak memory	273936 kb
Host	smart-3804f65c-1a40-4548-802c-f165bba668c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734186014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_perf.734186014
Directory	/workspace/46.spi_device_perf/latest

Test location	/workspace/coverage/default/46.spi_device_read_buffer_direct.325578551
Short name	T842
Test name
Test status
Simulation time	847208629 ps
CPU time	3.7 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	234528 kb
Host	smart-6241335f-ca45-4195-823d-73a1c99cf4a1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=325578551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire ct.325578551
Directory	/workspace/46.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/46.spi_device_rx_async_fifo_reset.3417814504
Short name	T1230
Test name
Test status
Simulation time	39760384 ps
CPU time	0.9 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	208440 kb
Host	smart-19ce2c58-3e9c-4540-8111-39e52b204081
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417814504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_async_fifo_reset.3417814504
Directory	/workspace/46.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/46.spi_device_rx_timeout.345164911
Short name	T960
Test name
Test status
Simulation time	946002983 ps
CPU time	6.96 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	216824 kb
Host	smart-324b7c23-c3b2-44dc-905e-8bd45b90aead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345164911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_rx_timeout.345164911
Directory	/workspace/46.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/46.spi_device_smoke.449353707
Short name	T1466
Test name
Test status
Simulation time	17411574 ps
CPU time	1.07 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	208068 kb
Host	smart-76fee3fb-f7ed-4ec5-ba7e-f672d169bbdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449353707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_smoke.449353707
Directory	/workspace/46.spi_device_smoke/latest

Test location	/workspace/coverage/default/46.spi_device_stress_all.3438961409
Short name	T558
Test name
Test status
Simulation time	83960608045 ps
CPU time	1085.28 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:43:26 PM PST 24
Peak memory	538632 kb
Host	smart-76eebe20-000e-4013-8bb9-eae397688855
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438961409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre ss_all.3438961409
Directory	/workspace/46.spi_device_stress_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_all.264651942
Short name	T568
Test name
Test status
Simulation time	12891868386 ps
CPU time	30.09 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:43 PM PST 24
Peak memory	217060 kb
Host	smart-6f11a236-6aa8-4a45-b49f-d984d1b7f103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264651942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.264651942
Directory	/workspace/46.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3848532698
Short name	T1096
Test name
Test status
Simulation time	485217186 ps
CPU time	1.82 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	208216 kb
Host	smart-d48ad0d8-3362-4ca9-962e-7bdc46be4ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848532698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3848532698
Directory	/workspace/46.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_rw.182466850
Short name	T858
Test name
Test status
Simulation time	243335273 ps
CPU time	1.04 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	207420 kb
Host	smart-b7f5ff44-5541-44bc-82cb-b3db3e2facc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182466850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.182466850
Directory	/workspace/46.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_sts_read.3365408642
Short name	T700
Test name
Test status
Simulation time	172545709 ps
CPU time	0.87 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	206812 kb
Host	smart-46fddb90-58fb-4020-b619-b36d26eed2df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365408642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3365408642
Directory	/workspace/46.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/46.spi_device_tx_async_fifo_reset.2421785349
Short name	T1168
Test name
Test status
Simulation time	27660575 ps
CPU time	0.76 seconds
Started	Jan 07 01:25:00 PM PST 24
Finished	Jan 07 01:25:13 PM PST 24
Peak memory	208408 kb
Host	smart-148d28af-fb85-48b4-8e7b-3673b2e60d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421785349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tx_async_fifo_reset.2421785349
Directory	/workspace/46.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/46.spi_device_txrx.3084097127
Short name	T1539
Test name
Test status
Simulation time	42573603051 ps
CPU time	371.62 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:31:30 PM PST 24
Peak memory	257344 kb
Host	smart-effb30b7-f98f-4386-a4ca-7c5bd3d2114f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084097127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_txrx.3084097127
Directory	/workspace/46.spi_device_txrx/latest

Test location	/workspace/coverage/default/46.spi_device_upload.1577104489
Short name	T239
Test name
Test status
Simulation time	6986144341 ps
CPU time	14.96 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:32 PM PST 24
Peak memory	246512 kb
Host	smart-f35d80de-4eb3-4754-a3b2-7a504c296a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577104489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1577104489
Directory	/workspace/46.spi_device_upload/latest

Test location	/workspace/coverage/default/47.spi_device_abort.2323431002
Short name	T1019
Test name
Test status
Simulation time	14636977 ps
CPU time	0.76 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	206616 kb
Host	smart-99761523-147a-46e3-a71b-af1948f1732b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323431002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_abort.2323431002
Directory	/workspace/47.spi_device_abort/latest

Test location	/workspace/coverage/default/47.spi_device_alert_test.2227388373
Short name	T681
Test name
Test status
Simulation time	12660318 ps
CPU time	0.71 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	206540 kb
Host	smart-99f5e7f6-6a68-4046-9418-19d966bfe62a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227388373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test. 2227388373
Directory	/workspace/47.spi_device_alert_test/latest

Test location	/workspace/coverage/default/47.spi_device_bit_transfer.191402586
Short name	T1751
Test name
Test status
Simulation time	1274309237 ps
CPU time	2.91 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	216720 kb
Host	smart-6edfe0a8-56a2-4cd1-8c86-c2d963443789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191402586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_bit_transfer.191402586
Directory	/workspace/47.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/47.spi_device_byte_transfer.1205355415
Short name	T1164
Test name
Test status
Simulation time	108404588 ps
CPU time	2.6 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	216908 kb
Host	smart-5b367fb5-ed4c-49ce-895f-6c55401e8ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205355415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_byte_transfer.1205355415
Directory	/workspace/47.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/47.spi_device_cfg_cmd.1876725938
Short name	T1107
Test name
Test status
Simulation time	193846560 ps
CPU time	2.17 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	218492 kb
Host	smart-9848d7be-83b4-41d6-91b0-ec571c9694b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876725938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1876725938
Directory	/workspace/47.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/47.spi_device_csb_read.3698044201
Short name	T35
Test name
Test status
Simulation time	49546473 ps
CPU time	0.74 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	206520 kb
Host	smart-263baf5c-6e1e-4e1c-8192-ec6fb15bc356
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698044201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3698044201
Directory	/workspace/47.spi_device_csb_read/latest

Test location	/workspace/coverage/default/47.spi_device_dummy_item_extra_dly.3270972537
Short name	T1379
Test name
Test status
Simulation time	132726986986 ps
CPU time	400.58 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:31:56 PM PST 24
Peak memory	282168 kb
Host	smart-067473a9-64de-4ff3-8b28-3e8b1cb27cca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270972537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_dummy_item_extra_dly.3270972537
Directory	/workspace/47.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/47.spi_device_extreme_fifo_size.1764196571
Short name	T646
Test name
Test status
Simulation time	13311910548 ps
CPU time	26.79 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:42 PM PST 24
Peak memory	231376 kb
Host	smart-c8e0d727-a9d3-489c-a334-d2a52dd23c6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764196571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_extreme_fifo_size.1764196571
Directory	/workspace/47.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/47.spi_device_fifo_full.2787091647
Short name	T940
Test name
Test status
Simulation time	60682891046 ps
CPU time	1288.53 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:46:42 PM PST 24
Peak memory	273216 kb
Host	smart-5bd08d3b-90c0-4fbf-b666-2e4649d707a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2787091647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_full.2787091647
Directory	/workspace/47.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/47.spi_device_fifo_underflow_overflow.1339675875
Short name	T1694
Test name
Test status
Simulation time	135020017509 ps
CPU time	296.15 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:30:17 PM PST 24
Peak memory	402236 kb
Host	smart-694502f8-52a2-4ecf-9173-79453d4be329
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1339675875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_fifo_underflow_overf low.1339675875
Directory	/workspace/47.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/47.spi_device_flash_all.1647385101
Short name	T321
Test name
Test status
Simulation time	7157585777 ps
CPU time	26.41 seconds
Started	Jan 07 01:25:10 PM PST 24
Finished	Jan 07 01:25:48 PM PST 24
Peak memory	249728 kb
Host	smart-4d618fcd-774d-484f-8482-e09129b8687e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647385101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1647385101
Directory	/workspace/47.spi_device_flash_all/latest

Test location	/workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2475349791
Short name	T1286
Test name
Test status
Simulation time	2889744663 ps
CPU time	33.58 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:53 PM PST 24
Peak memory	251192 kb
Host	smart-a64aec7f-d503-4869-941e-f44d4ad2d3b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475349791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl e.2475349791
Directory	/workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/47.spi_device_flash_mode.1728065325
Short name	T166
Test name
Test status
Simulation time	404351132 ps
CPU time	9.01 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:25:31 PM PST 24
Peak memory	234516 kb
Host	smart-516bcdcc-810f-4f45-9b54-43c128e7f924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728065325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1728065325
Directory	/workspace/47.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/47.spi_device_intercept.1045168192
Short name	T1218
Test name
Test status
Simulation time	348153446 ps
CPU time	5.08 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:24 PM PST 24
Peak memory	224988 kb
Host	smart-5c64ea7f-dc7d-4b61-9e42-18a31d0e5e4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045168192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1045168192
Directory	/workspace/47.spi_device_intercept/latest

Test location	/workspace/coverage/default/47.spi_device_intr.2568883118
Short name	T987
Test name
Test status
Simulation time	3921983685 ps
CPU time	19.15 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:39 PM PST 24
Peak memory	224996 kb
Host	smart-df2de19f-88ac-4d0b-be73-fb9a75a4c859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568883118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intr.2568883118
Directory	/workspace/47.spi_device_intr/latest

Test location	/workspace/coverage/default/47.spi_device_mailbox.4208590489
Short name	T460
Test name
Test status
Simulation time	22293795945 ps
CPU time	23.8 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:40 PM PST 24
Peak memory	249804 kb
Host	smart-fc6d93ca-3fa1-4706-9ceb-6930eead5627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208590489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4208590489
Directory	/workspace/47.spi_device_mailbox/latest

Test location	/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3407926752
Short name	T16
Test name
Test status
Simulation time	4423307395 ps
CPU time	14.49 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:29 PM PST 24
Peak memory	227296 kb
Host	smart-66c172d4-98f2-4915-8ba5-905f17d443ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407926752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa p.3407926752
Directory	/workspace/47.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/47.spi_device_pass_cmd_filtering.2393498336
Short name	T1039
Test name
Test status
Simulation time	1970046227 ps
CPU time	6.98 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	218876 kb
Host	smart-b8e7888b-d5f0-4dca-ae17-e7233226ade9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393498336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2393498336
Directory	/workspace/47.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/47.spi_device_perf.1757869964
Short name	T563
Test name
Test status
Simulation time	66888982340 ps
CPU time	2657.83 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 02:09:36 PM PST 24
Peak memory	289700 kb
Host	smart-347b1da5-1215-4920-8176-a0241eb55dd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757869964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_perf.1757869964
Directory	/workspace/47.spi_device_perf/latest

Test location	/workspace/coverage/default/47.spi_device_read_buffer_direct.1094619397
Short name	T864
Test name
Test status
Simulation time	2352416605 ps
CPU time	5.44 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	236468 kb
Host	smart-1ccaac34-b1e6-4fd8-a63b-701a8ff1d133
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1094619397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir ect.1094619397
Directory	/workspace/47.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/47.spi_device_rx_async_fifo_reset.1105653566
Short name	T1744
Test name
Test status
Simulation time	30811891 ps
CPU time	0.88 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:17 PM PST 24
Peak memory	208540 kb
Host	smart-428c873b-74ca-4b81-a0b2-05f6528ba860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105653566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_async_fifo_reset.1105653566
Directory	/workspace/47.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/47.spi_device_rx_timeout.1505893149
Short name	T892
Test name
Test status
Simulation time	1137790999 ps
CPU time	4.89 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:25 PM PST 24
Peak memory	216896 kb
Host	smart-9ab9c14d-a841-4884-8a16-cc7c43f41df6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505893149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_rx_timeout.1505893149
Directory	/workspace/47.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/47.spi_device_smoke.2641684950
Short name	T1279
Test name
Test status
Simulation time	20925310 ps
CPU time	1.12 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	216612 kb
Host	smart-b917a1e5-50ad-40e5-9e98-ad21733bd3f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641684950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_smoke.2641684950
Directory	/workspace/47.spi_device_smoke/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_all.2898621327
Short name	T561
Test name
Test status
Simulation time	94659959 ps
CPU time	2.44 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	217060 kb
Host	smart-f7bab533-3aa6-4751-a0b8-644c9a42c9b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898621327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2898621327
Directory	/workspace/47.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3390019603
Short name	T447
Test name
Test status
Simulation time	1765287624 ps
CPU time	11.26 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:28 PM PST 24
Peak memory	216820 kb
Host	smart-bd220946-e555-4abf-8c06-42f0ec5e65bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390019603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3390019603
Directory	/workspace/47.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_rw.359105898
Short name	T1729
Test name
Test status
Simulation time	991713965 ps
CPU time	2.29 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	216892 kb
Host	smart-8f30879e-0cf0-41cb-becb-affe8fe92fff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359105898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.359105898
Directory	/workspace/47.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_sts_read.1800005179
Short name	T1596
Test name
Test status
Simulation time	43881067 ps
CPU time	0.84 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:19 PM PST 24
Peak memory	206768 kb
Host	smart-88ba7c2d-2a9e-4ec6-912e-b84b657b0d02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800005179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1800005179
Directory	/workspace/47.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/47.spi_device_tx_async_fifo_reset.3172657501
Short name	T745
Test name
Test status
Simulation time	73187763 ps
CPU time	0.83 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	208400 kb
Host	smart-09dca968-0e79-4d01-be14-f6a3fd41f761
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172657501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tx_async_fifo_reset.3172657501
Directory	/workspace/47.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/47.spi_device_txrx.3094996867
Short name	T1236
Test name
Test status
Simulation time	21981728816 ps
CPU time	161.17 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:27:59 PM PST 24
Peak memory	286836 kb
Host	smart-b5a921e3-d189-4341-b68e-cc2f478eff73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094996867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_txrx.3094996867
Directory	/workspace/47.spi_device_txrx/latest

Test location	/workspace/coverage/default/47.spi_device_upload.91304938
Short name	T769
Test name
Test status
Simulation time	27168061108 ps
CPU time	21.41 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:41 PM PST 24
Peak memory	249524 kb
Host	smart-61ccf622-ce0b-48d9-b58e-b4201e81084f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91304938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.91304938
Directory	/workspace/47.spi_device_upload/latest

Test location	/workspace/coverage/default/48.spi_device_abort.799486240
Short name	T1021
Test name
Test status
Simulation time	25545735 ps
CPU time	0.8 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	206672 kb
Host	smart-abcd96f3-3bf4-4a1c-8b43-aabb0dcc3e41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799486240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_abort.799486240
Directory	/workspace/48.spi_device_abort/latest

Test location	/workspace/coverage/default/48.spi_device_alert_test.4162915683
Short name	T1040
Test name
Test status
Simulation time	15664221 ps
CPU time	0.72 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:25:17 PM PST 24
Peak memory	206432 kb
Host	smart-4306e011-701d-4323-946e-eebe55ec16c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162915683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test. 4162915683
Directory	/workspace/48.spi_device_alert_test/latest

Test location	/workspace/coverage/default/48.spi_device_bit_transfer.758214465
Short name	T1490
Test name
Test status
Simulation time	374791075 ps
CPU time	2.58 seconds
Started	Jan 07 01:25:14 PM PST 24
Finished	Jan 07 01:25:25 PM PST 24
Peak memory	216756 kb
Host	smart-88756dec-b826-4f13-9c1d-6166b9f614bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=758214465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_bit_transfer.758214465
Directory	/workspace/48.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/48.spi_device_byte_transfer.1093867364
Short name	T1091
Test name
Test status
Simulation time	449887987 ps
CPU time	2.6 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:23 PM PST 24
Peak memory	216792 kb
Host	smart-7260ec31-c381-409e-9bae-bccb97b7308d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093867364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_byte_transfer.1093867364
Directory	/workspace/48.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/48.spi_device_cfg_cmd.2799054508
Short name	T844
Test name
Test status
Simulation time	2124516870 ps
CPU time	6.4 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:27 PM PST 24
Peak memory	219176 kb
Host	smart-bdea6356-7266-40d4-8fbd-42ff22055a0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799054508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2799054508
Directory	/workspace/48.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/48.spi_device_csb_read.1805851298
Short name	T859
Test name
Test status
Simulation time	69811426 ps
CPU time	0.79 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	207544 kb
Host	smart-93cb7b8d-7513-40cd-ba06-255dea9acab0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805851298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1805851298
Directory	/workspace/48.spi_device_csb_read/latest

Test location	/workspace/coverage/default/48.spi_device_dummy_item_extra_dly.228827578
Short name	T1578
Test name
Test status
Simulation time	178244662767 ps
CPU time	703.26 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:37:05 PM PST 24
Peak memory	248084 kb
Host	smart-18740e80-66b1-4fc8-a623-17676d7bd8d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228827578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_dummy_item_extra_dly.228827578
Directory	/workspace/48.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/48.spi_device_extreme_fifo_size.629281165
Short name	T63
Test name
Test status
Simulation time	8174989715 ps
CPU time	19.77 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:25:42 PM PST 24
Peak memory	222320 kb
Host	smart-eec7c287-90b8-4239-bc5c-4e2ebf11e513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629281165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_extreme_fifo_size.629281165
Directory	/workspace/48.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/48.spi_device_fifo_full.2724551439
Short name	T446
Test name
Test status
Simulation time	17728944571 ps
CPU time	916.3 seconds
Started	Jan 07 01:25:10 PM PST 24
Finished	Jan 07 01:40:38 PM PST 24
Peak memory	277320 kb
Host	smart-72657716-ac53-49f1-8bfc-639df4fb03d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724551439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_full.2724551439
Directory	/workspace/48.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/48.spi_device_fifo_underflow_overflow.2602676529
Short name	T1384
Test name
Test status
Simulation time	129341446315 ps
CPU time	826.46 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:39:07 PM PST 24
Peak memory	534024 kb
Host	smart-aa3ba576-9592-4f03-b96b-36e1802dea86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602676529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_fifo_underflow_overf low.2602676529
Directory	/workspace/48.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/48.spi_device_flash_all.1369951009
Short name	T222
Test name
Test status
Simulation time	103597120694 ps
CPU time	459.29 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:32:53 PM PST 24
Peak memory	273360 kb
Host	smart-32ee7686-a98e-4319-a8fb-981bb17c719c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369951009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1369951009
Directory	/workspace/48.spi_device_flash_all/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm.4140343272
Short name	T322
Test name
Test status
Simulation time	119765948322 ps
CPU time	415.09 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:32:13 PM PST 24
Peak memory	266160 kb
Host	smart-0f7e5a34-fdd0-4dc0-b2e9-68f422b026a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140343272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4140343272
Directory	/workspace/48.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/48.spi_device_flash_mode.2255173673
Short name	T1532
Test name
Test status
Simulation time	2666407153 ps
CPU time	14.34 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:32 PM PST 24
Peak memory	257768 kb
Host	smart-2464956a-f756-4e8a-a328-7536b268b1e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255173673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2255173673
Directory	/workspace/48.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/48.spi_device_intercept.4282435680
Short name	T1034
Test name
Test status
Simulation time	3198899820 ps
CPU time	12.02 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:32 PM PST 24
Peak memory	241388 kb
Host	smart-f319fab4-a2cd-42a9-9e78-2d813e98ca70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282435680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4282435680
Directory	/workspace/48.spi_device_intercept/latest

Test location	/workspace/coverage/default/48.spi_device_intr.3928908527
Short name	T1449
Test name
Test status
Simulation time	20232027070 ps
CPU time	27.13 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:25:49 PM PST 24
Peak memory	220684 kb
Host	smart-6616aef0-bde5-45fc-97e9-86a3770dc258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928908527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intr.3928908527
Directory	/workspace/48.spi_device_intr/latest

Test location	/workspace/coverage/default/48.spi_device_mailbox.1277890713
Short name	T1425
Test name
Test status
Simulation time	26214327549 ps
CPU time	10.99 seconds
Started	Jan 07 01:25:06 PM PST 24
Finished	Jan 07 01:25:28 PM PST 24
Peak memory	227128 kb
Host	smart-03d1da26-2101-4611-8f22-0ddad1d7fa1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277890713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1277890713
Directory	/workspace/48.spi_device_mailbox/latest

Test location	/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3734755474
Short name	T25
Test name
Test status
Simulation time	3102930468 ps
CPU time	11.27 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:26 PM PST 24
Peak memory	220944 kb
Host	smart-dd0c5501-1243-480a-bd52-c2f16528be55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734755474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa p.3734755474
Directory	/workspace/48.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/48.spi_device_pass_cmd_filtering.1411083256
Short name	T252
Test name
Test status
Simulation time	663096787 ps
CPU time	10.06 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:25:31 PM PST 24
Peak memory	239568 kb
Host	smart-da04351d-9a1f-458b-8592-1ec241af6f98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411083256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1411083256
Directory	/workspace/48.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/48.spi_device_perf.4062902572
Short name	T998
Test name
Test status
Simulation time	55573264349 ps
CPU time	455.33 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:32:55 PM PST 24
Peak memory	241536 kb
Host	smart-ae7ae1ea-9304-4858-97b4-d7144343b5a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062902572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_perf.4062902572
Directory	/workspace/48.spi_device_perf/latest

Test location	/workspace/coverage/default/48.spi_device_read_buffer_direct.1228456427
Short name	T1390
Test name
Test status
Simulation time	1123903477 ps
CPU time	6.27 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:24 PM PST 24
Peak memory	219892 kb
Host	smart-1ee6e3e8-6c03-43db-8bca-f494053c8ad8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1228456427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir ect.1228456427
Directory	/workspace/48.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/48.spi_device_rx_async_fifo_reset.208303968
Short name	T594
Test name
Test status
Simulation time	36167275 ps
CPU time	0.92 seconds
Started	Jan 07 01:25:02 PM PST 24
Finished	Jan 07 01:25:15 PM PST 24
Peak memory	208420 kb
Host	smart-e5760a29-d54a-4381-9d5e-275ec45caa6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208303968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_async_fifo_reset.208303968
Directory	/workspace/48.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/48.spi_device_rx_timeout.288118537
Short name	T531
Test name
Test status
Simulation time	528698682 ps
CPU time	5.37 seconds
Started	Jan 07 01:25:14 PM PST 24
Finished	Jan 07 01:25:28 PM PST 24
Peak memory	216920 kb
Host	smart-674f7354-b34e-47bf-8440-abb9b87fd0c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288118537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_rx_timeout.288118537
Directory	/workspace/48.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/48.spi_device_smoke.4141744622
Short name	T613
Test name
Test status
Simulation time	305252057 ps
CPU time	1.23 seconds
Started	Jan 07 01:25:03 PM PST 24
Finished	Jan 07 01:25:16 PM PST 24
Peak memory	216748 kb
Host	smart-36ccf973-20b6-4152-a903-9f32454d9bb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141744622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_smoke.4141744622
Directory	/workspace/48.spi_device_smoke/latest

Test location	/workspace/coverage/default/48.spi_device_stress_all.4236950994
Short name	T254
Test name
Test status
Simulation time	78846741055 ps
CPU time	596.9 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:35:17 PM PST 24
Peak memory	313244 kb
Host	smart-e55e64c0-5f23-4698-9c6a-94f7d6aa48e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236950994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre ss_all.4236950994
Directory	/workspace/48.spi_device_stress_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_all.127611378
Short name	T1212
Test name
Test status
Simulation time	17525829506 ps
CPU time	64.78 seconds
Started	Jan 07 01:25:14 PM PST 24
Finished	Jan 07 01:26:27 PM PST 24
Peak memory	216984 kb
Host	smart-245d9cd9-d999-4a2d-8731-36768abea144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127611378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.127611378
Directory	/workspace/48.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3591514136
Short name	T500
Test name
Test status
Simulation time	13743111852 ps
CPU time	8.78 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:25:31 PM PST 24
Peak memory	216888 kb
Host	smart-08733b77-8ab6-4e8a-abf9-342feed278e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591514136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3591514136
Directory	/workspace/48.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_rw.3933165322
Short name	T1629
Test name
Test status
Simulation time	20452227 ps
CPU time	1.23 seconds
Started	Jan 07 01:25:01 PM PST 24
Finished	Jan 07 01:25:14 PM PST 24
Peak memory	216784 kb
Host	smart-90476f52-6f35-497c-95bc-a463e866e62a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933165322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3933165322
Directory	/workspace/48.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_sts_read.537101483
Short name	T1380
Test name
Test status
Simulation time	43067498 ps
CPU time	0.87 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:21 PM PST 24
Peak memory	206836 kb
Host	smart-ac447900-bb68-44e8-b8ba-8b2b2a477e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537101483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.537101483
Directory	/workspace/48.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/48.spi_device_tx_async_fifo_reset.614430469
Short name	T1393
Test name
Test status
Simulation time	16090535 ps
CPU time	0.79 seconds
Started	Jan 07 01:25:05 PM PST 24
Finished	Jan 07 01:25:17 PM PST 24
Peak memory	208428 kb
Host	smart-fa627ab3-080c-4dce-b6ab-abb811b674ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614430469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tx_async_fifo_reset.614430469
Directory	/workspace/48.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/48.spi_device_txrx.3548563618
Short name	T1070
Test name
Test status
Simulation time	25231339963 ps
CPU time	204.5 seconds
Started	Jan 07 01:25:09 PM PST 24
Finished	Jan 07 01:28:45 PM PST 24
Peak memory	249508 kb
Host	smart-bc0d60a5-89fc-4668-b473-b0ca371a0ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548563618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_txrx.3548563618
Directory	/workspace/48.spi_device_txrx/latest

Test location	/workspace/coverage/default/48.spi_device_upload.87888956
Short name	T1402
Test name
Test status
Simulation time	680324002 ps
CPU time	4.72 seconds
Started	Jan 07 01:25:08 PM PST 24
Finished	Jan 07 01:25:25 PM PST 24
Peak memory	224552 kb
Host	smart-297baac8-a520-4909-b0a8-8d5a1e245177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87888956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.87888956
Directory	/workspace/48.spi_device_upload/latest

Test location	/workspace/coverage/default/49.spi_device_abort.2156606723
Short name	T1276
Test name
Test status
Simulation time	69203122 ps
CPU time	0.79 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:25:48 PM PST 24
Peak memory	206696 kb
Host	smart-ef5440dc-5d6a-42df-bc04-cd41ff41e023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156606723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_abort.2156606723
Directory	/workspace/49.spi_device_abort/latest

Test location	/workspace/coverage/default/49.spi_device_alert_test.1027184694
Short name	T1119
Test name
Test status
Simulation time	11058662 ps
CPU time	0.73 seconds
Started	Jan 07 01:25:29 PM PST 24
Finished	Jan 07 01:25:51 PM PST 24
Peak memory	206520 kb
Host	smart-4fcf3e08-3cc3-4992-8113-22ba1b860594
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027184694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test. 1027184694
Directory	/workspace/49.spi_device_alert_test/latest

Test location	/workspace/coverage/default/49.spi_device_bit_transfer.1790648995
Short name	T449
Test name
Test status
Simulation time	109651821 ps
CPU time	2.19 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:25:38 PM PST 24
Peak memory	216736 kb
Host	smart-5fe94ff6-0d13-4c6c-b667-bbbaaa9382cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790648995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_bit_transfer.1790648995
Directory	/workspace/49.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/49.spi_device_byte_transfer.1981332440
Short name	T61
Test name
Test status
Simulation time	262473905 ps
CPU time	3.51 seconds
Started	Jan 07 01:25:26 PM PST 24
Finished	Jan 07 01:25:40 PM PST 24
Peak memory	216860 kb
Host	smart-2842acd5-f1b6-4c6a-8a19-3f71bacb86be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981332440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_byte_transfer.1981332440
Directory	/workspace/49.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/49.spi_device_cfg_cmd.1818444825
Short name	T303
Test name
Test status
Simulation time	217969126 ps
CPU time	2.78 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:25:39 PM PST 24
Peak memory	240944 kb
Host	smart-07a8774d-7cab-47de-9c56-a59969542a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818444825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1818444825
Directory	/workspace/49.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/49.spi_device_csb_read.990434270
Short name	T547
Test name
Test status
Simulation time	21647730 ps
CPU time	0.8 seconds
Started	Jan 07 01:25:31 PM PST 24
Finished	Jan 07 01:25:53 PM PST 24
Peak memory	207488 kb
Host	smart-d8b1489e-6598-4785-9e98-e3b58c81dd92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990434270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.990434270
Directory	/workspace/49.spi_device_csb_read/latest

Test location	/workspace/coverage/default/49.spi_device_dummy_item_extra_dly.1329914893
Short name	T1414
Test name
Test status
Simulation time	115194922044 ps
CPU time	273.12 seconds
Started	Jan 07 01:25:38 PM PST 24
Finished	Jan 07 01:30:36 PM PST 24
Peak memory	289184 kb
Host	smart-e277d0bd-9ee6-4be7-a888-b3bab949d8d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329914893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_dummy_item_extra_dly.1329914893
Directory	/workspace/49.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/49.spi_device_extreme_fifo_size.3016310448
Short name	T200
Test name
Test status
Simulation time	18514848395 ps
CPU time	41.75 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:26:27 PM PST 24
Peak memory	240664 kb
Host	smart-f69e18f7-9544-4afc-be3c-2281ea8a1a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016310448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_extreme_fifo_size.3016310448
Directory	/workspace/49.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/49.spi_device_fifo_full.600410587
Short name	T1699
Test name
Test status
Simulation time	82713352252 ps
CPU time	1271.45 seconds
Started	Jan 07 01:25:13 PM PST 24
Finished	Jan 07 01:46:34 PM PST 24
Peak memory	273188 kb
Host	smart-8c0efd17-13a2-4228-8d36-96bb26ed2e4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600410587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_full.600410587
Directory	/workspace/49.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/49.spi_device_fifo_underflow_overflow.4065239421
Short name	T1139
Test name
Test status
Simulation time	100789377965 ps
CPU time	212.27 seconds
Started	Jan 07 01:25:07 PM PST 24
Finished	Jan 07 01:28:52 PM PST 24
Peak memory	342652 kb
Host	smart-f54fa79b-2503-4994-9305-e10a44f1872a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065239421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_fifo_underflow_overf low.4065239421
Directory	/workspace/49.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/49.spi_device_flash_all.2256366412
Short name	T505
Test name
Test status
Simulation time	9915655175 ps
CPU time	20.76 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:25:57 PM PST 24
Peak memory	249732 kb
Host	smart-7939195c-9bce-4ee6-bab7-eba4a9f19e12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256366412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2256366412
Directory	/workspace/49.spi_device_flash_all/latest

Test location	/workspace/coverage/default/49.spi_device_flash_and_tpm.2238976520
Short name	T297
Test name
Test status
Simulation time	5123463023 ps
CPU time	70.5 seconds
Started	Jan 07 01:25:30 PM PST 24
Finished	Jan 07 01:27:03 PM PST 24
Peak memory	229080 kb
Host	smart-3d28fb59-8361-48d0-9ff8-8a24f11b4f33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238976520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2238976520
Directory	/workspace/49.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/49.spi_device_flash_mode.3989952659
Short name	T1590
Test name
Test status
Simulation time	12090078696 ps
CPU time	18.81 seconds
Started	Jan 07 01:25:29 PM PST 24
Finished	Jan 07 01:26:13 PM PST 24
Peak memory	239752 kb
Host	smart-4c19ac49-87d2-484f-896c-56c344537385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989952659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3989952659
Directory	/workspace/49.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/49.spi_device_intercept.893065874
Short name	T688
Test name
Test status
Simulation time	3357100344 ps
CPU time	6.52 seconds
Started	Jan 07 01:25:26 PM PST 24
Finished	Jan 07 01:25:43 PM PST 24
Peak memory	236584 kb
Host	smart-41d68e0b-208f-4ad3-97d5-366c5015ac15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893065874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.893065874
Directory	/workspace/49.spi_device_intercept/latest

Test location	/workspace/coverage/default/49.spi_device_intr.2668760599
Short name	T991
Test name
Test status
Simulation time	11518493486 ps
CPU time	64.09 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:26:40 PM PST 24
Peak memory	241076 kb
Host	smart-d665333c-6a4b-40ae-968c-a2f3353994bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668760599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intr.2668760599
Directory	/workspace/49.spi_device_intr/latest

Test location	/workspace/coverage/default/49.spi_device_mailbox.875328001
Short name	T277
Test name
Test status
Simulation time	1867340900 ps
CPU time	7.84 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:25:57 PM PST 24
Peak memory	249000 kb
Host	smart-3a29cb2b-5cd3-4e30-91e8-c28ac1637e72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875328001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.875328001
Directory	/workspace/49.spi_device_mailbox/latest

Test location	/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1282398431
Short name	T1500
Test name
Test status
Simulation time	1328571471 ps
CPU time	7.03 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:25:57 PM PST 24
Peak memory	218744 kb
Host	smart-3288ff4f-cacd-49c3-b70f-ce7862b6ae90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282398431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa p.1282398431
Directory	/workspace/49.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/49.spi_device_pass_cmd_filtering.4042324030
Short name	T278
Test name
Test status
Simulation time	359899929 ps
CPU time	4.77 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:25:52 PM PST 24
Peak memory	248392 kb
Host	smart-7d45e7ea-a3a8-4cb0-b74f-bc767645ca5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042324030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4042324030
Directory	/workspace/49.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/49.spi_device_perf.1769190946
Short name	T1662
Test name
Test status
Simulation time	16673361096 ps
CPU time	297.38 seconds
Started	Jan 07 01:25:31 PM PST 24
Finished	Jan 07 01:30:50 PM PST 24
Peak memory	277408 kb
Host	smart-44442293-35e1-416a-a6ed-3fc1f12b19ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769190946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_perf.1769190946
Directory	/workspace/49.spi_device_perf/latest

Test location	/workspace/coverage/default/49.spi_device_read_buffer_direct.678002125
Short name	T825
Test name
Test status
Simulation time	536157092 ps
CPU time	4.45 seconds
Started	Jan 07 01:25:26 PM PST 24
Finished	Jan 07 01:25:41 PM PST 24
Peak memory	219724 kb
Host	smart-fd4c8f5d-1114-48ec-81f1-b7f33447bd06
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=678002125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire ct.678002125
Directory	/workspace/49.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/49.spi_device_rx_async_fifo_reset.1906267813
Short name	T925
Test name
Test status
Simulation time	16327064 ps
CPU time	0.85 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:25:37 PM PST 24
Peak memory	208464 kb
Host	smart-f25972a5-706c-4335-bdef-734d672d127e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906267813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_async_fifo_reset.1906267813
Directory	/workspace/49.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/49.spi_device_rx_timeout.1072413360
Short name	T1190
Test name
Test status
Simulation time	1480749763 ps
CPU time	5.12 seconds
Started	Jan 07 01:25:36 PM PST 24
Finished	Jan 07 01:26:03 PM PST 24
Peak memory	216880 kb
Host	smart-900ed789-e5b9-46e2-83e6-1d2062a87cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072413360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_rx_timeout.1072413360
Directory	/workspace/49.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/49.spi_device_smoke.160670708
Short name	T919
Test name
Test status
Simulation time	80930549 ps
CPU time	1.21 seconds
Started	Jan 07 01:25:10 PM PST 24
Finished	Jan 07 01:25:22 PM PST 24
Peak memory	216832 kb
Host	smart-23dddee4-4811-4b34-b655-50afcafe2e16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160670708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_smoke.160670708
Directory	/workspace/49.spi_device_smoke/latest

Test location	/workspace/coverage/default/49.spi_device_stress_all.1507644125
Short name	T1269
Test name
Test status
Simulation time	217408760107 ps
CPU time	598.46 seconds
Started	Jan 07 01:25:33 PM PST 24
Finished	Jan 07 01:35:53 PM PST 24
Peak memory	379904 kb
Host	smart-e7f99247-a66a-4a35-8a53-9935869bb8a9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507644125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre ss_all.1507644125
Directory	/workspace/49.spi_device_stress_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_all.4294489300
Short name	T751
Test name
Test status
Simulation time	1009382735 ps
CPU time	3.73 seconds
Started	Jan 07 01:25:25 PM PST 24
Finished	Jan 07 01:25:40 PM PST 24
Peak memory	219456 kb
Host	smart-1e04e9a3-975a-43dd-9c1a-1dca4697fc4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294489300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4294489300
Directory	/workspace/49.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3321630470
Short name	T966
Test name
Test status
Simulation time	1483991379 ps
CPU time	4.6 seconds
Started	Jan 07 01:25:38 PM PST 24
Finished	Jan 07 01:26:07 PM PST 24
Peak memory	216780 kb
Host	smart-540b0523-4bb5-4c11-9298-a5ff695f0f9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321630470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3321630470
Directory	/workspace/49.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_rw.1294217610
Short name	T1457
Test name
Test status
Simulation time	26241019 ps
CPU time	1.23 seconds
Started	Jan 07 01:25:24 PM PST 24
Finished	Jan 07 01:25:37 PM PST 24
Peak memory	216868 kb
Host	smart-be4a32b0-29f9-453d-8663-701f7ed1a113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294217610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1294217610
Directory	/workspace/49.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_sts_read.2460358707
Short name	T1195
Test name
Test status
Simulation time	81954108 ps
CPU time	0.73 seconds
Started	Jan 07 01:25:29 PM PST 24
Finished	Jan 07 01:25:52 PM PST 24
Peak memory	206800 kb
Host	smart-850d6312-be1c-4b2e-ab78-55a6e98c884e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460358707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2460358707
Directory	/workspace/49.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/49.spi_device_tx_async_fifo_reset.2187213365
Short name	T1516
Test name
Test status
Simulation time	18697447 ps
CPU time	0.77 seconds
Started	Jan 07 01:25:26 PM PST 24
Finished	Jan 07 01:25:37 PM PST 24
Peak memory	208484 kb
Host	smart-eaff868f-2bf5-487f-a7f8-ae60d3b79fae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187213365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tx_async_fifo_reset.2187213365
Directory	/workspace/49.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/49.spi_device_txrx.804304852
Short name	T1130
Test name
Test status
Simulation time	50028837793 ps
CPU time	428.75 seconds
Started	Jan 07 01:25:04 PM PST 24
Finished	Jan 07 01:32:25 PM PST 24
Peak memory	298952 kb
Host	smart-25879a7c-839e-43d7-982a-6ad200f2eec5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804304852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_txrx.804304852
Directory	/workspace/49.spi_device_txrx/latest

Test location	/workspace/coverage/default/49.spi_device_upload.2638515344
Short name	T1476
Test name
Test status
Simulation time	1159136466 ps
CPU time	10.65 seconds
Started	Jan 07 01:25:27 PM PST 24
Finished	Jan 07 01:26:00 PM PST 24
Peak memory	218824 kb
Host	smart-b0246acd-b1e1-4b77-8b5d-3ec3c96c6cd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638515344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2638515344
Directory	/workspace/49.spi_device_upload/latest

Test location	/workspace/coverage/default/5.spi_device_abort.2916213851
Short name	T699
Test name
Test status
Simulation time	16605588 ps
CPU time	0.73 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:19:17 PM PST 24
Peak memory	206648 kb
Host	smart-b92f207c-3590-47c5-b165-2a8452c41894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916213851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_abort.2916213851
Directory	/workspace/5.spi_device_abort/latest

Test location	/workspace/coverage/default/5.spi_device_alert_test.3394862565
Short name	T658
Test name
Test status
Simulation time	53076266 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:19:55 PM PST 24
Peak memory	206412 kb
Host	smart-e9c3bcfa-7df0-4cf3-85d1-4cb27f1d0d66
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394862565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3 394862565
Directory	/workspace/5.spi_device_alert_test/latest

Test location	/workspace/coverage/default/5.spi_device_bit_transfer.954083153
Short name	T1073
Test name
Test status
Simulation time	227620073 ps
CPU time	2.57 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:15 PM PST 24
Peak memory	216724 kb
Host	smart-83b0b4d0-a452-4318-b0fe-4edf64bbb9a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954083153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_bit_transfer.954083153
Directory	/workspace/5.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/5.spi_device_byte_transfer.2606630036
Short name	T429
Test name
Test status
Simulation time	269348704 ps
CPU time	3.22 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	216788 kb
Host	smart-b32934a7-f0a9-49d2-9bd9-773d83580cb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606630036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_byte_transfer.2606630036
Directory	/workspace/5.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/5.spi_device_cfg_cmd.402842592
Short name	T1189
Test name
Test status
Simulation time	7228121836 ps
CPU time	8.42 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:45 PM PST 24
Peak memory	220420 kb
Host	smart-2a98fe3b-c110-4bef-8737-7263d17e98cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402842592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.402842592
Directory	/workspace/5.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/5.spi_device_csb_read.862235449
Short name	T1514
Test name
Test status
Simulation time	20327362 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206520 kb
Host	smart-38bacf3b-0599-41f6-812a-43be8fee5fd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862235449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.862235449
Directory	/workspace/5.spi_device_csb_read/latest

Test location	/workspace/coverage/default/5.spi_device_dummy_item_extra_dly.2289622712
Short name	T471
Test name
Test status
Simulation time	23437084841 ps
CPU time	436.68 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:26:59 PM PST 24
Peak memory	251876 kb
Host	smart-6a715cf5-cd6a-482d-a37a-b9b66a86877c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289622712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_dummy_item_extra_dly.2289622712
Directory	/workspace/5.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/5.spi_device_extreme_fifo_size.1774079952
Short name	T814
Test name
Test status
Simulation time	207590240475 ps
CPU time	2361.03 seconds
Started	Jan 07 01:19:32 PM PST 24
Finished	Jan 07 01:58:57 PM PST 24
Peak memory	219096 kb
Host	smart-44ee179f-9272-4686-a509-ea2dce4df664
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774079952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_extreme_fifo_size.1774079952
Directory	/workspace/5.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/5.spi_device_fifo_full.1529572392
Short name	T1060
Test name
Test status
Simulation time	39028382466 ps
CPU time	445.16 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:26:53 PM PST 24
Peak memory	274312 kb
Host	smart-120a6d4f-bda5-4f83-a0e7-c526101419ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529572392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_full.1529572392
Directory	/workspace/5.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/5.spi_device_fifo_underflow_overflow.2672635363
Short name	T1619
Test name
Test status
Simulation time	17844399130 ps
CPU time	166.72 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:22:15 PM PST 24
Peak memory	306824 kb
Host	smart-1cee37b4-3004-422f-b67b-1d1618f778df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672635363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_fifo_underflow_overfl ow.2672635363
Directory	/workspace/5.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/5.spi_device_flash_all.1311191109
Short name	T1202
Test name
Test status
Simulation time	102208156664 ps
CPU time	113.65 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:21:47 PM PST 24
Peak memory	249792 kb
Host	smart-52d03710-48fd-47bb-b6df-5b94c08a4870
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311191109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1311191109
Directory	/workspace/5.spi_device_flash_all/latest

Test location	/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4024845445
Short name	T1521
Test name
Test status
Simulation time	3785439081 ps
CPU time	73.36 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:21:04 PM PST 24
Peak memory	249796 kb
Host	smart-08b8068f-2b43-47a4-bf68-6967f740eb91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024845445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle .4024845445
Directory	/workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/5.spi_device_flash_mode.2257523132
Short name	T746
Test name
Test status
Simulation time	8205842118 ps
CPU time	20.97 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:49 PM PST 24
Peak memory	233348 kb
Host	smart-368370c2-61d9-400e-8bb4-e3dfdc3020aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257523132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2257523132
Directory	/workspace/5.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/5.spi_device_intercept.1192800050
Short name	T922
Test name
Test status
Simulation time	605739714 ps
CPU time	6.45 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	239228 kb
Host	smart-468be2c7-6e91-494d-9885-2ce40976eb7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192800050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1192800050
Directory	/workspace/5.spi_device_intercept/latest

Test location	/workspace/coverage/default/5.spi_device_intr.4054486786
Short name	T1179
Test name
Test status
Simulation time	13835598364 ps
CPU time	14.63 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:19:39 PM PST 24
Peak memory	218204 kb
Host	smart-edb35fd4-dcfc-4a6d-8946-8a0a8edb0380
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054486786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intr.4054486786
Directory	/workspace/5.spi_device_intr/latest

Test location	/workspace/coverage/default/5.spi_device_mailbox.3615730972
Short name	T1311
Test name
Test status
Simulation time	22569884979 ps
CPU time	25.74 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:20:20 PM PST 24
Peak memory	236288 kb
Host	smart-9a5dc180-1e72-49c6-947a-4bd4cd0039c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615730972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3615730972
Directory	/workspace/5.spi_device_mailbox/latest

Test location	/workspace/coverage/default/5.spi_device_mem_parity.2580281280
Short name	T1329
Test name
Test status
Simulation time	50220618 ps
CPU time	1.03 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	218956 kb
Host	smart-5bc91124-a051-4101-ae1a-0d8631beace5
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580281280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.spi_device_mem_parity.2580281280
Directory	/workspace/5.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2270683681
Short name	T1507
Test name
Test status
Simulation time	28586384244 ps
CPU time	29.38 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:57 PM PST 24
Peak memory	240768 kb
Host	smart-455ab068-c5e0-479f-a128-b99e97d08cfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270683681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap .2270683681
Directory	/workspace/5.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/5.spi_device_pass_cmd_filtering.1405539820
Short name	T634
Test name
Test status
Simulation time	2047254052 ps
CPU time	2.94 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:53 PM PST 24
Peak memory	218764 kb
Host	smart-0b1acdb9-c044-4331-a492-cb26b3a6247e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405539820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1405539820
Directory	/workspace/5.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/5.spi_device_perf.135920593
Short name	T907
Test name
Test status
Simulation time	12581089647 ps
CPU time	773.94 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:32:31 PM PST 24
Peak memory	282904 kb
Host	smart-717af77c-3547-4f3f-b2d8-17f0db110a1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135920593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_perf.135920593
Directory	/workspace/5.spi_device_perf/latest

Test location	/workspace/coverage/default/5.spi_device_ram_cfg.1263781252
Short name	T1341
Test name
Test status
Simulation time	40779607 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:13 PM PST 24
Peak memory	216692 kb
Host	smart-ddaa0182-ea28-4b27-8bf6-0eac4e5dc747
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263781252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1263781252
Directory	/workspace/5.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/5.spi_device_read_buffer_direct.1281948043
Short name	T1312
Test name
Test status
Simulation time	674787600 ps
CPU time	4.37 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:19:59 PM PST 24
Peak memory	235348 kb
Host	smart-dcad3885-0f2f-4bc9-9146-92bceb83f22e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1281948043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire ct.1281948043
Directory	/workspace/5.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/5.spi_device_rx_async_fifo_reset.1058838413
Short name	T1610
Test name
Test status
Simulation time	44712958 ps
CPU time	0.93 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	208524 kb
Host	smart-1ec58116-2bfd-4eff-b002-8eb2520a8b7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058838413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_async_fifo_reset.1058838413
Directory	/workspace/5.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/5.spi_device_rx_timeout.3829087840
Short name	T108
Test name
Test status
Simulation time	2039994425 ps
CPU time	5.21 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:33 PM PST 24
Peak memory	216812 kb
Host	smart-fa01a03c-92ab-401b-adba-8954db5e4d4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829087840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_rx_timeout.3829087840
Directory	/workspace/5.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/5.spi_device_smoke.3972998266
Short name	T1165
Test name
Test status
Simulation time	131351911 ps
CPU time	1.16 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:14 PM PST 24
Peak memory	216600 kb
Host	smart-022d5a6f-9f5b-4d9b-a44e-19eca27da820
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972998266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_smoke.3972998266
Directory	/workspace/5.spi_device_smoke/latest

Test location	/workspace/coverage/default/5.spi_device_stress_all.766496138
Short name	T54
Test name
Test status
Simulation time	129933059029 ps
CPU time	2748 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 02:05:45 PM PST 24
Peak memory	473340 kb
Host	smart-48d579e4-ee0f-4b66-b287-7705a8048b30
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766496138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress _all.766496138
Directory	/workspace/5.spi_device_stress_all/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_all.3976273023
Short name	T1259
Test name
Test status
Simulation time	2780822268 ps
CPU time	15.89 seconds
Started	Jan 07 01:19:12 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	219848 kb
Host	smart-5fb28760-50a8-4be1-9185-a0525ea608e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976273023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3976273023
Directory	/workspace/5.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3451275565
Short name	T1579
Test name
Test status
Simulation time	875512438 ps
CPU time	7.35 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:35 PM PST 24
Peak memory	216876 kb
Host	smart-abc7cb10-8c70-48db-a93c-ae134dd9a8c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451275565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3451275565
Directory	/workspace/5.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_rw.837389869
Short name	T596
Test name
Test status
Simulation time	29009897 ps
CPU time	0.99 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	208356 kb
Host	smart-bdd23e44-c150-4948-8728-703c5349757f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837389869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.837389869
Directory	/workspace/5.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_sts_read.461223140
Short name	T106
Test name
Test status
Simulation time	90534088 ps
CPU time	0.92 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206896 kb
Host	smart-3957394c-e40b-4015-9042-393eac64d931
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461223140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.461223140
Directory	/workspace/5.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/5.spi_device_tx_async_fifo_reset.2101204455
Short name	T1616
Test name
Test status
Simulation time	47558494 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:19:25 PM PST 24
Peak memory	208452 kb
Host	smart-da9ef35a-b478-4111-83fc-735ff8e0e874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101204455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tx_async_fifo_reset.2101204455
Directory	/workspace/5.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/5.spi_device_txrx.2544005633
Short name	T1537
Test name
Test status
Simulation time	17311936129 ps
CPU time	193.73 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:22:42 PM PST 24
Peak memory	249668 kb
Host	smart-bd08e8ef-6145-4291-9c25-9b03bb4b813a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544005633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_txrx.2544005633
Directory	/workspace/5.spi_device_txrx/latest

Test location	/workspace/coverage/default/5.spi_device_upload.58135079
Short name	T1317
Test name
Test status
Simulation time	8039895321 ps
CPU time	13.98 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:42 PM PST 24
Peak memory	237604 kb
Host	smart-61192a99-155d-4e47-bd59-040c68e851cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58135079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.58135079
Directory	/workspace/5.spi_device_upload/latest

Test location	/workspace/coverage/default/6.spi_device_abort.3561162261
Short name	T467
Test name
Test status
Simulation time	22029144 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:00 PM PST 24
Peak memory	206580 kb
Host	smart-ba1d9b5e-8ae0-42c3-8c4d-36b0d7562f0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561162261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_abort.3561162261
Directory	/workspace/6.spi_device_abort/latest

Test location	/workspace/coverage/default/6.spi_device_alert_test.1517039961
Short name	T1419
Test name
Test status
Simulation time	48492929 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:43 PM PST 24
Peak memory	206436 kb
Host	smart-8a172ece-b674-48a1-8063-5e6d69c7215a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517039961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1 517039961
Directory	/workspace/6.spi_device_alert_test/latest

Test location	/workspace/coverage/default/6.spi_device_bit_transfer.261311009
Short name	T199
Test name
Test status
Simulation time	1022463737 ps
CPU time	2.81 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:03 PM PST 24
Peak memory	216776 kb
Host	smart-efa4776c-2cc5-4397-85ac-41fce2fadb3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=261311009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_bit_transfer.261311009
Directory	/workspace/6.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/6.spi_device_byte_transfer.2765829840
Short name	T1016
Test name
Test status
Simulation time	443714102 ps
CPU time	2.23 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:14 PM PST 24
Peak memory	216868 kb
Host	smart-257b2070-5380-4a1e-99f2-6aee8ab04eda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765829840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_byte_transfer.2765829840
Directory	/workspace/6.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/6.spi_device_cfg_cmd.729792966
Short name	T955
Test name
Test status
Simulation time	446102258 ps
CPU time	2.87 seconds
Started	Jan 07 01:19:11 PM PST 24
Finished	Jan 07 01:19:16 PM PST 24
Peak memory	218744 kb
Host	smart-70bf3b7a-1673-4581-9ce7-20a6cf6bc8d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729792966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.729792966
Directory	/workspace/6.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/6.spi_device_csb_read.2610380221
Short name	T973
Test name
Test status
Simulation time	40175805 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	206600 kb
Host	smart-401cb3cc-f7ca-44d8-8f31-9bad32583e80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610380221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2610380221
Directory	/workspace/6.spi_device_csb_read/latest

Test location	/workspace/coverage/default/6.spi_device_dummy_item_extra_dly.1404403505
Short name	T744
Test name
Test status
Simulation time	35171405712 ps
CPU time	788.34 seconds
Started	Jan 07 01:19:43 PM PST 24
Finished	Jan 07 01:33:05 PM PST 24
Peak memory	250760 kb
Host	smart-17f60034-dc0c-469c-ba0c-89ad6fd4f2b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404403505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_dummy_item_extra_dly.1404403505
Directory	/workspace/6.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/6.spi_device_extreme_fifo_size.3624689184
Short name	T1538
Test name
Test status
Simulation time	6357459574 ps
CPU time	61.3 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:20:59 PM PST 24
Peak memory	223080 kb
Host	smart-11347d2b-517a-4e01-9d28-37624a4dd58d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624689184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_extreme_fifo_size.3624689184
Directory	/workspace/6.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/6.spi_device_fifo_full.2320174334
Short name	T743
Test name
Test status
Simulation time	64763195708 ps
CPU time	1711.63 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:48:24 PM PST 24
Peak memory	283524 kb
Host	smart-9569e4d4-ed7e-4efe-9d0e-78cfd9c719ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320174334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_full.2320174334
Directory	/workspace/6.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/6.spi_device_fifo_underflow_overflow.1474705109
Short name	T180
Test name
Test status
Simulation time	60995426888 ps
CPU time	335.56 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:25:27 PM PST 24
Peak memory	380768 kb
Host	smart-fc2bce69-2b44-4a47-bdce-2681ffa57084
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474705109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_fifo_underflow_overfl ow.1474705109
Directory	/workspace/6.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/6.spi_device_flash_all.1927573562
Short name	T329
Test name
Test status
Simulation time	191622022297 ps
CPU time	245.56 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:23:34 PM PST 24
Peak memory	250680 kb
Host	smart-59a89fa6-edb6-4a88-90d8-261f1351648c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927573562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1927573562
Directory	/workspace/6.spi_device_flash_all/latest

Test location	/workspace/coverage/default/6.spi_device_flash_and_tpm.3388971888
Short name	T626
Test name
Test status
Simulation time	101126224655 ps
CPU time	156.42 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:22:14 PM PST 24
Peak memory	274396 kb
Host	smart-2362d6f7-62ae-497d-ac51-24b6081293cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388971888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3388971888
Directory	/workspace/6.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/6.spi_device_flash_mode.1075744685
Short name	T1067
Test name
Test status
Simulation time	1523922940 ps
CPU time	8.72 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:19:35 PM PST 24
Peak memory	224964 kb
Host	smart-db40012d-5122-4ecf-82e8-dfbdec4e695b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075744685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1075744685
Directory	/workspace/6.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/6.spi_device_intercept.2122622703
Short name	T1752
Test name
Test status
Simulation time	52938117 ps
CPU time	2.59 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:04 PM PST 24
Peak memory	218548 kb
Host	smart-c965d476-184a-4470-9e31-d06e58939043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122622703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2122622703
Directory	/workspace/6.spi_device_intercept/latest

Test location	/workspace/coverage/default/6.spi_device_intr.1469948993
Short name	T989
Test name
Test status
Simulation time	20407083903 ps
CPU time	45.35 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:20:37 PM PST 24
Peak memory	234384 kb
Host	smart-233ee129-628f-4bd5-9231-67f15616cd04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469948993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intr.1469948993
Directory	/workspace/6.spi_device_intr/latest

Test location	/workspace/coverage/default/6.spi_device_mailbox.3130097264
Short name	T698
Test name
Test status
Simulation time	42098497 ps
CPU time	2.97 seconds
Started	Jan 07 01:20:00 PM PST 24
Finished	Jan 07 01:20:14 PM PST 24
Peak memory	238264 kb
Host	smart-520a8cfe-4747-4983-b5a7-a9aee8edacca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130097264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3130097264
Directory	/workspace/6.spi_device_mailbox/latest

Test location	/workspace/coverage/default/6.spi_device_mem_parity.3088162209
Short name	T1252
Test name
Test status
Simulation time	14554689 ps
CPU time	1.01 seconds
Started	Jan 07 01:19:58 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	218880 kb
Host	smart-71a1f32e-9525-49b3-9191-aa25ba13535b
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088162209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.spi_device_mem_parity.3088162209
Directory	/workspace/6.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1481437400
Short name	T1633
Test name
Test status
Simulation time	4066185568 ps
CPU time	6.51 seconds
Started	Jan 07 01:19:50 PM PST 24
Finished	Jan 07 01:20:06 PM PST 24
Peak memory	218840 kb
Host	smart-46499977-1fb3-4f1c-bf13-7cfdf0650272
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481437400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .1481437400
Directory	/workspace/6.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_pass_cmd_filtering.1499087578
Short name	T1088
Test name
Test status
Simulation time	549298955 ps
CPU time	5.62 seconds
Started	Jan 07 01:19:48 PM PST 24
Finished	Jan 07 01:20:05 PM PST 24
Peak memory	249464 kb
Host	smart-25676b6a-1de3-4e28-9f4e-279eca77bcd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499087578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1499087578
Directory	/workspace/6.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/6.spi_device_perf.3922496835
Short name	T570
Test name
Test status
Simulation time	9041594819 ps
CPU time	536.29 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:28:54 PM PST 24
Peak memory	273508 kb
Host	smart-62e915ca-0736-4168-ac86-64bfddd785e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922496835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_perf.3922496835
Directory	/workspace/6.spi_device_perf/latest

Test location	/workspace/coverage/default/6.spi_device_ram_cfg.12931688
Short name	T909
Test name
Test status
Simulation time	19690193 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:59 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	216700 kb
Host	smart-a3b02d6e-70e2-436c-9ee5-4656c2017573
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12931688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.12931688
Directory	/workspace/6.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/6.spi_device_read_buffer_direct.2012043017
Short name	T686
Test name
Test status
Simulation time	350021578 ps
CPU time	4.67 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:33 PM PST 24
Peak memory	234364 kb
Host	smart-ee63b8ac-ff31-4fce-acf2-f8072240e04c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2012043017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire ct.2012043017
Directory	/workspace/6.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/6.spi_device_rx_async_fifo_reset.2009642275
Short name	T1062
Test name
Test status
Simulation time	76876678 ps
CPU time	0.87 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:08 PM PST 24
Peak memory	208328 kb
Host	smart-7504bb54-ae8a-4e4b-92e0-ec039b3dceb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009642275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_async_fifo_reset.2009642275
Directory	/workspace/6.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/6.spi_device_rx_timeout.3738911653
Short name	T996
Test name
Test status
Simulation time	991053332 ps
CPU time	5.77 seconds
Started	Jan 07 01:19:55 PM PST 24
Finished	Jan 07 01:20:13 PM PST 24
Peak memory	216912 kb
Host	smart-6e707963-a0e8-4229-9d61-30aa0852ff31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738911653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_rx_timeout.3738911653
Directory	/workspace/6.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/6.spi_device_smoke.616673723
Short name	T677
Test name
Test status
Simulation time	104164809 ps
CPU time	1.08 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	208196 kb
Host	smart-0bf425d4-0252-41a4-84db-a1b280e69f20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616673723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_smoke.616673723
Directory	/workspace/6.spi_device_smoke/latest

Test location	/workspace/coverage/default/6.spi_device_stress_all.3266384177
Short name	T125
Test name
Test status
Simulation time	528667498178 ps
CPU time	1478.68 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:44:16 PM PST 24
Peak memory	407108 kb
Host	smart-2b450ee2-c7fd-435c-a251-a44536bd1ce6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266384177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres s_all.3266384177
Directory	/workspace/6.spi_device_stress_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_all.2503598397
Short name	T910
Test name
Test status
Simulation time	83482395153 ps
CPU time	71.46 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:21:09 PM PST 24
Peak memory	216700 kb
Host	smart-785f6396-eb83-479f-bc30-fd7ef21090bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503598397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2503598397
Directory	/workspace/6.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4231751480
Short name	T1488
Test name
Test status
Simulation time	6185339091 ps
CPU time	18.84 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:31 PM PST 24
Peak memory	216824 kb
Host	smart-0e815d6d-e13a-4a4c-b611-b292d5722413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231751480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4231751480
Directory	/workspace/6.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_rw.1542155845
Short name	T349
Test name
Test status
Simulation time	861054296 ps
CPU time	4.92 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:20:17 PM PST 24
Peak memory	216832 kb
Host	smart-a90b2c7b-84de-4686-ba8e-ccfe469ceb40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1542155845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1542155845
Directory	/workspace/6.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_sts_read.3925956936
Short name	T495
Test name
Test status
Simulation time	167030009 ps
CPU time	0.9 seconds
Started	Jan 07 01:19:52 PM PST 24
Finished	Jan 07 01:20:04 PM PST 24
Peak memory	207836 kb
Host	smart-da13a88b-9cdd-46d9-b818-f295465a0a51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925956936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3925956936
Directory	/workspace/6.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/6.spi_device_tx_async_fifo_reset.1626712473
Short name	T610
Test name
Test status
Simulation time	17967827 ps
CPU time	0.79 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:07 PM PST 24
Peak memory	208496 kb
Host	smart-d72f3891-260c-46ad-8c93-5bf1cd3dad9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626712473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tx_async_fifo_reset.1626712473
Directory	/workspace/6.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/6.spi_device_txrx.2261637566
Short name	T439
Test name
Test status
Simulation time	79551177667 ps
CPU time	822.63 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:33:35 PM PST 24
Peak memory	283772 kb
Host	smart-be4ecb65-2518-4de0-b5b3-312e7741e4a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261637566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_txrx.2261637566
Directory	/workspace/6.spi_device_txrx/latest

Test location	/workspace/coverage/default/6.spi_device_upload.3274590049
Short name	T1270
Test name
Test status
Simulation time	3636550008 ps
CPU time	3.26 seconds
Started	Jan 07 01:19:54 PM PST 24
Finished	Jan 07 01:20:09 PM PST 24
Peak memory	217148 kb
Host	smart-60c59007-39dc-4250-b380-fe872a3b1f81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274590049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3274590049
Directory	/workspace/6.spi_device_upload/latest

Test location	/workspace/coverage/default/7.spi_device_abort.978511167
Short name	T1396
Test name
Test status
Simulation time	20803656 ps
CPU time	0.75 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206604 kb
Host	smart-bde8cf5c-65db-4171-a054-6b890120fd94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978511167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_abort.978511167
Directory	/workspace/7.spi_device_abort/latest

Test location	/workspace/coverage/default/7.spi_device_alert_test.2552658252
Short name	T1495
Test name
Test status
Simulation time	17836862 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	206324 kb
Host	smart-23077132-98d5-44d0-8bf9-6c1180cc8b25
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552658252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2 552658252
Directory	/workspace/7.spi_device_alert_test/latest

Test location	/workspace/coverage/default/7.spi_device_bit_transfer.1968566021
Short name	T887
Test name
Test status
Simulation time	87505876 ps
CPU time	2.5 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	216756 kb
Host	smart-980518c0-cad4-483b-8243-91c735a12e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968566021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_bit_transfer.1968566021
Directory	/workspace/7.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/7.spi_device_byte_transfer.1753172279
Short name	T655
Test name
Test status
Simulation time	61062095 ps
CPU time	2.43 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	216768 kb
Host	smart-87c742c5-0f76-407e-8c1a-11e411709434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753172279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_byte_transfer.1753172279
Directory	/workspace/7.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/7.spi_device_cfg_cmd.2279937122
Short name	T959
Test name
Test status
Simulation time	278014790 ps
CPU time	2.76 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:45 PM PST 24
Peak memory	225136 kb
Host	smart-bfcac531-20e0-42f7-9079-992466eb6018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279937122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2279937122
Directory	/workspace/7.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/7.spi_device_csb_read.725940414
Short name	T905
Test name
Test status
Simulation time	18239092 ps
CPU time	0.78 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:50 PM PST 24
Peak memory	206596 kb
Host	smart-c1a67e2e-4a3b-4fed-abe1-fd89a2df601b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725940414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.725940414
Directory	/workspace/7.spi_device_csb_read/latest

Test location	/workspace/coverage/default/7.spi_device_dummy_item_extra_dly.3429299981
Short name	T10
Test name
Test status
Simulation time	174622199166 ps
CPU time	653.1 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:30:45 PM PST 24
Peak memory	278772 kb
Host	smart-cf173e1f-edb5-4d25-aae8-a1cd71d52551
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429299981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_dummy_item_extra_dly.3429299981
Directory	/workspace/7.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/7.spi_device_extreme_fifo_size.3015856148
Short name	T1577
Test name
Test status
Simulation time	41821759666 ps
CPU time	2010.5 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:52:59 PM PST 24
Peak memory	217984 kb
Host	smart-679a5ea4-fb3f-4a77-b2ae-80260a929b7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015856148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_extreme_fifo_size.3015856148
Directory	/workspace/7.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/7.spi_device_fifo_full.397535079
Short name	T946
Test name
Test status
Simulation time	63422659319 ps
CPU time	956.8 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:35:25 PM PST 24
Peak memory	271428 kb
Host	smart-56d41067-c926-40da-81a9-1467894bdcee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397535079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_full.397535079
Directory	/workspace/7.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/7.spi_device_fifo_underflow_overflow.2100986150
Short name	T1113
Test name
Test status
Simulation time	64019587487 ps
CPU time	258.99 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:23:56 PM PST 24
Peak memory	356532 kb
Host	smart-a91a035b-66fe-4066-a2f5-b51ae15e8460
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100986150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_fifo_underflow_overfl ow.2100986150
Directory	/workspace/7.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/7.spi_device_flash_all.2583913271
Short name	T1657
Test name
Test status
Simulation time	5944248956 ps
CPU time	31.23 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:20:14 PM PST 24
Peak memory	241480 kb
Host	smart-1af14979-5783-4b0f-942a-43f21a964f42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583913271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2583913271
Directory	/workspace/7.spi_device_flash_all/latest

Test location	/workspace/coverage/default/7.spi_device_flash_and_tpm.1676678206
Short name	T1582
Test name
Test status
Simulation time	3094001706 ps
CPU time	50.82 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:20:34 PM PST 24
Peak memory	249808 kb
Host	smart-e6c9771e-d7ba-4610-a810-65f5be84f2e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676678206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1676678206
Directory	/workspace/7.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/7.spi_device_intercept.288994777
Short name	T204
Test name
Test status
Simulation time	861260385 ps
CPU time	3.46 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:32 PM PST 24
Peak memory	219248 kb
Host	smart-414a339d-dc01-4cac-b183-f03e5a929b8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288994777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.288994777
Directory	/workspace/7.spi_device_intercept/latest

Test location	/workspace/coverage/default/7.spi_device_intr.4052768594
Short name	T1256
Test name
Test status
Simulation time	9090678473 ps
CPU time	31.87 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:20:00 PM PST 24
Peak memory	219936 kb
Host	smart-a13bb816-069e-4c62-85f2-e6638b3903d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052768594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intr.4052768594
Directory	/workspace/7.spi_device_intr/latest

Test location	/workspace/coverage/default/7.spi_device_mailbox.1766606600
Short name	T578
Test name
Test status
Simulation time	42476642 ps
CPU time	2.98 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:46 PM PST 24
Peak memory	233308 kb
Host	smart-fdeb9b2d-8f37-4494-8c9f-7d7e3d03bb34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766606600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1766606600
Directory	/workspace/7.spi_device_mailbox/latest

Test location	/workspace/coverage/default/7.spi_device_mem_parity.79276831
Short name	T618
Test name
Test status
Simulation time	53886096 ps
CPU time	0.98 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	218780 kb
Host	smart-803cd0ac-f309-45ea-8dae-8c6b68ccf0d2
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79276831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.79276831
Directory	/workspace/7.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3285358340
Short name	T1110
Test name
Test status
Simulation time	3024082294 ps
CPU time	8.73 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:37 PM PST 24
Peak memory	220404 kb
Host	smart-ddc6fac3-5dea-4fe7-b14f-0a80daf0675f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285358340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap .3285358340
Directory	/workspace/7.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/7.spi_device_pass_cmd_filtering.1400475800
Short name	T5
Test name
Test status
Simulation time	402503085 ps
CPU time	4.67 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:33 PM PST 24
Peak memory	225116 kb
Host	smart-9b7d4b72-b492-42da-96b2-142093cf20e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400475800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1400475800
Directory	/workspace/7.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/7.spi_device_perf.1067931130
Short name	T857
Test name
Test status
Simulation time	7644432464 ps
CPU time	61.78 seconds
Started	Jan 07 01:19:18 PM PST 24
Finished	Jan 07 01:20:30 PM PST 24
Peak memory	257112 kb
Host	smart-d753f29a-d715-4612-b16a-073fd770c5f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067931130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_perf.1067931130
Directory	/workspace/7.spi_device_perf/latest

Test location	/workspace/coverage/default/7.spi_device_ram_cfg.2534769702
Short name	T85
Test name
Test status
Simulation time	47031662 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	216720 kb
Host	smart-90b8cbd9-b9fd-4fe9-911e-bf2af4fa17fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534769702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2534769702
Directory	/workspace/7.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/7.spi_device_read_buffer_direct.1383686742
Short name	T1669
Test name
Test status
Simulation time	4314228713 ps
CPU time	3.76 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:19:32 PM PST 24
Peak memory	218732 kb
Host	smart-5d55ef49-6481-47e4-9bcf-58abfcc285ff
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1383686742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire ct.1383686742
Directory	/workspace/7.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.2229482161
Short name	T1132
Test name
Test status
Simulation time	19627502 ps
CPU time	0.91 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	208444 kb
Host	smart-08673933-e49d-4b23-bda1-7d8e2fb51dd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229482161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_async_fifo_reset.2229482161
Directory	/workspace/7.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/7.spi_device_rx_timeout.1856437936
Short name	T690
Test name
Test status
Simulation time	690030466 ps
CPU time	5.38 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:33 PM PST 24
Peak memory	216868 kb
Host	smart-d1001526-9c69-4b13-bb8c-93221c94d7c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856437936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_rx_timeout.1856437936
Directory	/workspace/7.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/7.spi_device_smoke.3764604140
Short name	T616
Test name
Test status
Simulation time	149192771 ps
CPU time	0.99 seconds
Started	Jan 07 01:19:17 PM PST 24
Finished	Jan 07 01:19:26 PM PST 24
Peak memory	207944 kb
Host	smart-e1c2ee94-2af5-4d8e-b466-22f91674719d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764604140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_smoke.3764604140
Directory	/workspace/7.spi_device_smoke/latest

Test location	/workspace/coverage/default/7.spi_device_stress_all.390145690
Short name	T1050
Test name
Test status
Simulation time	357413271642 ps
CPU time	483.79 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:27:32 PM PST 24
Peak memory	479048 kb
Host	smart-4251fbc3-d99f-4f35-a8e7-6df8ff273228
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390145690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress _all.390145690
Directory	/workspace/7.spi_device_stress_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_all.1955441964
Short name	T896
Test name
Test status
Simulation time	14403330889 ps
CPU time	22.52 seconds
Started	Jan 07 01:19:20 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	216748 kb
Host	smart-da37dad4-f036-4074-aa30-7bd9662e56ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955441964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1955441964
Directory	/workspace/7.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3111245992
Short name	T551
Test name
Test status
Simulation time	749138699 ps
CPU time	6.08 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:49 PM PST 24
Peak memory	216820 kb
Host	smart-a8dcf458-5eb6-42a4-9ac2-24ce683df413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111245992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3111245992
Directory	/workspace/7.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_rw.733803600
Short name	T1467
Test name
Test status
Simulation time	56543001 ps
CPU time	0.99 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	207888 kb
Host	smart-c559d23e-44e6-47d7-bb50-c2633252b941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733803600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.733803600
Directory	/workspace/7.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_sts_read.2400167207
Short name	T625
Test name
Test status
Simulation time	45335930 ps
CPU time	0.85 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:29 PM PST 24
Peak memory	206928 kb
Host	smart-d818264d-a63e-4f3f-8c55-a6093356097e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400167207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2400167207
Directory	/workspace/7.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.3889019763
Short name	T600
Test name
Test status
Simulation time	135608828 ps
CPU time	0.74 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	208512 kb
Host	smart-994387d1-c5e9-4c4e-a826-51fe74c6004d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889019763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tx_async_fifo_reset.3889019763
Directory	/workspace/7.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/7.spi_device_txrx.1769249717
Short name	T837
Test name
Test status
Simulation time	273022418322 ps
CPU time	501.29 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:28:13 PM PST 24
Peak memory	271072 kb
Host	smart-97a75bc8-05e3-44fe-aeb7-59a0e03083b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769249717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_txrx.1769249717
Directory	/workspace/7.spi_device_txrx/latest

Test location	/workspace/coverage/default/7.spi_device_upload.3142505826
Short name	T1328
Test name
Test status
Simulation time	12575190563 ps
CPU time	23.33 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:20:06 PM PST 24
Peak memory	250740 kb
Host	smart-0b5dea94-db4e-4b1d-afd3-614762643f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142505826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3142505826
Directory	/workspace/7.spi_device_upload/latest

Test location	/workspace/coverage/default/8.spi_device_abort.3071360183
Short name	T492
Test name
Test status
Simulation time	15504399 ps
CPU time	0.75 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:19:53 PM PST 24
Peak memory	206672 kb
Host	smart-abb99b29-459c-4530-955c-ca5cc1f42bc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071360183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_abort.3071360183
Directory	/workspace/8.spi_device_abort/latest

Test location	/workspace/coverage/default/8.spi_device_alert_test.1124715938
Short name	T764
Test name
Test status
Simulation time	14560868 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:19:42 PM PST 24
Peak memory	206552 kb
Host	smart-2bac1727-02ea-464f-bcc2-41e715e50bbc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124715938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1 124715938
Directory	/workspace/8.spi_device_alert_test/latest

Test location	/workspace/coverage/default/8.spi_device_bit_transfer.536605935
Short name	T1273
Test name
Test status
Simulation time	617466805 ps
CPU time	2.76 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:20:00 PM PST 24
Peak memory	216788 kb
Host	smart-e1b41e98-79ab-4bc5-93e2-802b29e3be82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536605935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_bit_transfer.536605935
Directory	/workspace/8.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/8.spi_device_byte_transfer.1606564544
Short name	T761
Test name
Test status
Simulation time	570213903 ps
CPU time	2.51 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:19:31 PM PST 24
Peak memory	216836 kb
Host	smart-9bae5d44-5d12-4284-a767-d43b8fdf3d3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606564544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_byte_transfer.1606564544
Directory	/workspace/8.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/8.spi_device_cfg_cmd.1369758072
Short name	T280
Test name
Test status
Simulation time	943165482 ps
CPU time	5.03 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:56 PM PST 24
Peak memory	221008 kb
Host	smart-53452957-5856-4461-bc1d-6d99b3aaf71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369758072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1369758072
Directory	/workspace/8.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/8.spi_device_csb_read.2160564075
Short name	T1260
Test name
Test status
Simulation time	82515350 ps
CPU time	0.74 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:50 PM PST 24
Peak memory	206556 kb
Host	smart-4ed5e416-1128-4c9e-bdde-8b66bfaac16a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160564075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2160564075
Directory	/workspace/8.spi_device_csb_read/latest

Test location	/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.3656345413
Short name	T961
Test name
Test status
Simulation time	59409104323 ps
CPU time	579.15 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:29:23 PM PST 24
Peak memory	254780 kb
Host	smart-8584f427-d03a-42ac-8e35-5064bd3c9e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656345413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_dummy_item_extra_dly.3656345413
Directory	/workspace/8.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/8.spi_device_extreme_fifo_size.1159096840
Short name	T976
Test name
Test status
Simulation time	235803523079 ps
CPU time	1065.9 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:37:29 PM PST 24
Peak memory	225160 kb
Host	smart-faf7b496-6b0a-44c3-8b49-6503b62edcc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159096840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_extreme_fifo_size.1159096840
Directory	/workspace/8.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/8.spi_device_fifo_full.3304435148
Short name	T484
Test name
Test status
Simulation time	27667520175 ps
CPU time	430.28 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:26:38 PM PST 24
Peak memory	282244 kb
Host	smart-ad7be806-3a49-420a-95ab-1895dcf87b3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304435148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_full.3304435148
Directory	/workspace/8.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.3077604315
Short name	T726
Test name
Test status
Simulation time	50857285483 ps
CPU time	148.85 seconds
Started	Jan 07 01:19:19 PM PST 24
Finished	Jan 07 01:21:57 PM PST 24
Peak memory	349176 kb
Host	smart-5d51ec8f-9fb8-4094-9b1c-5dd14412ba3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077604315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_fifo_underflow_overfl ow.3077604315
Directory	/workspace/8.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/8.spi_device_flash_all.3664742671
Short name	T1243
Test name
Test status
Simulation time	3798720742 ps
CPU time	19.66 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:19 PM PST 24
Peak memory	225220 kb
Host	smart-02e49638-a4a2-468b-9a77-90ffd3910b86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664742671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3664742671
Directory	/workspace/8.spi_device_flash_all/latest

Test location	/workspace/coverage/default/8.spi_device_flash_and_tpm.2739561018
Short name	T1293
Test name
Test status
Simulation time	85976779592 ps
CPU time	553.42 seconds
Started	Jan 07 01:20:01 PM PST 24
Finished	Jan 07 01:29:25 PM PST 24
Peak memory	266388 kb
Host	smart-7ff892de-bfe5-446f-9b96-58e0469d3ff0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739561018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2739561018
Directory	/workspace/8.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/8.spi_device_flash_mode.3002629712
Short name	T333
Test name
Test status
Simulation time	2093557359 ps
CPU time	11.6 seconds
Started	Jan 07 01:19:49 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	248892 kb
Host	smart-6447d1b4-744f-4c38-aab8-aee9b1812017
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002629712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3002629712
Directory	/workspace/8.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/8.spi_device_intercept.3450857792
Short name	T94
Test name
Test status
Simulation time	510027116 ps
CPU time	2.52 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:19:55 PM PST 24
Peak memory	218520 kb
Host	smart-6f3adb76-240e-4dce-ac87-c92c8a8ae8bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450857792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3450857792
Directory	/workspace/8.spi_device_intercept/latest

Test location	/workspace/coverage/default/8.spi_device_intr.1706996849
Short name	T59
Test name
Test status
Simulation time	11958576485 ps
CPU time	43.28 seconds
Started	Jan 07 01:19:48 PM PST 24
Finished	Jan 07 01:20:43 PM PST 24
Peak memory	221356 kb
Host	smart-721a29d1-8879-4db7-9cbb-303d35a54298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706996849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intr.1706996849
Directory	/workspace/8.spi_device_intr/latest

Test location	/workspace/coverage/default/8.spi_device_mem_parity.3387982527
Short name	T1346
Test name
Test status
Simulation time	45983100 ps
CPU time	1.04 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:19:51 PM PST 24
Peak memory	218944 kb
Host	smart-8d5200fb-e0f8-4743-b6c7-b94914de73a5
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387982527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.spi_device_mem_parity.3387982527
Directory	/workspace/8.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.872336174
Short name	T924
Test name
Test status
Simulation time	484892260 ps
CPU time	2.25 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:53 PM PST 24
Peak memory	218228 kb
Host	smart-851687af-8379-4a51-9f9a-4a3c9e6dd498
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872336174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap. 872336174
Directory	/workspace/8.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/8.spi_device_pass_cmd_filtering.2095745335
Short name	T1059
Test name
Test status
Simulation time	6163886495 ps
CPU time	19.78 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:20:11 PM PST 24
Peak memory	248140 kb
Host	smart-7e5d5fd6-7450-4e7b-b93b-7d7e80443eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095745335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2095745335
Directory	/workspace/8.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/8.spi_device_perf.2201545925
Short name	T874
Test name
Test status
Simulation time	10561391001 ps
CPU time	646.69 seconds
Started	Jan 07 01:19:21 PM PST 24
Finished	Jan 07 01:30:15 PM PST 24
Peak memory	284208 kb
Host	smart-25d10d3f-1549-4bb4-b52c-d0fd6e094f30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201545925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_perf.2201545925
Directory	/workspace/8.spi_device_perf/latest

Test location	/workspace/coverage/default/8.spi_device_ram_cfg.3700772421
Short name	T1745
Test name
Test status
Simulation time	16192539 ps
CPU time	0.74 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	216680 kb
Host	smart-b0d0d83b-aaaf-4a2a-84db-9d86c1e73df9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700772421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3700772421
Directory	/workspace/8.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/8.spi_device_read_buffer_direct.2115969179
Short name	T540
Test name
Test status
Simulation time	1279269101 ps
CPU time	4.47 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:20:02 PM PST 24
Peak memory	218708 kb
Host	smart-2230f039-de83-4116-a225-d380753f490d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2115969179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire ct.2115969179
Directory	/workspace/8.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.495590557
Short name	T1315
Test name
Test status
Simulation time	151831466 ps
CPU time	0.98 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	208296 kb
Host	smart-2f3cecf5-0a70-489c-9c82-d848cfdd3806
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495590557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_async_fifo_reset.495590557
Directory	/workspace/8.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/8.spi_device_rx_timeout.4230839509
Short name	T694
Test name
Test status
Simulation time	2319409609 ps
CPU time	5.63 seconds
Started	Jan 07 01:19:22 PM PST 24
Finished	Jan 07 01:19:34 PM PST 24
Peak memory	216884 kb
Host	smart-41692ef3-7747-4a60-b81e-518e84e94f43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230839509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_rx_timeout.4230839509
Directory	/workspace/8.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/8.spi_device_smoke.2242447898
Short name	T870
Test name
Test status
Simulation time	75937620 ps
CPU time	1.1 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	216508 kb
Host	smart-c109fe41-1542-4261-abef-ab4f7fa5cc8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242447898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_smoke.2242447898
Directory	/workspace/8.spi_device_smoke/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_all.3164057946
Short name	T507
Test name
Test status
Simulation time	3891489739 ps
CPU time	40.5 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:20:32 PM PST 24
Peak memory	217056 kb
Host	smart-06b1f7f3-5c92-4593-8fa6-f0bfdedfeb70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164057946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3164057946
Directory	/workspace/8.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3526224313
Short name	T662
Test name
Test status
Simulation time	1400989205 ps
CPU time	4.94 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:19:57 PM PST 24
Peak memory	216796 kb
Host	smart-101aa91d-b959-4874-8262-f456bc9c3536
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526224313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3526224313
Directory	/workspace/8.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_rw.1376122342
Short name	T1562
Test name
Test status
Simulation time	646252749 ps
CPU time	3.77 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:19:56 PM PST 24
Peak memory	216828 kb
Host	smart-61b10d1c-f6c8-4186-bb6e-a9e4a7975a62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376122342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1376122342
Directory	/workspace/8.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_sts_read.604057513
Short name	T1213
Test name
Test status
Simulation time	202809168 ps
CPU time	0.89 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:19:54 PM PST 24
Peak memory	208048 kb
Host	smart-e41bf77e-33a8-4e98-9b63-eb39ae4ff411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604057513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.604057513
Directory	/workspace/8.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.1330295159
Short name	T604
Test name
Test status
Simulation time	43778839 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:43 PM PST 24
Finished	Jan 07 01:19:57 PM PST 24
Peak memory	208460 kb
Host	smart-eb96ce38-9a9a-4be6-8f34-17887bcf2409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330295159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tx_async_fifo_reset.1330295159
Directory	/workspace/8.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/8.spi_device_txrx.3089933978
Short name	T445
Test name
Test status
Simulation time	207637092980 ps
CPU time	544.08 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:28:55 PM PST 24
Peak memory	265256 kb
Host	smart-f9f66832-7c58-4dab-8cc2-54b66a403925
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089933978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_txrx.3089933978
Directory	/workspace/8.spi_device_txrx/latest

Test location	/workspace/coverage/default/8.spi_device_upload.4293979999
Short name	T1614
Test name
Test status
Simulation time	6903876666 ps
CPU time	15.19 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:20:12 PM PST 24
Peak memory	233352 kb
Host	smart-5a54228e-e63f-4eeb-bcbc-28a7f6086bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293979999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4293979999
Directory	/workspace/8.spi_device_upload/latest

Test location	/workspace/coverage/default/9.spi_device_abort.1533168671
Short name	T589
Test name
Test status
Simulation time	16722380 ps
CPU time	0.72 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:43 PM PST 24
Peak memory	206548 kb
Host	smart-5c355f80-2e21-47f3-baa7-2086f456d5fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533168671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_abort_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_abort.1533168671
Directory	/workspace/9.spi_device_abort/latest

Test location	/workspace/coverage/default/9.spi_device_alert_test.3846461775
Short name	T773
Test name
Test status
Simulation time	14468554 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:19:56 PM PST 24
Peak memory	206496 kb
Host	smart-a694d589-19f9-4f0c-85ec-0778d337949a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846461775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3 846461775
Directory	/workspace/9.spi_device_alert_test/latest

Test location	/workspace/coverage/default/9.spi_device_bit_transfer.1455251996
Short name	T517
Test name
Test status
Simulation time	773184370 ps
CPU time	2.55 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	216876 kb
Host	smart-764dba93-bb83-4db2-84ec-b1596d861f90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455251996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_bit_transfer.1455251996
Directory	/workspace/9.spi_device_bit_transfer/latest

Test location	/workspace/coverage/default/9.spi_device_byte_transfer.4004860710
Short name	T1547
Test name
Test status
Simulation time	140834530 ps
CPU time	2.96 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	216876 kb
Host	smart-05498d81-8782-45f5-bae7-adbf1e12e6b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004860710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_byte_transfer_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_byte_transfer.4004860710
Directory	/workspace/9.spi_device_byte_transfer/latest

Test location	/workspace/coverage/default/9.spi_device_cfg_cmd.525027042
Short name	T1584
Test name
Test status
Simulation time	896861775 ps
CPU time	5.04 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:47 PM PST 24
Peak memory	225040 kb
Host	smart-6913087e-dd69-4296-a39c-c45cbd7f1331
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525027042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.525027042
Directory	/workspace/9.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/9.spi_device_csb_read.9926429
Short name	T979
Test name
Test status
Simulation time	32793884 ps
CPU time	0.76 seconds
Started	Jan 07 01:19:39 PM PST 24
Finished	Jan 07 01:19:52 PM PST 24
Peak memory	206560 kb
Host	smart-e8f6a60c-0045-4198-8e51-2b8093e2340e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9926429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.9926429
Directory	/workspace/9.spi_device_csb_read/latest

Test location	/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.3238747158
Short name	T660
Test name
Test status
Simulation time	411894173909 ps
CPU time	327.38 seconds
Started	Jan 07 01:19:40 PM PST 24
Finished	Jan 07 01:25:20 PM PST 24
Peak memory	266200 kb
Host	smart-9174f443-7017-48c8-83f7-237b9b9dce2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238747158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_dummy_item_extra_dly_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_dummy_item_extra_dly.3238747158
Directory	/workspace/9.spi_device_dummy_item_extra_dly/latest

Test location	/workspace/coverage/default/9.spi_device_extreme_fifo_size.3069306240
Short name	T92
Test name
Test status
Simulation time	397916569107 ps
CPU time	974.29 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:35:52 PM PST 24
Peak memory	225232 kb
Host	smart-5ad7a5a5-34dd-46be-ade1-7f5ba87db627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069306240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_extreme_fifo_size_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_extreme_fifo_size.3069306240
Directory	/workspace/9.spi_device_extreme_fifo_size/latest

Test location	/workspace/coverage/default/9.spi_device_fifo_full.724486725
Short name	T1638
Test name
Test status
Simulation time	55885220879 ps
CPU time	1537.05 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:45:32 PM PST 24
Peak memory	312304 kb
Host	smart-3fa91853-27eb-4fab-9319-18004bf66067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724486725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_full_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_full.724486725
Directory	/workspace/9.spi_device_fifo_full/latest

Test location	/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.3923002728
Short name	T1002
Test name
Test status
Simulation time	27465889419 ps
CPU time	209.36 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:23:08 PM PST 24
Peak memory	348312 kb
Host	smart-27688553-586c-46f5-8d92-8828ab641860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923002728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_fifo_underflow_overflow_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_fifo_underflow_overfl ow.3923002728
Directory	/workspace/9.spi_device_fifo_underflow_overflow/latest

Test location	/workspace/coverage/default/9.spi_device_flash_all.3524537988
Short name	T827
Test name
Test status
Simulation time	205848118012 ps
CPU time	250.41 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:23:54 PM PST 24
Peak memory	257992 kb
Host	smart-ea47aab0-09be-41c3-8277-6e2f9d1c8113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524537988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3524537988
Directory	/workspace/9.spi_device_flash_all/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm.3495884959
Short name	T318
Test name
Test status
Simulation time	35829063511 ps
CPU time	296.4 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:24:38 PM PST 24
Peak memory	272700 kb
Host	smart-5c112e9a-c8e2-4be7-bf97-45553c91e5d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495884959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3495884959
Directory	/workspace/9.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2131089667
Short name	T574
Test name
Test status
Simulation time	10308300125 ps
CPU time	96.04 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:21:30 PM PST 24
Peak memory	250108 kb
Host	smart-9e44f161-8ca5-4fdd-8367-1a9c79c4db1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131089667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle .2131089667
Directory	/workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/9.spi_device_flash_mode.1760078214
Short name	T722
Test name
Test status
Simulation time	34156581869 ps
CPU time	44.59 seconds
Started	Jan 07 01:19:43 PM PST 24
Finished	Jan 07 01:20:41 PM PST 24
Peak memory	240916 kb
Host	smart-b8f48bdb-2ba4-4e02-87dd-9b521a1ecc56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760078214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1760078214
Directory	/workspace/9.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/9.spi_device_intercept.2197698277
Short name	T1718
Test name
Test status
Simulation time	12685947307 ps
CPU time	10.91 seconds
Started	Jan 07 01:19:43 PM PST 24
Finished	Jan 07 01:20:07 PM PST 24
Peak memory	239712 kb
Host	smart-b24276f5-6d51-4f14-be28-934de93f78ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197698277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2197698277
Directory	/workspace/9.spi_device_intercept/latest

Test location	/workspace/coverage/default/9.spi_device_intr.3796502946
Short name	T1077
Test name
Test status
Simulation time	19012685695 ps
CPU time	28.93 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:20:19 PM PST 24
Peak memory	233156 kb
Host	smart-befd1fd9-bf34-46e3-b7f1-02cc2b0dfabb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796502946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intr_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intr.3796502946
Directory	/workspace/9.spi_device_intr/latest

Test location	/workspace/coverage/default/9.spi_device_mailbox.259323214
Short name	T1746
Test name
Test status
Simulation time	1253795402 ps
CPU time	6.17 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:43 PM PST 24
Peak memory	249732 kb
Host	smart-094939c5-d492-4ebf-a605-044803ab0a31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259323214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.259323214
Directory	/workspace/9.spi_device_mailbox/latest

Test location	/workspace/coverage/default/9.spi_device_mem_parity.3019118844
Short name	T42
Test name
Test status
Simulation time	97729296 ps
CPU time	1.04 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:19:55 PM PST 24
Peak memory	218936 kb
Host	smart-3ef3d236-0b33-4bd1-82d0-aa9a8ac80c4f
User	root
Command	/workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019118844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.spi_device_mem_parity.3019118844
Directory	/workspace/9.spi_device_mem_parity/latest

Test location	/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3676431962
Short name	T708
Test name
Test status
Simulation time	270324169 ps
CPU time	4.26 seconds
Started	Jan 07 01:19:37 PM PST 24
Finished	Jan 07 01:19:52 PM PST 24
Peak memory	238952 kb
Host	smart-e30b9d09-10c8-422a-bb81-2ee79140a0f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676431962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap .3676431962
Directory	/workspace/9.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/9.spi_device_pass_cmd_filtering.3531942418
Short name	T240
Test name
Test status
Simulation time	15559205927 ps
CPU time	18.68 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:20:01 PM PST 24
Peak memory	228756 kb
Host	smart-12a03fc4-1d2d-46b1-84f0-1d68311e2f68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531942418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3531942418
Directory	/workspace/9.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/9.spi_device_perf.1955637745
Short name	T1528
Test name
Test status
Simulation time	10756444005 ps
CPU time	306.43 seconds
Started	Jan 07 01:19:44 PM PST 24
Finished	Jan 07 01:25:04 PM PST 24
Peak memory	277044 kb
Host	smart-d16d6df9-ca87-41aa-96d9-95da347ab9f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955637745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_perf_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_perf.1955637745
Directory	/workspace/9.spi_device_perf/latest

Test location	/workspace/coverage/default/9.spi_device_ram_cfg.1559259684
Short name	T1498
Test name
Test status
Simulation time	42912838 ps
CPU time	0.71 seconds
Started	Jan 07 01:19:42 PM PST 24
Finished	Jan 07 01:19:56 PM PST 24
Peak memory	216736 kb
Host	smart-220a558b-f182-4eff-a4ac-67b4e26f3fe9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559259684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1559259684
Directory	/workspace/9.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/9.spi_device_read_buffer_direct.1005027206
Short name	T1015
Test name
Test status
Simulation time	2205801168 ps
CPU time	4.5 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:19:58 PM PST 24
Peak memory	220012 kb
Host	smart-8c89d2cf-93b0-4ba4-9a1d-3b8366b03bfb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1005027206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.1005027206
Directory	/workspace/9.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.4292215982
Short name	T1142
Test name
Test status
Simulation time	15236345 ps
CPU time	0.84 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:19:39 PM PST 24
Peak memory	208424 kb
Host	smart-f4b8a360-e869-4f03-bbbb-3028cb57b09d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292215982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_async_fifo_reset.4292215982
Directory	/workspace/9.spi_device_rx_async_fifo_reset/latest

Test location	/workspace/coverage/default/9.spi_device_rx_timeout.2993089635
Short name	T1733
Test name
Test status
Simulation time	1331217204 ps
CPU time	5.53 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:19:44 PM PST 24
Peak memory	216788 kb
Host	smart-449c1b59-3728-432f-abf2-423d3fbc0237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993089635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_rx_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_rx_timeout.2993089635
Directory	/workspace/9.spi_device_rx_timeout/latest

Test location	/workspace/coverage/default/9.spi_device_smoke.30858030
Short name	T1685
Test name
Test status
Simulation time	257151598 ps
CPU time	0.87 seconds
Started	Jan 07 01:19:33 PM PST 24
Finished	Jan 07 01:19:37 PM PST 24
Peak memory	207800 kb
Host	smart-eac2e117-8d12-4aeb-b40a-2cc7275dedaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30858030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_smoke.30858030
Directory	/workspace/9.spi_device_smoke/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_all.1993132168
Short name	T1221
Test name
Test status
Simulation time	5096557181 ps
CPU time	26.42 seconds
Started	Jan 07 01:19:46 PM PST 24
Finished	Jan 07 01:20:24 PM PST 24
Peak memory	217000 kb
Host	smart-100456b1-3c3e-4b39-894d-96076c3b7b53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993132168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1993132168
Directory	/workspace/9.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.478801453
Short name	T780
Test name
Test status
Simulation time	35294977 ps
CPU time	1.01 seconds
Started	Jan 07 01:19:36 PM PST 24
Finished	Jan 07 01:19:43 PM PST 24
Peak memory	207040 kb
Host	smart-e7d1889d-864b-405d-9e06-3d3cf2e786eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478801453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.478801453
Directory	/workspace/9.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_rw.633210955
Short name	T709
Test name
Test status
Simulation time	113080382 ps
CPU time	1.62 seconds
Started	Jan 07 01:19:41 PM PST 24
Finished	Jan 07 01:19:55 PM PST 24
Peak memory	216860 kb
Host	smart-a932428b-35cc-4dba-be31-b578f62a0db7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633210955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.633210955
Directory	/workspace/9.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_sts_read.2498894469
Short name	T542
Test name
Test status
Simulation time	161905955 ps
CPU time	1.03 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	208052 kb
Host	smart-6c136be5-0c3e-4b74-9faf-7802c14bdb3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498894469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2498894469
Directory	/workspace/9.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2359106590
Short name	T696
Test name
Test status
Simulation time	253826292 ps
CPU time	0.77 seconds
Started	Jan 07 01:19:34 PM PST 24
Finished	Jan 07 01:19:38 PM PST 24
Peak memory	208376 kb
Host	smart-db56d36b-9930-49d0-96d0-0a32e145c96d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359106590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tx_async_fifo_reset_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tx_async_fifo_reset.2359106590
Directory	/workspace/9.spi_device_tx_async_fifo_reset/latest

Test location	/workspace/coverage/default/9.spi_device_txrx.589471119
Short name	T1668
Test name
Test status
Simulation time	30951860322 ps
CPU time	147.24 seconds
Started	Jan 07 01:19:35 PM PST 24
Finished	Jan 07 01:22:08 PM PST 24
Peak memory	254812 kb
Host	smart-1886b0b3-fdd6-4530-bed7-165e298f55a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589471119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_txrx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_txrx.589471119
Directory	/workspace/9.spi_device_txrx/latest

Test location	/workspace/coverage/default/9.spi_device_upload.3754525415
Short name	T266
Test name
Test status
Simulation time	18065149567 ps
CPU time	20.77 seconds
Started	Jan 07 01:19:38 PM PST 24
Finished	Jan 07 01:20:10 PM PST 24
Peak memory	248660 kb
Host	smart-85c33313-d04a-47d3-a361-7107f1c602d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754525415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3754525415
Directory	/workspace/9.spi_device_upload/latest

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