Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	8524853	1			T3	3168		T4	3905		T6	24
all_values[1]	8524853	1			T3	3168		T4	3905		T6	24
all_values[2]	8524853	1			T3	3168		T4	3905		T6	24
all_values[3]	8524853	1			T3	3168		T4	3905		T6	24
all_values[4]	8524853	1			T3	3168		T4	3905		T6	24
all_values[5]	8524853	1			T3	3168		T4	3905		T6	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49745534

1

T3

19008

T4

23430

T6

144

auto[1]

1403584

1

T48

25

T49

86

T50

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51070039

1

T3

19008

T4

23430

T6

140

auto[1]

79079

1

T6

4

T7

1729

T23

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	8207120	1			T3	3168		T4	3905		T6	24
all_values[0]	auto[0]	auto[1]	43597	1			T7	991		T11	249		T12	642
all_values[0]	auto[1]	auto[0]	271850	1			T48	3		T49	6		T50	5
all_values[0]	auto[1]	auto[1]	2286	1			T48	1		T49	3		T50	5
all_values[1]	auto[0]	auto[0]	8290787	1			T3	3168		T4	3905		T6	24
all_values[1]	auto[0]	auto[1]	22658	1			T7	592		T11	34		T12	270
all_values[1]	auto[1]	auto[0]	210450	1			T48	5		T49	13		T50	9
all_values[1]	auto[1]	auto[1]	958	1			T49	7		T50	6		T51	2
all_values[2]	auto[0]	auto[0]	8339954	1			T3	3168		T4	3905		T6	24
all_values[2]	auto[0]	auto[1]	7672	1			T7	146		T11	26		T12	47
all_values[2]	auto[1]	auto[0]	176708	1			T49	12		T50	7		T51	3
all_values[2]	auto[1]	auto[1]	519	1			T48	2		T49	5		T50	2
all_values[3]	auto[0]	auto[0]	8258580	1			T3	3168		T4	3905		T6	24
all_values[3]	auto[0]	auto[1]	196	1			T48	3		T49	9		T120	1
all_values[3]	auto[1]	auto[0]	265888	1			T48	3		T49	8		T50	12
all_values[3]	auto[1]	auto[1]	189	1			T48	1		T49	6		T50	1
all_values[4]	auto[0]	auto[0]	8362141	1			T3	3168		T4	3905		T6	24
all_values[4]	auto[0]	auto[1]	212	1			T48	3		T49	3		T120	1
all_values[4]	auto[1]	auto[0]	162302	1			T48	2		T49	12		T50	6
all_values[4]	auto[1]	auto[1]	198	1			T48	2		T49	8		T50	5
all_values[5]	auto[0]	auto[0]	8212206	1			T3	3168		T4	3905		T6	20
all_values[5]	auto[0]	auto[1]	411	1			T6	4		T23	4		T48	3
all_values[5]	auto[1]	auto[0]	312053	1			T48	5		T49	4		T50	2
all_values[5]	auto[1]	auto[1]	183	1			T48	1		T49	2		T50	5